1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Tegra host1x driver 4 * 5 * Copyright (c) 2010-2013, NVIDIA Corporation. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/io.h> 11 #include <linux/list.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/of.h> 15 #include <linux/slab.h> 16 17 #define CREATE_TRACE_POINTS 18 #include <trace/events/host1x.h> 19 #undef CREATE_TRACE_POINTS 20 21 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 22 #include <asm/dma-iommu.h> 23 #endif 24 25 #include "bus.h" 26 #include "channel.h" 27 #include "debug.h" 28 #include "dev.h" 29 #include "intr.h" 30 31 #include "hw/host1x01.h" 32 #include "hw/host1x02.h" 33 #include "hw/host1x04.h" 34 #include "hw/host1x05.h" 35 #include "hw/host1x06.h" 36 #include "hw/host1x07.h" 37 38 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r) 39 { 40 writel(v, host1x->hv_regs + r); 41 } 42 43 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r) 44 { 45 return readl(host1x->hv_regs + r); 46 } 47 48 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r) 49 { 50 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 51 52 writel(v, sync_regs + r); 53 } 54 55 u32 host1x_sync_readl(struct host1x *host1x, u32 r) 56 { 57 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 58 59 return readl(sync_regs + r); 60 } 61 62 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r) 63 { 64 writel(v, ch->regs + r); 65 } 66 67 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r) 68 { 69 return readl(ch->regs + r); 70 } 71 72 static const struct host1x_info host1x01_info = { 73 .nb_channels = 8, 74 .nb_pts = 32, 75 .nb_mlocks = 16, 76 .nb_bases = 8, 77 .init = host1x01_init, 78 .sync_offset = 0x3000, 79 .dma_mask = DMA_BIT_MASK(32), 80 }; 81 82 static const struct host1x_info host1x02_info = { 83 .nb_channels = 9, 84 .nb_pts = 32, 85 .nb_mlocks = 16, 86 .nb_bases = 12, 87 .init = host1x02_init, 88 .sync_offset = 0x3000, 89 .dma_mask = DMA_BIT_MASK(32), 90 }; 91 92 static const struct host1x_info host1x04_info = { 93 .nb_channels = 12, 94 .nb_pts = 192, 95 .nb_mlocks = 16, 96 .nb_bases = 64, 97 .init = host1x04_init, 98 .sync_offset = 0x2100, 99 .dma_mask = DMA_BIT_MASK(34), 100 }; 101 102 static const struct host1x_info host1x05_info = { 103 .nb_channels = 14, 104 .nb_pts = 192, 105 .nb_mlocks = 16, 106 .nb_bases = 64, 107 .init = host1x05_init, 108 .sync_offset = 0x2100, 109 .dma_mask = DMA_BIT_MASK(34), 110 }; 111 112 static const struct host1x_sid_entry tegra186_sid_table[] = { 113 { 114 /* VIC */ 115 .base = 0x1af0, 116 .offset = 0x30, 117 .limit = 0x34 118 }, 119 }; 120 121 static const struct host1x_info host1x06_info = { 122 .nb_channels = 63, 123 .nb_pts = 576, 124 .nb_mlocks = 24, 125 .nb_bases = 16, 126 .init = host1x06_init, 127 .sync_offset = 0x0, 128 .dma_mask = DMA_BIT_MASK(40), 129 .has_hypervisor = true, 130 .num_sid_entries = ARRAY_SIZE(tegra186_sid_table), 131 .sid_table = tegra186_sid_table, 132 }; 133 134 static const struct host1x_sid_entry tegra194_sid_table[] = { 135 { 136 /* VIC */ 137 .base = 0x1af0, 138 .offset = 0x30, 139 .limit = 0x34 140 }, 141 }; 142 143 static const struct host1x_info host1x07_info = { 144 .nb_channels = 63, 145 .nb_pts = 704, 146 .nb_mlocks = 32, 147 .nb_bases = 0, 148 .init = host1x07_init, 149 .sync_offset = 0x0, 150 .dma_mask = DMA_BIT_MASK(40), 151 .has_hypervisor = true, 152 .num_sid_entries = ARRAY_SIZE(tegra194_sid_table), 153 .sid_table = tegra194_sid_table, 154 }; 155 156 static const struct of_device_id host1x_of_match[] = { 157 { .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, }, 158 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, }, 159 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, }, 160 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, }, 161 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, }, 162 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, 163 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, 164 { }, 165 }; 166 MODULE_DEVICE_TABLE(of, host1x_of_match); 167 168 static void host1x_setup_sid_table(struct host1x *host) 169 { 170 const struct host1x_info *info = host->info; 171 unsigned int i; 172 173 for (i = 0; i < info->num_sid_entries; i++) { 174 const struct host1x_sid_entry *entry = &info->sid_table[i]; 175 176 host1x_hypervisor_writel(host, entry->offset, entry->base); 177 host1x_hypervisor_writel(host, entry->limit, entry->base + 4); 178 } 179 } 180 181 static int host1x_probe(struct platform_device *pdev) 182 { 183 struct host1x *host; 184 struct resource *regs, *hv_regs = NULL; 185 int syncpt_irq; 186 int err; 187 188 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 189 if (!host) 190 return -ENOMEM; 191 192 host->info = of_device_get_match_data(&pdev->dev); 193 194 if (host->info->has_hypervisor) { 195 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm"); 196 if (!regs) { 197 dev_err(&pdev->dev, "failed to get vm registers\n"); 198 return -ENXIO; 199 } 200 201 hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, 202 "hypervisor"); 203 if (!hv_regs) { 204 dev_err(&pdev->dev, 205 "failed to get hypervisor registers\n"); 206 return -ENXIO; 207 } 208 } else { 209 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 210 if (!regs) { 211 dev_err(&pdev->dev, "failed to get registers\n"); 212 return -ENXIO; 213 } 214 } 215 216 syncpt_irq = platform_get_irq(pdev, 0); 217 if (syncpt_irq < 0) { 218 dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq); 219 return syncpt_irq; 220 } 221 222 mutex_init(&host->devices_lock); 223 INIT_LIST_HEAD(&host->devices); 224 INIT_LIST_HEAD(&host->list); 225 host->dev = &pdev->dev; 226 227 /* set common host1x device data */ 228 platform_set_drvdata(pdev, host); 229 230 host->regs = devm_ioremap_resource(&pdev->dev, regs); 231 if (IS_ERR(host->regs)) 232 return PTR_ERR(host->regs); 233 234 if (host->info->has_hypervisor) { 235 host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs); 236 if (IS_ERR(host->hv_regs)) 237 return PTR_ERR(host->hv_regs); 238 } 239 240 dma_set_mask_and_coherent(host->dev, host->info->dma_mask); 241 242 if (host->info->init) { 243 err = host->info->init(host); 244 if (err) 245 return err; 246 } 247 248 host->clk = devm_clk_get(&pdev->dev, NULL); 249 if (IS_ERR(host->clk)) { 250 dev_err(&pdev->dev, "failed to get clock\n"); 251 err = PTR_ERR(host->clk); 252 return err; 253 } 254 255 host->rst = devm_reset_control_get(&pdev->dev, "host1x"); 256 if (IS_ERR(host->rst)) { 257 err = PTR_ERR(host->rst); 258 dev_err(&pdev->dev, "failed to get reset: %d\n", err); 259 return err; 260 } 261 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 262 if (host->dev->archdata.mapping) { 263 struct dma_iommu_mapping *mapping = 264 to_dma_iommu_mapping(host->dev); 265 arm_iommu_detach_device(host->dev); 266 arm_iommu_release_mapping(mapping); 267 } 268 #endif 269 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) 270 goto skip_iommu; 271 272 host->group = iommu_group_get(&pdev->dev); 273 if (host->group) { 274 struct iommu_domain_geometry *geometry; 275 u64 mask = dma_get_mask(host->dev); 276 dma_addr_t start, end; 277 unsigned long order; 278 279 err = iova_cache_get(); 280 if (err < 0) 281 goto put_group; 282 283 host->domain = iommu_domain_alloc(&platform_bus_type); 284 if (!host->domain) { 285 err = -ENOMEM; 286 goto put_cache; 287 } 288 289 err = iommu_attach_group(host->domain, host->group); 290 if (err) { 291 if (err == -ENODEV) { 292 iommu_domain_free(host->domain); 293 host->domain = NULL; 294 iova_cache_put(); 295 iommu_group_put(host->group); 296 host->group = NULL; 297 goto skip_iommu; 298 } 299 300 goto fail_free_domain; 301 } 302 303 geometry = &host->domain->geometry; 304 start = geometry->aperture_start & mask; 305 end = geometry->aperture_end & mask; 306 307 order = __ffs(host->domain->pgsize_bitmap); 308 init_iova_domain(&host->iova, 1UL << order, start >> order); 309 host->iova_end = end; 310 } 311 312 skip_iommu: 313 err = host1x_channel_list_init(&host->channel_list, 314 host->info->nb_channels); 315 if (err) { 316 dev_err(&pdev->dev, "failed to initialize channel list\n"); 317 goto fail_detach_device; 318 } 319 320 err = clk_prepare_enable(host->clk); 321 if (err < 0) { 322 dev_err(&pdev->dev, "failed to enable clock\n"); 323 goto fail_free_channels; 324 } 325 326 err = reset_control_deassert(host->rst); 327 if (err < 0) { 328 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err); 329 goto fail_unprepare_disable; 330 } 331 332 err = host1x_syncpt_init(host); 333 if (err) { 334 dev_err(&pdev->dev, "failed to initialize syncpts\n"); 335 goto fail_reset_assert; 336 } 337 338 err = host1x_intr_init(host, syncpt_irq); 339 if (err) { 340 dev_err(&pdev->dev, "failed to initialize interrupts\n"); 341 goto fail_deinit_syncpt; 342 } 343 344 host1x_debug_init(host); 345 346 if (host->info->has_hypervisor) 347 host1x_setup_sid_table(host); 348 349 err = host1x_register(host); 350 if (err < 0) 351 goto fail_deinit_intr; 352 353 return 0; 354 355 fail_deinit_intr: 356 host1x_intr_deinit(host); 357 fail_deinit_syncpt: 358 host1x_syncpt_deinit(host); 359 fail_reset_assert: 360 reset_control_assert(host->rst); 361 fail_unprepare_disable: 362 clk_disable_unprepare(host->clk); 363 fail_free_channels: 364 host1x_channel_list_free(&host->channel_list); 365 fail_detach_device: 366 if (host->group && host->domain) { 367 put_iova_domain(&host->iova); 368 iommu_detach_group(host->domain, host->group); 369 } 370 fail_free_domain: 371 if (host->domain) 372 iommu_domain_free(host->domain); 373 put_cache: 374 if (host->group) 375 iova_cache_put(); 376 put_group: 377 iommu_group_put(host->group); 378 379 return err; 380 } 381 382 static int host1x_remove(struct platform_device *pdev) 383 { 384 struct host1x *host = platform_get_drvdata(pdev); 385 386 host1x_unregister(host); 387 host1x_intr_deinit(host); 388 host1x_syncpt_deinit(host); 389 reset_control_assert(host->rst); 390 clk_disable_unprepare(host->clk); 391 392 if (host->domain) { 393 put_iova_domain(&host->iova); 394 iommu_detach_group(host->domain, host->group); 395 iommu_domain_free(host->domain); 396 iova_cache_put(); 397 iommu_group_put(host->group); 398 } 399 400 return 0; 401 } 402 403 static struct platform_driver tegra_host1x_driver = { 404 .driver = { 405 .name = "tegra-host1x", 406 .of_match_table = host1x_of_match, 407 }, 408 .probe = host1x_probe, 409 .remove = host1x_remove, 410 }; 411 412 static struct platform_driver * const drivers[] = { 413 &tegra_host1x_driver, 414 &tegra_mipi_driver, 415 }; 416 417 static int __init tegra_host1x_init(void) 418 { 419 int err; 420 421 err = bus_register(&host1x_bus_type); 422 if (err < 0) 423 return err; 424 425 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 426 if (err < 0) 427 bus_unregister(&host1x_bus_type); 428 429 return err; 430 } 431 module_init(tegra_host1x_init); 432 433 static void __exit tegra_host1x_exit(void) 434 { 435 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 436 bus_unregister(&host1x_bus_type); 437 } 438 module_exit(tegra_host1x_exit); 439 440 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 441 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>"); 442 MODULE_DESCRIPTION("Host1x driver for Tegra products"); 443 MODULE_LICENSE("GPL"); 444