1 /* 2 * Tegra host1x driver 3 * 4 * Copyright (c) 2010-2013, NVIDIA Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/io.h> 22 #include <linux/list.h> 23 #include <linux/module.h> 24 #include <linux/of_device.h> 25 #include <linux/of.h> 26 #include <linux/slab.h> 27 28 #define CREATE_TRACE_POINTS 29 #include <trace/events/host1x.h> 30 #undef CREATE_TRACE_POINTS 31 32 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 33 #include <asm/dma-iommu.h> 34 #endif 35 36 #include "bus.h" 37 #include "channel.h" 38 #include "debug.h" 39 #include "dev.h" 40 #include "intr.h" 41 42 #include "hw/host1x01.h" 43 #include "hw/host1x02.h" 44 #include "hw/host1x04.h" 45 #include "hw/host1x05.h" 46 #include "hw/host1x06.h" 47 48 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r) 49 { 50 writel(v, host1x->hv_regs + r); 51 } 52 53 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r) 54 { 55 return readl(host1x->hv_regs + r); 56 } 57 58 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r) 59 { 60 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 61 62 writel(v, sync_regs + r); 63 } 64 65 u32 host1x_sync_readl(struct host1x *host1x, u32 r) 66 { 67 void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset; 68 69 return readl(sync_regs + r); 70 } 71 72 void host1x_ch_writel(struct host1x_channel *ch, u32 v, u32 r) 73 { 74 writel(v, ch->regs + r); 75 } 76 77 u32 host1x_ch_readl(struct host1x_channel *ch, u32 r) 78 { 79 return readl(ch->regs + r); 80 } 81 82 static const struct host1x_info host1x01_info = { 83 .nb_channels = 8, 84 .nb_pts = 32, 85 .nb_mlocks = 16, 86 .nb_bases = 8, 87 .init = host1x01_init, 88 .sync_offset = 0x3000, 89 .dma_mask = DMA_BIT_MASK(32), 90 }; 91 92 static const struct host1x_info host1x02_info = { 93 .nb_channels = 9, 94 .nb_pts = 32, 95 .nb_mlocks = 16, 96 .nb_bases = 12, 97 .init = host1x02_init, 98 .sync_offset = 0x3000, 99 .dma_mask = DMA_BIT_MASK(32), 100 }; 101 102 static const struct host1x_info host1x04_info = { 103 .nb_channels = 12, 104 .nb_pts = 192, 105 .nb_mlocks = 16, 106 .nb_bases = 64, 107 .init = host1x04_init, 108 .sync_offset = 0x2100, 109 .dma_mask = DMA_BIT_MASK(34), 110 }; 111 112 static const struct host1x_info host1x05_info = { 113 .nb_channels = 14, 114 .nb_pts = 192, 115 .nb_mlocks = 16, 116 .nb_bases = 64, 117 .init = host1x05_init, 118 .sync_offset = 0x2100, 119 .dma_mask = DMA_BIT_MASK(34), 120 }; 121 122 static const struct host1x_info host1x06_info = { 123 .nb_channels = 63, 124 .nb_pts = 576, 125 .nb_mlocks = 24, 126 .nb_bases = 16, 127 .init = host1x06_init, 128 .sync_offset = 0x0, 129 .dma_mask = DMA_BIT_MASK(34), 130 .has_hypervisor = true, 131 }; 132 133 static const struct of_device_id host1x_of_match[] = { 134 { .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, }, 135 { .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, }, 136 { .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, }, 137 { .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, }, 138 { .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, }, 139 { .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, }, 140 { }, 141 }; 142 MODULE_DEVICE_TABLE(of, host1x_of_match); 143 144 static int host1x_probe(struct platform_device *pdev) 145 { 146 struct host1x *host; 147 struct resource *regs, *hv_regs = NULL; 148 int syncpt_irq; 149 int err; 150 151 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); 152 if (!host) 153 return -ENOMEM; 154 155 host->info = of_device_get_match_data(&pdev->dev); 156 157 if (host->info->has_hypervisor) { 158 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vm"); 159 if (!regs) { 160 dev_err(&pdev->dev, "failed to get vm registers\n"); 161 return -ENXIO; 162 } 163 164 hv_regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, 165 "hypervisor"); 166 if (!hv_regs) { 167 dev_err(&pdev->dev, 168 "failed to get hypervisor registers\n"); 169 return -ENXIO; 170 } 171 } else { 172 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 173 if (!regs) { 174 dev_err(&pdev->dev, "failed to get registers\n"); 175 return -ENXIO; 176 } 177 } 178 179 syncpt_irq = platform_get_irq(pdev, 0); 180 if (syncpt_irq < 0) { 181 dev_err(&pdev->dev, "failed to get IRQ: %d\n", syncpt_irq); 182 return syncpt_irq; 183 } 184 185 mutex_init(&host->devices_lock); 186 INIT_LIST_HEAD(&host->devices); 187 INIT_LIST_HEAD(&host->list); 188 host->dev = &pdev->dev; 189 190 /* set common host1x device data */ 191 platform_set_drvdata(pdev, host); 192 193 host->regs = devm_ioremap_resource(&pdev->dev, regs); 194 if (IS_ERR(host->regs)) 195 return PTR_ERR(host->regs); 196 197 if (host->info->has_hypervisor) { 198 host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs); 199 if (IS_ERR(host->hv_regs)) 200 return PTR_ERR(host->hv_regs); 201 } 202 203 dma_set_mask_and_coherent(host->dev, host->info->dma_mask); 204 205 if (host->info->init) { 206 err = host->info->init(host); 207 if (err) 208 return err; 209 } 210 211 host->clk = devm_clk_get(&pdev->dev, NULL); 212 if (IS_ERR(host->clk)) { 213 dev_err(&pdev->dev, "failed to get clock\n"); 214 err = PTR_ERR(host->clk); 215 return err; 216 } 217 218 host->rst = devm_reset_control_get(&pdev->dev, "host1x"); 219 if (IS_ERR(host->rst)) { 220 err = PTR_ERR(host->rst); 221 dev_err(&pdev->dev, "failed to get reset: %d\n", err); 222 return err; 223 } 224 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 225 if (host->dev->archdata.mapping) { 226 struct dma_iommu_mapping *mapping = 227 to_dma_iommu_mapping(host->dev); 228 arm_iommu_detach_device(host->dev); 229 arm_iommu_release_mapping(mapping); 230 } 231 #endif 232 if (IS_ENABLED(CONFIG_TEGRA_HOST1X_FIREWALL)) 233 goto skip_iommu; 234 235 host->group = iommu_group_get(&pdev->dev); 236 if (host->group) { 237 struct iommu_domain_geometry *geometry; 238 unsigned long order; 239 240 err = iova_cache_get(); 241 if (err < 0) 242 goto put_group; 243 244 host->domain = iommu_domain_alloc(&platform_bus_type); 245 if (!host->domain) { 246 err = -ENOMEM; 247 goto put_cache; 248 } 249 250 err = iommu_attach_group(host->domain, host->group); 251 if (err) { 252 if (err == -ENODEV) { 253 iommu_domain_free(host->domain); 254 host->domain = NULL; 255 iova_cache_put(); 256 iommu_group_put(host->group); 257 host->group = NULL; 258 goto skip_iommu; 259 } 260 261 goto fail_free_domain; 262 } 263 264 geometry = &host->domain->geometry; 265 266 order = __ffs(host->domain->pgsize_bitmap); 267 init_iova_domain(&host->iova, 1UL << order, 268 geometry->aperture_start >> order); 269 host->iova_end = geometry->aperture_end; 270 } 271 272 skip_iommu: 273 err = host1x_channel_list_init(&host->channel_list, 274 host->info->nb_channels); 275 if (err) { 276 dev_err(&pdev->dev, "failed to initialize channel list\n"); 277 goto fail_detach_device; 278 } 279 280 err = clk_prepare_enable(host->clk); 281 if (err < 0) { 282 dev_err(&pdev->dev, "failed to enable clock\n"); 283 goto fail_free_channels; 284 } 285 286 err = reset_control_deassert(host->rst); 287 if (err < 0) { 288 dev_err(&pdev->dev, "failed to deassert reset: %d\n", err); 289 goto fail_unprepare_disable; 290 } 291 292 err = host1x_syncpt_init(host); 293 if (err) { 294 dev_err(&pdev->dev, "failed to initialize syncpts\n"); 295 goto fail_reset_assert; 296 } 297 298 err = host1x_intr_init(host, syncpt_irq); 299 if (err) { 300 dev_err(&pdev->dev, "failed to initialize interrupts\n"); 301 goto fail_deinit_syncpt; 302 } 303 304 host1x_debug_init(host); 305 306 err = host1x_register(host); 307 if (err < 0) 308 goto fail_deinit_intr; 309 310 return 0; 311 312 fail_deinit_intr: 313 host1x_intr_deinit(host); 314 fail_deinit_syncpt: 315 host1x_syncpt_deinit(host); 316 fail_reset_assert: 317 reset_control_assert(host->rst); 318 fail_unprepare_disable: 319 clk_disable_unprepare(host->clk); 320 fail_free_channels: 321 host1x_channel_list_free(&host->channel_list); 322 fail_detach_device: 323 if (host->group && host->domain) { 324 put_iova_domain(&host->iova); 325 iommu_detach_group(host->domain, host->group); 326 } 327 fail_free_domain: 328 if (host->domain) 329 iommu_domain_free(host->domain); 330 put_cache: 331 if (host->group) 332 iova_cache_put(); 333 put_group: 334 iommu_group_put(host->group); 335 336 return err; 337 } 338 339 static int host1x_remove(struct platform_device *pdev) 340 { 341 struct host1x *host = platform_get_drvdata(pdev); 342 343 host1x_unregister(host); 344 host1x_intr_deinit(host); 345 host1x_syncpt_deinit(host); 346 reset_control_assert(host->rst); 347 clk_disable_unprepare(host->clk); 348 349 if (host->domain) { 350 put_iova_domain(&host->iova); 351 iommu_detach_group(host->domain, host->group); 352 iommu_domain_free(host->domain); 353 iova_cache_put(); 354 iommu_group_put(host->group); 355 } 356 357 return 0; 358 } 359 360 static struct platform_driver tegra_host1x_driver = { 361 .driver = { 362 .name = "tegra-host1x", 363 .of_match_table = host1x_of_match, 364 }, 365 .probe = host1x_probe, 366 .remove = host1x_remove, 367 }; 368 369 static struct platform_driver * const drivers[] = { 370 &tegra_host1x_driver, 371 &tegra_mipi_driver, 372 }; 373 374 static int __init tegra_host1x_init(void) 375 { 376 int err; 377 378 err = bus_register(&host1x_bus_type); 379 if (err < 0) 380 return err; 381 382 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 383 if (err < 0) 384 bus_unregister(&host1x_bus_type); 385 386 return err; 387 } 388 module_init(tegra_host1x_init); 389 390 static void __exit tegra_host1x_exit(void) 391 { 392 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 393 bus_unregister(&host1x_bus_type); 394 } 395 module_exit(tegra_host1x_exit); 396 397 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 398 MODULE_AUTHOR("Terje Bergstrom <tbergstrom@nvidia.com>"); 399 MODULE_DESCRIPTION("Host1x driver for Tegra products"); 400 MODULE_LICENSE("GPL"); 401