1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ZynqMP Display Controller Driver 4 * 5 * Copyright (C) 2017 - 2020 Xilinx, Inc. 6 * 7 * Authors: 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_blend.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_device.h> 18 #include <drm/drm_fb_cma_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_framebuffer.h> 21 #include <drm/drm_managed.h> 22 #include <drm/drm_plane.h> 23 #include <drm/drm_plane_helper.h> 24 #include <drm/drm_vblank.h> 25 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/dma/xilinx_dpdma.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/dmaengine.h> 31 #include <linux/module.h> 32 #include <linux/of.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/spinlock.h> 36 37 #include "zynqmp_disp.h" 38 #include "zynqmp_disp_regs.h" 39 #include "zynqmp_dp.h" 40 #include "zynqmp_dpsub.h" 41 42 /* 43 * Overview 44 * -------- 45 * 46 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video 47 * Buffer Manager, the Video Rendering Pipeline (blender) and the Audio Mixer. 48 * 49 * +------------------------------------------------------------+ 50 * +--------+ | +----------------+ +-----------+ | 51 * | DPDMA | --->| | --> | Video | Video +-------------+ | 52 * | 4x vid | | | | | Rendering | -+--> | | | +------+ 53 * | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 | 54 * +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+ 55 * | | and STC | +-----------+ | | Controller | | +------+ 56 * Live Video --->| | --> | Audio | Audio | |---> | PHY1 | 57 * | | | | Mixer | --+-> | | | +------+ 58 * Live Audio --->| | --> | | || +-------------+ | 59 * | +----------------+ +-----------+ || | 60 * +---------------------------------------||-------------------+ 61 * vv 62 * Blended Video and 63 * Mixed Audio to PL 64 * 65 * Only non-live input from the DPDMA and output to the DisplayPort Source 66 * Controller are currently supported. Interface with the programmable logic 67 * for live streams is not implemented. 68 * 69 * The display controller code creates planes for the DPDMA video and graphics 70 * layers, and a CRTC for the Video Rendering Pipeline. 71 */ 72 73 #define ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS 4 74 #define ZYNQMP_DISP_AV_BUF_NUM_BUFFERS 6 75 76 #define ZYNQMP_DISP_NUM_LAYERS 2 77 #define ZYNQMP_DISP_MAX_NUM_SUB_PLANES 3 78 79 /** 80 * struct zynqmp_disp_format - Display subsystem format information 81 * @drm_fmt: DRM format (4CC) 82 * @buf_fmt: AV buffer format 83 * @bus_fmt: Media bus formats (live formats) 84 * @swap: Flag to swap R & B for RGB formats, and U & V for YUV formats 85 * @sf: Scaling factors for color components 86 */ 87 struct zynqmp_disp_format { 88 u32 drm_fmt; 89 u32 buf_fmt; 90 u32 bus_fmt; 91 bool swap; 92 const u32 *sf; 93 }; 94 95 /** 96 * enum zynqmp_disp_layer_id - Layer identifier 97 * @ZYNQMP_DISP_LAYER_VID: Video layer 98 * @ZYNQMP_DISP_LAYER_GFX: Graphics layer 99 */ 100 enum zynqmp_disp_layer_id { 101 ZYNQMP_DISP_LAYER_VID, 102 ZYNQMP_DISP_LAYER_GFX 103 }; 104 105 /** 106 * enum zynqmp_disp_layer_mode - Layer mode 107 * @ZYNQMP_DISP_LAYER_NONLIVE: non-live (memory) mode 108 * @ZYNQMP_DISP_LAYER_LIVE: live (stream) mode 109 */ 110 enum zynqmp_disp_layer_mode { 111 ZYNQMP_DISP_LAYER_NONLIVE, 112 ZYNQMP_DISP_LAYER_LIVE 113 }; 114 115 /** 116 * struct zynqmp_disp_layer_dma - DMA channel for one data plane of a layer 117 * @chan: DMA channel 118 * @xt: Interleaved DMA descriptor template 119 * @sgl: Data chunk for dma_interleaved_template 120 */ 121 struct zynqmp_disp_layer_dma { 122 struct dma_chan *chan; 123 struct dma_interleaved_template xt; 124 struct data_chunk sgl; 125 }; 126 127 /** 128 * struct zynqmp_disp_layer_info - Static layer information 129 * @formats: Array of supported formats 130 * @num_formats: Number of formats in @formats array 131 * @num_channels: Number of DMA channels 132 */ 133 struct zynqmp_disp_layer_info { 134 const struct zynqmp_disp_format *formats; 135 unsigned int num_formats; 136 unsigned int num_channels; 137 }; 138 139 /** 140 * struct zynqmp_disp_layer - Display layer (DRM plane) 141 * @plane: DRM plane 142 * @id: Layer ID 143 * @disp: Back pointer to struct zynqmp_disp 144 * @info: Static layer information 145 * @dmas: DMA channels 146 * @disp_fmt: Current format information 147 * @drm_fmt: Current DRM format information 148 * @mode: Current operation mode 149 */ 150 struct zynqmp_disp_layer { 151 struct drm_plane plane; 152 enum zynqmp_disp_layer_id id; 153 struct zynqmp_disp *disp; 154 const struct zynqmp_disp_layer_info *info; 155 156 struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES]; 157 158 const struct zynqmp_disp_format *disp_fmt; 159 const struct drm_format_info *drm_fmt; 160 enum zynqmp_disp_layer_mode mode; 161 }; 162 163 /** 164 * struct zynqmp_disp - Display controller 165 * @dev: Device structure 166 * @drm: DRM core 167 * @dpsub: Display subsystem 168 * @crtc: DRM CRTC 169 * @blend.base: Register I/O base address for the blender 170 * @avbuf.base: Register I/O base address for the audio/video buffer manager 171 * @audio.base: Registers I/O base address for the audio mixer 172 * @audio.clk: Audio clock 173 * @audio.clk_from_ps: True of the audio clock comes from PS, false from PL 174 * @layers: Layers (planes) 175 * @event: Pending vblank event request 176 * @pclk: Pixel clock 177 * @pclk_from_ps: True of the video clock comes from PS, false from PL 178 */ 179 struct zynqmp_disp { 180 struct device *dev; 181 struct drm_device *drm; 182 struct zynqmp_dpsub *dpsub; 183 184 struct drm_crtc crtc; 185 186 struct { 187 void __iomem *base; 188 } blend; 189 struct { 190 void __iomem *base; 191 } avbuf; 192 struct { 193 void __iomem *base; 194 struct clk *clk; 195 bool clk_from_ps; 196 } audio; 197 198 struct zynqmp_disp_layer layers[ZYNQMP_DISP_NUM_LAYERS]; 199 200 struct drm_pending_vblank_event *event; 201 202 struct clk *pclk; 203 bool pclk_from_ps; 204 }; 205 206 /* ----------------------------------------------------------------------------- 207 * Audio/Video Buffer Manager 208 */ 209 210 static const u32 scaling_factors_444[] = { 211 ZYNQMP_DISP_AV_BUF_4BIT_SF, 212 ZYNQMP_DISP_AV_BUF_4BIT_SF, 213 ZYNQMP_DISP_AV_BUF_4BIT_SF, 214 }; 215 216 static const u32 scaling_factors_555[] = { 217 ZYNQMP_DISP_AV_BUF_5BIT_SF, 218 ZYNQMP_DISP_AV_BUF_5BIT_SF, 219 ZYNQMP_DISP_AV_BUF_5BIT_SF, 220 }; 221 222 static const u32 scaling_factors_565[] = { 223 ZYNQMP_DISP_AV_BUF_5BIT_SF, 224 ZYNQMP_DISP_AV_BUF_6BIT_SF, 225 ZYNQMP_DISP_AV_BUF_5BIT_SF, 226 }; 227 228 static const u32 scaling_factors_888[] = { 229 ZYNQMP_DISP_AV_BUF_8BIT_SF, 230 ZYNQMP_DISP_AV_BUF_8BIT_SF, 231 ZYNQMP_DISP_AV_BUF_8BIT_SF, 232 }; 233 234 static const u32 scaling_factors_101010[] = { 235 ZYNQMP_DISP_AV_BUF_10BIT_SF, 236 ZYNQMP_DISP_AV_BUF_10BIT_SF, 237 ZYNQMP_DISP_AV_BUF_10BIT_SF, 238 }; 239 240 /* List of video layer formats */ 241 static const struct zynqmp_disp_format avbuf_vid_fmts[] = { 242 { 243 .drm_fmt = DRM_FORMAT_VYUY, 244 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY, 245 .swap = true, 246 .sf = scaling_factors_888, 247 }, { 248 .drm_fmt = DRM_FORMAT_UYVY, 249 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY, 250 .swap = false, 251 .sf = scaling_factors_888, 252 }, { 253 .drm_fmt = DRM_FORMAT_YUYV, 254 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV, 255 .swap = false, 256 .sf = scaling_factors_888, 257 }, { 258 .drm_fmt = DRM_FORMAT_YVYU, 259 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV, 260 .swap = true, 261 .sf = scaling_factors_888, 262 }, { 263 .drm_fmt = DRM_FORMAT_YUV422, 264 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16, 265 .swap = false, 266 .sf = scaling_factors_888, 267 }, { 268 .drm_fmt = DRM_FORMAT_YVU422, 269 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16, 270 .swap = true, 271 .sf = scaling_factors_888, 272 }, { 273 .drm_fmt = DRM_FORMAT_YUV444, 274 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24, 275 .swap = false, 276 .sf = scaling_factors_888, 277 }, { 278 .drm_fmt = DRM_FORMAT_YVU444, 279 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24, 280 .swap = true, 281 .sf = scaling_factors_888, 282 }, { 283 .drm_fmt = DRM_FORMAT_NV16, 284 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI, 285 .swap = false, 286 .sf = scaling_factors_888, 287 }, { 288 .drm_fmt = DRM_FORMAT_NV61, 289 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI, 290 .swap = true, 291 .sf = scaling_factors_888, 292 }, { 293 .drm_fmt = DRM_FORMAT_BGR888, 294 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888, 295 .swap = false, 296 .sf = scaling_factors_888, 297 }, { 298 .drm_fmt = DRM_FORMAT_RGB888, 299 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888, 300 .swap = true, 301 .sf = scaling_factors_888, 302 }, { 303 .drm_fmt = DRM_FORMAT_XBGR8888, 304 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880, 305 .swap = false, 306 .sf = scaling_factors_888, 307 }, { 308 .drm_fmt = DRM_FORMAT_XRGB8888, 309 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880, 310 .swap = true, 311 .sf = scaling_factors_888, 312 }, { 313 .drm_fmt = DRM_FORMAT_XBGR2101010, 314 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10, 315 .swap = false, 316 .sf = scaling_factors_101010, 317 }, { 318 .drm_fmt = DRM_FORMAT_XRGB2101010, 319 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10, 320 .swap = true, 321 .sf = scaling_factors_101010, 322 }, { 323 .drm_fmt = DRM_FORMAT_YUV420, 324 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420, 325 .swap = false, 326 .sf = scaling_factors_888, 327 }, { 328 .drm_fmt = DRM_FORMAT_YVU420, 329 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420, 330 .swap = true, 331 .sf = scaling_factors_888, 332 }, { 333 .drm_fmt = DRM_FORMAT_NV12, 334 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420, 335 .swap = false, 336 .sf = scaling_factors_888, 337 }, { 338 .drm_fmt = DRM_FORMAT_NV21, 339 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420, 340 .swap = true, 341 .sf = scaling_factors_888, 342 }, 343 }; 344 345 /* List of graphics layer formats */ 346 static const struct zynqmp_disp_format avbuf_gfx_fmts[] = { 347 { 348 .drm_fmt = DRM_FORMAT_ABGR8888, 349 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888, 350 .swap = false, 351 .sf = scaling_factors_888, 352 }, { 353 .drm_fmt = DRM_FORMAT_ARGB8888, 354 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888, 355 .swap = true, 356 .sf = scaling_factors_888, 357 }, { 358 .drm_fmt = DRM_FORMAT_RGBA8888, 359 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888, 360 .swap = false, 361 .sf = scaling_factors_888, 362 }, { 363 .drm_fmt = DRM_FORMAT_BGRA8888, 364 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888, 365 .swap = true, 366 .sf = scaling_factors_888, 367 }, { 368 .drm_fmt = DRM_FORMAT_BGR888, 369 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888, 370 .swap = false, 371 .sf = scaling_factors_888, 372 }, { 373 .drm_fmt = DRM_FORMAT_RGB888, 374 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888, 375 .swap = false, 376 .sf = scaling_factors_888, 377 }, { 378 .drm_fmt = DRM_FORMAT_RGBA5551, 379 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551, 380 .swap = false, 381 .sf = scaling_factors_555, 382 }, { 383 .drm_fmt = DRM_FORMAT_BGRA5551, 384 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551, 385 .swap = true, 386 .sf = scaling_factors_555, 387 }, { 388 .drm_fmt = DRM_FORMAT_RGBA4444, 389 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444, 390 .swap = false, 391 .sf = scaling_factors_444, 392 }, { 393 .drm_fmt = DRM_FORMAT_BGRA4444, 394 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444, 395 .swap = true, 396 .sf = scaling_factors_444, 397 }, { 398 .drm_fmt = DRM_FORMAT_RGB565, 399 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565, 400 .swap = false, 401 .sf = scaling_factors_565, 402 }, { 403 .drm_fmt = DRM_FORMAT_BGR565, 404 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565, 405 .swap = true, 406 .sf = scaling_factors_565, 407 }, 408 }; 409 410 static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp *disp, int reg) 411 { 412 return readl(disp->avbuf.base + reg); 413 } 414 415 static void zynqmp_disp_avbuf_write(struct zynqmp_disp *disp, int reg, u32 val) 416 { 417 writel(val, disp->avbuf.base + reg); 418 } 419 420 static bool zynqmp_disp_layer_is_gfx(const struct zynqmp_disp_layer *layer) 421 { 422 return layer->id == ZYNQMP_DISP_LAYER_GFX; 423 } 424 425 static bool zynqmp_disp_layer_is_video(const struct zynqmp_disp_layer *layer) 426 { 427 return layer->id == ZYNQMP_DISP_LAYER_VID; 428 } 429 430 /** 431 * zynqmp_disp_avbuf_set_format - Set the input format for a layer 432 * @disp: Display controller 433 * @layer: The layer 434 * @fmt: The format information 435 * 436 * Set the video buffer manager format for @layer to @fmt. 437 */ 438 static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp *disp, 439 struct zynqmp_disp_layer *layer, 440 const struct zynqmp_disp_format *fmt) 441 { 442 unsigned int i; 443 u32 val; 444 445 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_FMT); 446 val &= zynqmp_disp_layer_is_video(layer) 447 ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK 448 : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK; 449 val |= fmt->buf_fmt; 450 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_FMT, val); 451 452 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++) { 453 unsigned int reg = zynqmp_disp_layer_is_video(layer) 454 ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i) 455 : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i); 456 457 zynqmp_disp_avbuf_write(disp, reg, fmt->sf[i]); 458 } 459 } 460 461 /** 462 * zynqmp_disp_avbuf_set_clocks_sources - Set the clocks sources 463 * @disp: Display controller 464 * @video_from_ps: True if the video clock originates from the PS 465 * @audio_from_ps: True if the audio clock originates from the PS 466 * @timings_internal: True if video timings are generated internally 467 * 468 * Set the source for the video and audio clocks, as well as for the video 469 * timings. Clocks can originate from the PS or PL, and timings can be 470 * generated internally or externally. 471 */ 472 static void 473 zynqmp_disp_avbuf_set_clocks_sources(struct zynqmp_disp *disp, 474 bool video_from_ps, bool audio_from_ps, 475 bool timings_internal) 476 { 477 u32 val = 0; 478 479 if (video_from_ps) 480 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS; 481 if (audio_from_ps) 482 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS; 483 if (timings_internal) 484 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING; 485 486 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CLK_SRC, val); 487 } 488 489 /** 490 * zynqmp_disp_avbuf_enable_channels - Enable buffer channels 491 * @disp: Display controller 492 * 493 * Enable all (video and audio) buffer channels. 494 */ 495 static void zynqmp_disp_avbuf_enable_channels(struct zynqmp_disp *disp) 496 { 497 unsigned int i; 498 u32 val; 499 500 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN | 501 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX << 502 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT); 503 504 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS; i++) 505 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i), 506 val); 507 508 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN | 509 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX << 510 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT); 511 512 for (; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++) 513 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i), 514 val); 515 } 516 517 /** 518 * zynqmp_disp_avbuf_disable_channels - Disable buffer channels 519 * @disp: Display controller 520 * 521 * Disable all (video and audio) buffer channels. 522 */ 523 static void zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp *disp) 524 { 525 unsigned int i; 526 527 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++) 528 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_CHBUF(i), 529 ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH); 530 } 531 532 /** 533 * zynqmp_disp_avbuf_enable_audio - Enable audio 534 * @disp: Display controller 535 * 536 * Enable all audio buffers with a non-live (memory) source. 537 */ 538 static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp *disp) 539 { 540 u32 val; 541 542 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 543 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; 544 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM; 545 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; 546 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 547 } 548 549 /** 550 * zynqmp_disp_avbuf_disable_audio - Disable audio 551 * @disp: Display controller 552 * 553 * Disable all audio buffers. 554 */ 555 static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp *disp) 556 { 557 u32 val; 558 559 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 560 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; 561 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE; 562 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; 563 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 564 } 565 566 /** 567 * zynqmp_disp_avbuf_enable_video - Enable a video layer 568 * @disp: Display controller 569 * @layer: The layer 570 * @mode: Operating mode of layer 571 * 572 * Enable the video/graphics buffer for @layer. 573 */ 574 static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp *disp, 575 struct zynqmp_disp_layer *layer, 576 enum zynqmp_disp_layer_mode mode) 577 { 578 u32 val; 579 580 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 581 if (zynqmp_disp_layer_is_video(layer)) { 582 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; 583 if (mode == ZYNQMP_DISP_LAYER_NONLIVE) 584 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM; 585 else 586 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE; 587 } else { 588 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; 589 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; 590 if (mode == ZYNQMP_DISP_LAYER_NONLIVE) 591 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; 592 else 593 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE; 594 } 595 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 596 } 597 598 /** 599 * zynqmp_disp_avbuf_disable_video - Disable a video layer 600 * @disp: Display controller 601 * @layer: The layer 602 * 603 * Disable the video/graphics buffer for @layer. 604 */ 605 static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp *disp, 606 struct zynqmp_disp_layer *layer) 607 { 608 u32 val; 609 610 val = zynqmp_disp_avbuf_read(disp, ZYNQMP_DISP_AV_BUF_OUTPUT); 611 if (zynqmp_disp_layer_is_video(layer)) { 612 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; 613 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE; 614 } else { 615 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; 616 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE; 617 } 618 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 619 } 620 621 /** 622 * zynqmp_disp_avbuf_enable - Enable the video pipe 623 * @disp: Display controller 624 * 625 * De-assert the video pipe reset. 626 */ 627 static void zynqmp_disp_avbuf_enable(struct zynqmp_disp *disp) 628 { 629 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG, 0); 630 } 631 632 /** 633 * zynqmp_disp_avbuf_disable - Disable the video pipe 634 * @disp: Display controller 635 * 636 * Assert the video pipe reset. 637 */ 638 static void zynqmp_disp_avbuf_disable(struct zynqmp_disp *disp) 639 { 640 zynqmp_disp_avbuf_write(disp, ZYNQMP_DISP_AV_BUF_SRST_REG, 641 ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST); 642 } 643 644 /* ----------------------------------------------------------------------------- 645 * Blender (Video Pipeline) 646 */ 647 648 static void zynqmp_disp_blend_write(struct zynqmp_disp *disp, int reg, u32 val) 649 { 650 writel(val, disp->blend.base + reg); 651 } 652 653 /* 654 * Colorspace conversion matrices. 655 * 656 * Hardcode RGB <-> YUV conversion to full-range SDTV for now. 657 */ 658 static const u16 csc_zero_matrix[] = { 659 0x0, 0x0, 0x0, 660 0x0, 0x0, 0x0, 661 0x0, 0x0, 0x0 662 }; 663 664 static const u16 csc_identity_matrix[] = { 665 0x1000, 0x0, 0x0, 666 0x0, 0x1000, 0x0, 667 0x0, 0x0, 0x1000 668 }; 669 670 static const u32 csc_zero_offsets[] = { 671 0, 0, 0 672 }; 673 674 static const u16 csc_rgb_to_sdtv_matrix[] = { 675 0x4c9, 0x864, 0x1d3, 676 0x7d4d, 0x7ab3, 0x800, 677 0x800, 0x794d, 0x7eb3 678 }; 679 680 static const u32 csc_rgb_to_sdtv_offsets[] = { 681 0x0, 0x8000000, 0x8000000 682 }; 683 684 static const u16 csc_sdtv_to_rgb_matrix[] = { 685 0x1000, 0x166f, 0x0, 686 0x1000, 0x7483, 0x7a7f, 687 0x1000, 0x0, 0x1c5a 688 }; 689 690 static const u32 csc_sdtv_to_rgb_offsets[] = { 691 0x0, 0x1800, 0x1800 692 }; 693 694 /** 695 * zynqmp_disp_blend_set_output_format - Set the output format of the blender 696 * @disp: Display controller 697 * @format: Output format 698 * 699 * Set the output format of the blender to @format. 700 */ 701 static void zynqmp_disp_blend_set_output_format(struct zynqmp_disp *disp, 702 enum zynqmp_dpsub_format format) 703 { 704 static const unsigned int blend_output_fmts[] = { 705 [ZYNQMP_DPSUB_FORMAT_RGB] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB, 706 [ZYNQMP_DPSUB_FORMAT_YCRCB444] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444, 707 [ZYNQMP_DPSUB_FORMAT_YCRCB422] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422 708 | ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE, 709 [ZYNQMP_DPSUB_FORMAT_YONLY] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY, 710 }; 711 712 u32 fmt = blend_output_fmts[format]; 713 const u16 *coeffs; 714 const u32 *offsets; 715 unsigned int i; 716 717 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT, fmt); 718 if (fmt == ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB) { 719 coeffs = csc_identity_matrix; 720 offsets = csc_zero_offsets; 721 } else { 722 coeffs = csc_rgb_to_sdtv_matrix; 723 offsets = csc_rgb_to_sdtv_offsets; 724 } 725 726 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++) 727 zynqmp_disp_blend_write(disp, 728 ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(i), 729 coeffs[i]); 730 731 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++) 732 zynqmp_disp_blend_write(disp, 733 ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(i), 734 offsets[i]); 735 } 736 737 /** 738 * zynqmp_disp_blend_set_bg_color - Set the background color 739 * @disp: Display controller 740 * @rcr: Red/Cr color component 741 * @gy: Green/Y color component 742 * @bcb: Blue/Cb color component 743 * 744 * Set the background color to (@rcr, @gy, @bcb), corresponding to the R, G and 745 * B or Cr, Y and Cb components respectively depending on the selected output 746 * format. 747 */ 748 static void zynqmp_disp_blend_set_bg_color(struct zynqmp_disp *disp, 749 u32 rcr, u32 gy, u32 bcb) 750 { 751 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_0, rcr); 752 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_1, gy); 753 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_BG_CLR_2, bcb); 754 } 755 756 /** 757 * zynqmp_disp_blend_set_global_alpha - Configure global alpha blending 758 * @disp: Display controller 759 * @enable: True to enable global alpha blending 760 * @alpha: Global alpha value (ignored if @enabled is false) 761 */ 762 static void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp *disp, 763 bool enable, u32 alpha) 764 { 765 zynqmp_disp_blend_write(disp, ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA, 766 ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(alpha) | 767 (enable ? ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN : 0)); 768 } 769 770 /** 771 * zynqmp_disp_blend_layer_set_csc - Configure colorspace conversion for layer 772 * @disp: Display controller 773 * @layer: The layer 774 * @coeffs: Colorspace conversion matrix 775 * @offsets: Colorspace conversion offsets 776 * 777 * Configure the input colorspace conversion matrix and offsets for the @layer. 778 * Columns of the matrix are automatically swapped based on the input format to 779 * handle RGB and YCrCb components permutations. 780 */ 781 static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp *disp, 782 struct zynqmp_disp_layer *layer, 783 const u16 *coeffs, 784 const u32 *offsets) 785 { 786 unsigned int swap[3] = { 0, 1, 2 }; 787 unsigned int reg; 788 unsigned int i; 789 790 if (layer->disp_fmt->swap) { 791 if (layer->drm_fmt->is_yuv) { 792 /* Swap U and V. */ 793 swap[1] = 2; 794 swap[2] = 1; 795 } else { 796 /* Swap R and B. */ 797 swap[0] = 2; 798 swap[2] = 0; 799 } 800 } 801 802 if (zynqmp_disp_layer_is_video(layer)) 803 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(0); 804 else 805 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(0); 806 807 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i += 3, reg += 12) { 808 zynqmp_disp_blend_write(disp, reg + 0, coeffs[i + swap[0]]); 809 zynqmp_disp_blend_write(disp, reg + 4, coeffs[i + swap[1]]); 810 zynqmp_disp_blend_write(disp, reg + 8, coeffs[i + swap[2]]); 811 } 812 813 if (zynqmp_disp_layer_is_video(layer)) 814 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(0); 815 else 816 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(0); 817 818 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++) 819 zynqmp_disp_blend_write(disp, reg + i * 4, offsets[i]); 820 } 821 822 /** 823 * zynqmp_disp_blend_layer_enable - Enable a layer 824 * @disp: Display controller 825 * @layer: The layer 826 */ 827 static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp, 828 struct zynqmp_disp_layer *layer) 829 { 830 const u16 *coeffs; 831 const u32 *offsets; 832 u32 val; 833 834 val = (layer->drm_fmt->is_yuv ? 835 0 : ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB) | 836 (layer->drm_fmt->hsub > 1 ? 837 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US : 0); 838 839 zynqmp_disp_blend_write(disp, 840 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id), 841 val); 842 843 if (layer->drm_fmt->is_yuv) { 844 coeffs = csc_sdtv_to_rgb_matrix; 845 offsets = csc_sdtv_to_rgb_offsets; 846 } else { 847 coeffs = csc_identity_matrix; 848 offsets = csc_zero_offsets; 849 } 850 851 zynqmp_disp_blend_layer_set_csc(disp, layer, coeffs, offsets); 852 } 853 854 /** 855 * zynqmp_disp_blend_layer_disable - Disable a layer 856 * @disp: Display controller 857 * @layer: The layer 858 */ 859 static void zynqmp_disp_blend_layer_disable(struct zynqmp_disp *disp, 860 struct zynqmp_disp_layer *layer) 861 { 862 zynqmp_disp_blend_write(disp, 863 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id), 864 0); 865 866 zynqmp_disp_blend_layer_set_csc(disp, layer, csc_zero_matrix, 867 csc_zero_offsets); 868 } 869 870 /* ----------------------------------------------------------------------------- 871 * Audio Mixer 872 */ 873 874 static void zynqmp_disp_audio_write(struct zynqmp_disp *disp, int reg, u32 val) 875 { 876 writel(val, disp->audio.base + reg); 877 } 878 879 /** 880 * zynqmp_disp_audio_enable - Enable the audio mixer 881 * @disp: Display controller 882 * 883 * Enable the audio mixer by de-asserting the soft reset. The audio state is set to 884 * default values by the reset, set the default mixer volume explicitly. 885 */ 886 static void zynqmp_disp_audio_enable(struct zynqmp_disp *disp) 887 { 888 /* Clear the audio soft reset register as it's an non-reset flop. */ 889 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET, 0); 890 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_MIXER_VOLUME, 891 ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE); 892 } 893 894 /** 895 * zynqmp_disp_audio_disable - Disable the audio mixer 896 * @disp: Display controller 897 * 898 * Disable the audio mixer by asserting its soft reset. 899 */ 900 static void zynqmp_disp_audio_disable(struct zynqmp_disp *disp) 901 { 902 zynqmp_disp_audio_write(disp, ZYNQMP_DISP_AUD_SOFT_RESET, 903 ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST); 904 } 905 906 static void zynqmp_disp_audio_init(struct zynqmp_disp *disp) 907 { 908 /* Try the live PL audio clock. */ 909 disp->audio.clk = devm_clk_get(disp->dev, "dp_live_audio_aclk"); 910 if (!IS_ERR(disp->audio.clk)) { 911 disp->audio.clk_from_ps = false; 912 return; 913 } 914 915 /* If the live PL audio clock is not valid, fall back to PS clock. */ 916 disp->audio.clk = devm_clk_get(disp->dev, "dp_aud_clk"); 917 if (!IS_ERR(disp->audio.clk)) { 918 disp->audio.clk_from_ps = true; 919 return; 920 } 921 922 dev_err(disp->dev, "audio disabled due to missing clock\n"); 923 } 924 925 /* ----------------------------------------------------------------------------- 926 * ZynqMP Display external functions for zynqmp_dp 927 */ 928 929 /** 930 * zynqmp_disp_handle_vblank - Handle the vblank event 931 * @disp: Display controller 932 * 933 * This function handles the vblank interrupt, and sends an event to 934 * CRTC object. This will be called by the DP vblank interrupt handler. 935 */ 936 void zynqmp_disp_handle_vblank(struct zynqmp_disp *disp) 937 { 938 struct drm_crtc *crtc = &disp->crtc; 939 940 drm_crtc_handle_vblank(crtc); 941 } 942 943 /** 944 * zynqmp_disp_audio_enabled - If the audio is enabled 945 * @disp: Display controller 946 * 947 * Return if the audio is enabled depending on the audio clock. 948 * 949 * Return: true if audio is enabled, or false. 950 */ 951 bool zynqmp_disp_audio_enabled(struct zynqmp_disp *disp) 952 { 953 return !!disp->audio.clk; 954 } 955 956 /** 957 * zynqmp_disp_get_audio_clk_rate - Get the current audio clock rate 958 * @disp: Display controller 959 * 960 * Return: the current audio clock rate. 961 */ 962 unsigned int zynqmp_disp_get_audio_clk_rate(struct zynqmp_disp *disp) 963 { 964 if (zynqmp_disp_audio_enabled(disp)) 965 return 0; 966 return clk_get_rate(disp->audio.clk); 967 } 968 969 /** 970 * zynqmp_disp_get_crtc_mask - Return the CRTC bit mask 971 * @disp: Display controller 972 * 973 * Return: the crtc mask of the zyqnmp_disp CRTC. 974 */ 975 uint32_t zynqmp_disp_get_crtc_mask(struct zynqmp_disp *disp) 976 { 977 return drm_crtc_mask(&disp->crtc); 978 } 979 980 /* ----------------------------------------------------------------------------- 981 * ZynqMP Display Layer & DRM Plane 982 */ 983 984 /** 985 * zynqmp_disp_layer_find_format - Find format information for a DRM format 986 * @layer: The layer 987 * @drm_fmt: DRM format to search 988 * 989 * Search display subsystem format information corresponding to the given DRM 990 * format @drm_fmt for the @layer, and return a pointer to the format 991 * descriptor. 992 * 993 * Return: A pointer to the format descriptor if found, NULL otherwise 994 */ 995 static const struct zynqmp_disp_format * 996 zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer, 997 u32 drm_fmt) 998 { 999 unsigned int i; 1000 1001 for (i = 0; i < layer->info->num_formats; i++) { 1002 if (layer->info->formats[i].drm_fmt == drm_fmt) 1003 return &layer->info->formats[i]; 1004 } 1005 1006 return NULL; 1007 } 1008 1009 /** 1010 * zynqmp_disp_layer_enable - Enable a layer 1011 * @layer: The layer 1012 * 1013 * Enable the @layer in the audio/video buffer manager and the blender. DMA 1014 * channels are started separately by zynqmp_disp_layer_update(). 1015 */ 1016 static void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer) 1017 { 1018 zynqmp_disp_avbuf_enable_video(layer->disp, layer, 1019 ZYNQMP_DISP_LAYER_NONLIVE); 1020 zynqmp_disp_blend_layer_enable(layer->disp, layer); 1021 1022 layer->mode = ZYNQMP_DISP_LAYER_NONLIVE; 1023 } 1024 1025 /** 1026 * zynqmp_disp_layer_disable - Disable the layer 1027 * @layer: The layer 1028 * 1029 * Disable the layer by stopping its DMA channels and disabling it in the 1030 * audio/video buffer manager and the blender. 1031 */ 1032 static void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer) 1033 { 1034 unsigned int i; 1035 1036 for (i = 0; i < layer->drm_fmt->num_planes; i++) 1037 dmaengine_terminate_sync(layer->dmas[i].chan); 1038 1039 zynqmp_disp_avbuf_disable_video(layer->disp, layer); 1040 zynqmp_disp_blend_layer_disable(layer->disp, layer); 1041 } 1042 1043 /** 1044 * zynqmp_disp_layer_set_format - Set the layer format 1045 * @layer: The layer 1046 * @state: The plane state 1047 * 1048 * Set the format for @layer based on @state->fb->format. The layer must be 1049 * disabled. 1050 */ 1051 static void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, 1052 struct drm_plane_state *state) 1053 { 1054 const struct drm_format_info *info = state->fb->format; 1055 unsigned int i; 1056 1057 layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format); 1058 layer->drm_fmt = info; 1059 1060 zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); 1061 1062 /* 1063 * Set pconfig for each DMA channel to indicate they're part of a 1064 * video group. 1065 */ 1066 for (i = 0; i < info->num_planes; i++) { 1067 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1068 struct xilinx_dpdma_peripheral_config pconfig = { 1069 .video_group = true, 1070 }; 1071 struct dma_slave_config config = { 1072 .direction = DMA_MEM_TO_DEV, 1073 .peripheral_config = &pconfig, 1074 .peripheral_size = sizeof(pconfig), 1075 }; 1076 1077 dmaengine_slave_config(dma->chan, &config); 1078 } 1079 } 1080 1081 /** 1082 * zynqmp_disp_layer_update - Update the layer framebuffer 1083 * @layer: The layer 1084 * @state: The plane state 1085 * 1086 * Update the framebuffer for the layer by issuing a new DMA engine transaction 1087 * for the new framebuffer. 1088 * 1089 * Return: 0 on success, or the DMA descriptor failure error otherwise 1090 */ 1091 static int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, 1092 struct drm_plane_state *state) 1093 { 1094 const struct drm_format_info *info = layer->drm_fmt; 1095 unsigned int i; 1096 1097 for (i = 0; i < layer->drm_fmt->num_planes; i++) { 1098 unsigned int width = state->crtc_w / (i ? info->hsub : 1); 1099 unsigned int height = state->crtc_h / (i ? info->vsub : 1); 1100 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1101 struct dma_async_tx_descriptor *desc; 1102 dma_addr_t paddr; 1103 1104 paddr = drm_fb_cma_get_gem_addr(state->fb, state, i); 1105 1106 dma->xt.numf = height; 1107 dma->sgl.size = width * info->cpp[i]; 1108 dma->sgl.icg = state->fb->pitches[i] - dma->sgl.size; 1109 dma->xt.src_start = paddr; 1110 dma->xt.frame_size = 1; 1111 dma->xt.dir = DMA_MEM_TO_DEV; 1112 dma->xt.src_sgl = true; 1113 dma->xt.dst_sgl = false; 1114 1115 desc = dmaengine_prep_interleaved_dma(dma->chan, &dma->xt, 1116 DMA_CTRL_ACK | 1117 DMA_PREP_REPEAT | 1118 DMA_PREP_LOAD_EOT); 1119 if (!desc) { 1120 dev_err(layer->disp->dev, 1121 "failed to prepare DMA descriptor\n"); 1122 return -ENOMEM; 1123 } 1124 1125 dmaengine_submit(desc); 1126 dma_async_issue_pending(dma->chan); 1127 } 1128 1129 return 0; 1130 } 1131 1132 static inline struct zynqmp_disp_layer *plane_to_layer(struct drm_plane *plane) 1133 { 1134 return container_of(plane, struct zynqmp_disp_layer, plane); 1135 } 1136 1137 static int 1138 zynqmp_disp_plane_atomic_check(struct drm_plane *plane, 1139 struct drm_atomic_state *state) 1140 { 1141 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1142 plane); 1143 struct drm_crtc_state *crtc_state; 1144 1145 if (!new_plane_state->crtc) 1146 return 0; 1147 1148 crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc); 1149 if (IS_ERR(crtc_state)) 1150 return PTR_ERR(crtc_state); 1151 1152 return drm_atomic_helper_check_plane_state(new_plane_state, 1153 crtc_state, 1154 DRM_PLANE_HELPER_NO_SCALING, 1155 DRM_PLANE_HELPER_NO_SCALING, 1156 false, false); 1157 } 1158 1159 static void 1160 zynqmp_disp_plane_atomic_disable(struct drm_plane *plane, 1161 struct drm_atomic_state *state) 1162 { 1163 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 1164 plane); 1165 struct zynqmp_disp_layer *layer = plane_to_layer(plane); 1166 1167 if (!old_state->fb) 1168 return; 1169 1170 zynqmp_disp_layer_disable(layer); 1171 1172 if (zynqmp_disp_layer_is_gfx(layer)) 1173 zynqmp_disp_blend_set_global_alpha(layer->disp, false, 1174 plane->state->alpha >> 8); 1175 } 1176 1177 static void 1178 zynqmp_disp_plane_atomic_update(struct drm_plane *plane, 1179 struct drm_atomic_state *state) 1180 { 1181 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); 1182 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1183 struct zynqmp_disp_layer *layer = plane_to_layer(plane); 1184 bool format_changed = false; 1185 1186 if (!old_state->fb || 1187 old_state->fb->format->format != new_state->fb->format->format) 1188 format_changed = true; 1189 1190 /* 1191 * If the format has changed (including going from a previously 1192 * disabled state to any format), reconfigure the format. Disable the 1193 * plane first if needed. 1194 */ 1195 if (format_changed) { 1196 if (old_state->fb) 1197 zynqmp_disp_layer_disable(layer); 1198 1199 zynqmp_disp_layer_set_format(layer, new_state); 1200 } 1201 1202 zynqmp_disp_layer_update(layer, new_state); 1203 1204 if (zynqmp_disp_layer_is_gfx(layer)) 1205 zynqmp_disp_blend_set_global_alpha(layer->disp, true, 1206 plane->state->alpha >> 8); 1207 1208 /* Enable or re-enable the plane is the format has changed. */ 1209 if (format_changed) 1210 zynqmp_disp_layer_enable(layer); 1211 } 1212 1213 static const struct drm_plane_helper_funcs zynqmp_disp_plane_helper_funcs = { 1214 .atomic_check = zynqmp_disp_plane_atomic_check, 1215 .atomic_update = zynqmp_disp_plane_atomic_update, 1216 .atomic_disable = zynqmp_disp_plane_atomic_disable, 1217 }; 1218 1219 static const struct drm_plane_funcs zynqmp_disp_plane_funcs = { 1220 .update_plane = drm_atomic_helper_update_plane, 1221 .disable_plane = drm_atomic_helper_disable_plane, 1222 .destroy = drm_plane_cleanup, 1223 .reset = drm_atomic_helper_plane_reset, 1224 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1225 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1226 }; 1227 1228 static int zynqmp_disp_create_planes(struct zynqmp_disp *disp) 1229 { 1230 unsigned int i, j; 1231 int ret; 1232 1233 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) { 1234 struct zynqmp_disp_layer *layer = &disp->layers[i]; 1235 enum drm_plane_type type; 1236 u32 *drm_formats; 1237 1238 drm_formats = drmm_kcalloc(disp->drm, sizeof(*drm_formats), 1239 layer->info->num_formats, 1240 GFP_KERNEL); 1241 if (!drm_formats) 1242 return -ENOMEM; 1243 1244 for (j = 0; j < layer->info->num_formats; ++j) 1245 drm_formats[j] = layer->info->formats[j].drm_fmt; 1246 1247 /* Graphics layer is primary, and video layer is overlay. */ 1248 type = zynqmp_disp_layer_is_video(layer) 1249 ? DRM_PLANE_TYPE_OVERLAY : DRM_PLANE_TYPE_PRIMARY; 1250 ret = drm_universal_plane_init(disp->drm, &layer->plane, 0, 1251 &zynqmp_disp_plane_funcs, 1252 drm_formats, 1253 layer->info->num_formats, 1254 NULL, type, NULL); 1255 if (ret) 1256 return ret; 1257 1258 drm_plane_helper_add(&layer->plane, 1259 &zynqmp_disp_plane_helper_funcs); 1260 1261 drm_plane_create_zpos_immutable_property(&layer->plane, i); 1262 if (zynqmp_disp_layer_is_gfx(layer)) 1263 drm_plane_create_alpha_property(&layer->plane); 1264 } 1265 1266 return 0; 1267 } 1268 1269 /** 1270 * zynqmp_disp_layer_release_dma - Release DMA channels for a layer 1271 * @disp: Display controller 1272 * @layer: The layer 1273 * 1274 * Release the DMA channels associated with @layer. 1275 */ 1276 static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp, 1277 struct zynqmp_disp_layer *layer) 1278 { 1279 unsigned int i; 1280 1281 if (!layer->info) 1282 return; 1283 1284 for (i = 0; i < layer->info->num_channels; i++) { 1285 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1286 1287 if (!dma->chan) 1288 continue; 1289 1290 /* Make sure the channel is terminated before release. */ 1291 dmaengine_terminate_sync(dma->chan); 1292 dma_release_channel(dma->chan); 1293 } 1294 } 1295 1296 /** 1297 * zynqmp_disp_destroy_layers - Destroy all layers 1298 * @disp: Display controller 1299 */ 1300 static void zynqmp_disp_destroy_layers(struct zynqmp_disp *disp) 1301 { 1302 unsigned int i; 1303 1304 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) 1305 zynqmp_disp_layer_release_dma(disp, &disp->layers[i]); 1306 } 1307 1308 /** 1309 * zynqmp_disp_layer_request_dma - Request DMA channels for a layer 1310 * @disp: Display controller 1311 * @layer: The layer 1312 * 1313 * Request all DMA engine channels needed by @layer. 1314 * 1315 * Return: 0 on success, or the DMA channel request error otherwise 1316 */ 1317 static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp, 1318 struct zynqmp_disp_layer *layer) 1319 { 1320 static const char * const dma_names[] = { "vid", "gfx" }; 1321 unsigned int i; 1322 int ret; 1323 1324 for (i = 0; i < layer->info->num_channels; i++) { 1325 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1326 char dma_channel_name[16]; 1327 1328 snprintf(dma_channel_name, sizeof(dma_channel_name), 1329 "%s%u", dma_names[layer->id], i); 1330 dma->chan = dma_request_chan(disp->dev, dma_channel_name); 1331 if (IS_ERR(dma->chan)) { 1332 dev_err(disp->dev, "failed to request dma channel\n"); 1333 ret = PTR_ERR(dma->chan); 1334 dma->chan = NULL; 1335 return ret; 1336 } 1337 } 1338 1339 return 0; 1340 } 1341 1342 /** 1343 * zynqmp_disp_create_layers - Create and initialize all layers 1344 * @disp: Display controller 1345 * 1346 * Return: 0 on success, or the DMA channel request error otherwise 1347 */ 1348 static int zynqmp_disp_create_layers(struct zynqmp_disp *disp) 1349 { 1350 static const struct zynqmp_disp_layer_info layer_info[] = { 1351 [ZYNQMP_DISP_LAYER_VID] = { 1352 .formats = avbuf_vid_fmts, 1353 .num_formats = ARRAY_SIZE(avbuf_vid_fmts), 1354 .num_channels = 3, 1355 }, 1356 [ZYNQMP_DISP_LAYER_GFX] = { 1357 .formats = avbuf_gfx_fmts, 1358 .num_formats = ARRAY_SIZE(avbuf_gfx_fmts), 1359 .num_channels = 1, 1360 }, 1361 }; 1362 1363 unsigned int i; 1364 int ret; 1365 1366 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) { 1367 struct zynqmp_disp_layer *layer = &disp->layers[i]; 1368 1369 layer->id = i; 1370 layer->disp = disp; 1371 layer->info = &layer_info[i]; 1372 1373 ret = zynqmp_disp_layer_request_dma(disp, layer); 1374 if (ret) 1375 goto err; 1376 } 1377 1378 return 0; 1379 1380 err: 1381 zynqmp_disp_destroy_layers(disp); 1382 return ret; 1383 } 1384 1385 /* ----------------------------------------------------------------------------- 1386 * ZynqMP Display & DRM CRTC 1387 */ 1388 1389 /** 1390 * zynqmp_disp_enable - Enable the display controller 1391 * @disp: Display controller 1392 */ 1393 static void zynqmp_disp_enable(struct zynqmp_disp *disp) 1394 { 1395 zynqmp_disp_avbuf_enable(disp); 1396 /* Choose clock source based on the DT clock handle. */ 1397 zynqmp_disp_avbuf_set_clocks_sources(disp, disp->pclk_from_ps, 1398 disp->audio.clk_from_ps, true); 1399 zynqmp_disp_avbuf_enable_channels(disp); 1400 zynqmp_disp_avbuf_enable_audio(disp); 1401 1402 zynqmp_disp_audio_enable(disp); 1403 } 1404 1405 /** 1406 * zynqmp_disp_disable - Disable the display controller 1407 * @disp: Display controller 1408 */ 1409 static void zynqmp_disp_disable(struct zynqmp_disp *disp) 1410 { 1411 zynqmp_disp_audio_disable(disp); 1412 1413 zynqmp_disp_avbuf_disable_audio(disp); 1414 zynqmp_disp_avbuf_disable_channels(disp); 1415 zynqmp_disp_avbuf_disable(disp); 1416 } 1417 1418 static inline struct zynqmp_disp *crtc_to_disp(struct drm_crtc *crtc) 1419 { 1420 return container_of(crtc, struct zynqmp_disp, crtc); 1421 } 1422 1423 static int zynqmp_disp_crtc_setup_clock(struct drm_crtc *crtc, 1424 struct drm_display_mode *adjusted_mode) 1425 { 1426 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1427 unsigned long mode_clock = adjusted_mode->clock * 1000; 1428 unsigned long rate; 1429 long diff; 1430 int ret; 1431 1432 ret = clk_set_rate(disp->pclk, mode_clock); 1433 if (ret) { 1434 dev_err(disp->dev, "failed to set a pixel clock\n"); 1435 return ret; 1436 } 1437 1438 rate = clk_get_rate(disp->pclk); 1439 diff = rate - mode_clock; 1440 if (abs(diff) > mode_clock / 20) 1441 dev_info(disp->dev, 1442 "requested pixel rate: %lu actual rate: %lu\n", 1443 mode_clock, rate); 1444 else 1445 dev_dbg(disp->dev, 1446 "requested pixel rate: %lu actual rate: %lu\n", 1447 mode_clock, rate); 1448 1449 return 0; 1450 } 1451 1452 static void 1453 zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc, 1454 struct drm_atomic_state *state) 1455 { 1456 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1457 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1458 int ret, vrefresh; 1459 1460 pm_runtime_get_sync(disp->dev); 1461 1462 zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode); 1463 1464 ret = clk_prepare_enable(disp->pclk); 1465 if (ret) { 1466 dev_err(disp->dev, "failed to enable a pixel clock\n"); 1467 pm_runtime_put_sync(disp->dev); 1468 return; 1469 } 1470 1471 zynqmp_disp_blend_set_output_format(disp, ZYNQMP_DPSUB_FORMAT_RGB); 1472 zynqmp_disp_blend_set_bg_color(disp, 0, 0, 0); 1473 1474 zynqmp_disp_enable(disp); 1475 1476 /* Delay of 3 vblank intervals for timing gen to be stable */ 1477 vrefresh = (adjusted_mode->clock * 1000) / 1478 (adjusted_mode->vtotal * adjusted_mode->htotal); 1479 msleep(3 * 1000 / vrefresh); 1480 } 1481 1482 static void 1483 zynqmp_disp_crtc_atomic_disable(struct drm_crtc *crtc, 1484 struct drm_atomic_state *state) 1485 { 1486 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1487 struct drm_plane_state *old_plane_state; 1488 1489 /* 1490 * Disable the plane if active. The old plane state can be NULL in the 1491 * .shutdown() path if the plane is already disabled, skip 1492 * zynqmp_disp_plane_atomic_disable() in that case. 1493 */ 1494 old_plane_state = drm_atomic_get_old_plane_state(state, crtc->primary); 1495 if (old_plane_state) 1496 zynqmp_disp_plane_atomic_disable(crtc->primary, state); 1497 1498 zynqmp_disp_disable(disp); 1499 1500 drm_crtc_vblank_off(&disp->crtc); 1501 1502 spin_lock_irq(&crtc->dev->event_lock); 1503 if (crtc->state->event) { 1504 drm_crtc_send_vblank_event(crtc, crtc->state->event); 1505 crtc->state->event = NULL; 1506 } 1507 spin_unlock_irq(&crtc->dev->event_lock); 1508 1509 clk_disable_unprepare(disp->pclk); 1510 pm_runtime_put_sync(disp->dev); 1511 } 1512 1513 static int zynqmp_disp_crtc_atomic_check(struct drm_crtc *crtc, 1514 struct drm_atomic_state *state) 1515 { 1516 return drm_atomic_add_affected_planes(state, crtc); 1517 } 1518 1519 static void 1520 zynqmp_disp_crtc_atomic_begin(struct drm_crtc *crtc, 1521 struct drm_atomic_state *state) 1522 { 1523 drm_crtc_vblank_on(crtc); 1524 } 1525 1526 static void 1527 zynqmp_disp_crtc_atomic_flush(struct drm_crtc *crtc, 1528 struct drm_atomic_state *state) 1529 { 1530 if (crtc->state->event) { 1531 struct drm_pending_vblank_event *event; 1532 1533 /* Consume the flip_done event from atomic helper. */ 1534 event = crtc->state->event; 1535 crtc->state->event = NULL; 1536 1537 event->pipe = drm_crtc_index(crtc); 1538 1539 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1540 1541 spin_lock_irq(&crtc->dev->event_lock); 1542 drm_crtc_arm_vblank_event(crtc, event); 1543 spin_unlock_irq(&crtc->dev->event_lock); 1544 } 1545 } 1546 1547 static const struct drm_crtc_helper_funcs zynqmp_disp_crtc_helper_funcs = { 1548 .atomic_enable = zynqmp_disp_crtc_atomic_enable, 1549 .atomic_disable = zynqmp_disp_crtc_atomic_disable, 1550 .atomic_check = zynqmp_disp_crtc_atomic_check, 1551 .atomic_begin = zynqmp_disp_crtc_atomic_begin, 1552 .atomic_flush = zynqmp_disp_crtc_atomic_flush, 1553 }; 1554 1555 static int zynqmp_disp_crtc_enable_vblank(struct drm_crtc *crtc) 1556 { 1557 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1558 1559 zynqmp_dp_enable_vblank(disp->dpsub->dp); 1560 1561 return 0; 1562 } 1563 1564 static void zynqmp_disp_crtc_disable_vblank(struct drm_crtc *crtc) 1565 { 1566 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1567 1568 zynqmp_dp_disable_vblank(disp->dpsub->dp); 1569 } 1570 1571 static const struct drm_crtc_funcs zynqmp_disp_crtc_funcs = { 1572 .destroy = drm_crtc_cleanup, 1573 .set_config = drm_atomic_helper_set_config, 1574 .page_flip = drm_atomic_helper_page_flip, 1575 .reset = drm_atomic_helper_crtc_reset, 1576 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1577 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1578 .enable_vblank = zynqmp_disp_crtc_enable_vblank, 1579 .disable_vblank = zynqmp_disp_crtc_disable_vblank, 1580 }; 1581 1582 static int zynqmp_disp_create_crtc(struct zynqmp_disp *disp) 1583 { 1584 struct drm_plane *plane = &disp->layers[ZYNQMP_DISP_LAYER_GFX].plane; 1585 int ret; 1586 1587 ret = drm_crtc_init_with_planes(disp->drm, &disp->crtc, plane, 1588 NULL, &zynqmp_disp_crtc_funcs, NULL); 1589 if (ret < 0) 1590 return ret; 1591 1592 drm_crtc_helper_add(&disp->crtc, &zynqmp_disp_crtc_helper_funcs); 1593 1594 /* Start with vertical blanking interrupt reporting disabled. */ 1595 drm_crtc_vblank_off(&disp->crtc); 1596 1597 return 0; 1598 } 1599 1600 static void zynqmp_disp_map_crtc_to_plane(struct zynqmp_disp *disp) 1601 { 1602 u32 possible_crtcs = drm_crtc_mask(&disp->crtc); 1603 unsigned int i; 1604 1605 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) 1606 disp->layers[i].plane.possible_crtcs = possible_crtcs; 1607 } 1608 1609 /* ----------------------------------------------------------------------------- 1610 * Initialization & Cleanup 1611 */ 1612 1613 int zynqmp_disp_drm_init(struct zynqmp_dpsub *dpsub) 1614 { 1615 struct zynqmp_disp *disp = dpsub->disp; 1616 int ret; 1617 1618 ret = zynqmp_disp_create_planes(disp); 1619 if (ret) 1620 return ret; 1621 1622 ret = zynqmp_disp_create_crtc(disp); 1623 if (ret < 0) 1624 return ret; 1625 1626 zynqmp_disp_map_crtc_to_plane(disp); 1627 1628 return 0; 1629 } 1630 1631 int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub, struct drm_device *drm) 1632 { 1633 struct platform_device *pdev = to_platform_device(dpsub->dev); 1634 struct zynqmp_disp *disp; 1635 struct zynqmp_disp_layer *layer; 1636 struct resource *res; 1637 int ret; 1638 1639 disp = drmm_kzalloc(drm, sizeof(*disp), GFP_KERNEL); 1640 if (!disp) 1641 return -ENOMEM; 1642 1643 disp->dev = &pdev->dev; 1644 disp->dpsub = dpsub; 1645 disp->drm = drm; 1646 1647 dpsub->disp = disp; 1648 1649 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "blend"); 1650 disp->blend.base = devm_ioremap_resource(disp->dev, res); 1651 if (IS_ERR(disp->blend.base)) 1652 return PTR_ERR(disp->blend.base); 1653 1654 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "av_buf"); 1655 disp->avbuf.base = devm_ioremap_resource(disp->dev, res); 1656 if (IS_ERR(disp->avbuf.base)) 1657 return PTR_ERR(disp->avbuf.base); 1658 1659 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aud"); 1660 disp->audio.base = devm_ioremap_resource(disp->dev, res); 1661 if (IS_ERR(disp->audio.base)) 1662 return PTR_ERR(disp->audio.base); 1663 1664 /* Try the live PL video clock */ 1665 disp->pclk = devm_clk_get(disp->dev, "dp_live_video_in_clk"); 1666 if (!IS_ERR(disp->pclk)) 1667 disp->pclk_from_ps = false; 1668 else if (PTR_ERR(disp->pclk) == -EPROBE_DEFER) 1669 return PTR_ERR(disp->pclk); 1670 1671 /* If the live PL video clock is not valid, fall back to PS clock */ 1672 if (IS_ERR_OR_NULL(disp->pclk)) { 1673 disp->pclk = devm_clk_get(disp->dev, "dp_vtc_pixel_clk_in"); 1674 if (IS_ERR(disp->pclk)) { 1675 dev_err(disp->dev, "failed to init any video clock\n"); 1676 return PTR_ERR(disp->pclk); 1677 } 1678 disp->pclk_from_ps = true; 1679 } 1680 1681 zynqmp_disp_audio_init(disp); 1682 1683 ret = zynqmp_disp_create_layers(disp); 1684 if (ret) 1685 return ret; 1686 1687 layer = &disp->layers[ZYNQMP_DISP_LAYER_VID]; 1688 dpsub->dma_align = 1 << layer->dmas[0].chan->device->copy_align; 1689 1690 return 0; 1691 } 1692 1693 void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub) 1694 { 1695 struct zynqmp_disp *disp = dpsub->disp; 1696 1697 zynqmp_disp_destroy_layers(disp); 1698 } 1699