1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * ZynqMP Display Controller Driver 4 * 5 * Copyright (C) 2017 - 2020 Xilinx, Inc. 6 * 7 * Authors: 8 * - Hyun Woo Kwon <hyun.kwon@xilinx.com> 9 * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 10 */ 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_atomic_uapi.h> 15 #include <drm/drm_crtc.h> 16 #include <drm/drm_device.h> 17 #include <drm/drm_fb_cma_helper.h> 18 #include <drm/drm_fourcc.h> 19 #include <drm/drm_framebuffer.h> 20 #include <drm/drm_managed.h> 21 #include <drm/drm_plane.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_vblank.h> 24 25 #include <linux/clk.h> 26 #include <linux/delay.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/dmaengine.h> 29 #include <linux/module.h> 30 #include <linux/of.h> 31 #include <linux/of_dma.h> 32 #include <linux/platform_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/spinlock.h> 35 36 #include "zynqmp_disp.h" 37 #include "zynqmp_disp_regs.h" 38 #include "zynqmp_dp.h" 39 #include "zynqmp_dpsub.h" 40 41 /* 42 * Overview 43 * -------- 44 * 45 * The display controller part of ZynqMP DP subsystem, made of the Audio/Video 46 * Buffer Manager, the Video Rendering Pipeline (blender) and the Audio Mixer. 47 * 48 * +------------------------------------------------------------+ 49 * +--------+ | +----------------+ +-----------+ | 50 * | DPDMA | --->| | --> | Video | Video +-------------+ | 51 * | 4x vid | | | | | Rendering | -+--> | | | +------+ 52 * | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 | 53 * +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+ 54 * | | and STC | +-----------+ | | Controller | | +------+ 55 * Live Video --->| | --> | Audio | Audio | |---> | PHY1 | 56 * | | | | Mixer | --+-> | | | +------+ 57 * Live Audio --->| | --> | | || +-------------+ | 58 * | +----------------+ +-----------+ || | 59 * +---------------------------------------||-------------------+ 60 * vv 61 * Blended Video and 62 * Mixed Audio to PL 63 * 64 * Only non-live input from the DPDMA and output to the DisplayPort Source 65 * Controller are currently supported. Interface with the programmable logic 66 * for live streams is not implemented. 67 * 68 * The display controller code creates planes for the DPDMA video and graphics 69 * layers, and a CRTC for the Video Rendering Pipeline. 70 */ 71 72 #define ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS 4 73 #define ZYNQMP_DISP_AV_BUF_NUM_BUFFERS 6 74 75 #define ZYNQMP_DISP_NUM_LAYERS 2 76 #define ZYNQMP_DISP_MAX_NUM_SUB_PLANES 3 77 78 /** 79 * struct zynqmp_disp_format - Display subsystem format information 80 * @drm_fmt: DRM format (4CC) 81 * @buf_fmt: AV buffer format 82 * @bus_fmt: Media bus formats (live formats) 83 * @swap: Flag to swap R & B for RGB formats, and U & V for YUV formats 84 * @sf: Scaling factors for color components 85 */ 86 struct zynqmp_disp_format { 87 u32 drm_fmt; 88 u32 buf_fmt; 89 u32 bus_fmt; 90 bool swap; 91 const u32 *sf; 92 }; 93 94 /** 95 * enum zynqmp_disp_id - Layer identifier 96 * @ZYNQMP_DISP_LAYER_VID: Video layer 97 * @ZYNQMP_DISP_LAYER_GFX: Graphics layer 98 */ 99 enum zynqmp_disp_layer_id { 100 ZYNQMP_DISP_LAYER_VID, 101 ZYNQMP_DISP_LAYER_GFX 102 }; 103 104 /** 105 * enum zynqmp_disp_layer_mode - Layer mode 106 * @ZYNQMP_DISP_LAYER_NONLIVE: non-live (memory) mode 107 * @ZYNQMP_DISP_LAYER_LIVE: live (stream) mode 108 */ 109 enum zynqmp_disp_layer_mode { 110 ZYNQMP_DISP_LAYER_NONLIVE, 111 ZYNQMP_DISP_LAYER_LIVE 112 }; 113 114 /** 115 * struct zynqmp_disp_layer_dma - DMA channel for one data plane of a layer 116 * @chan: DMA channel 117 * @xt: Interleaved DMA descriptor template 118 * @sgl: Data chunk for dma_interleaved_template 119 */ 120 struct zynqmp_disp_layer_dma { 121 struct dma_chan *chan; 122 struct dma_interleaved_template xt; 123 struct data_chunk sgl; 124 }; 125 126 /** 127 * struct zynqmp_disp_layer_info - Static layer information 128 * @formats: Array of supported formats 129 * @num_formats: Number of formats in @formats array 130 * @num_channels: Number of DMA channels 131 */ 132 struct zynqmp_disp_layer_info { 133 const struct zynqmp_disp_format *formats; 134 unsigned int num_formats; 135 unsigned int num_channels; 136 }; 137 138 /** 139 * struct zynqmp_disp_layer - Display layer (DRM plane) 140 * @plane: DRM plane 141 * @id: Layer ID 142 * @disp: Back pointer to struct zynqmp_disp 143 * @info: Static layer information 144 * @dmas: DMA channels 145 * @disp_fmt: Current format information 146 * @drm_fmt: Current DRM format information 147 * @mode: Current operation mode 148 */ 149 struct zynqmp_disp_layer { 150 struct drm_plane plane; 151 enum zynqmp_disp_layer_id id; 152 struct zynqmp_disp *disp; 153 const struct zynqmp_disp_layer_info *info; 154 155 struct zynqmp_disp_layer_dma dmas[ZYNQMP_DISP_MAX_NUM_SUB_PLANES]; 156 157 const struct zynqmp_disp_format *disp_fmt; 158 const struct drm_format_info *drm_fmt; 159 enum zynqmp_disp_layer_mode mode; 160 }; 161 162 /** 163 * struct zynqmp_disp_blend - Blender 164 * @base: Registers I/O base address 165 */ 166 struct zynqmp_disp_blend { 167 void __iomem *base; 168 }; 169 170 /** 171 * struct zynqmp_disp_avbuf - Audio/video buffer manager 172 * @base: Registers I/O base address 173 */ 174 struct zynqmp_disp_avbuf { 175 void __iomem *base; 176 }; 177 178 /** 179 * struct zynqmp_disp_audio - Audio mixer 180 * @base: Registers I/O base address 181 * @clk: Audio clock 182 * @clk_from_ps: True of the audio clock comes from PS, false from PL 183 */ 184 struct zynqmp_disp_audio { 185 void __iomem *base; 186 struct clk *clk; 187 bool clk_from_ps; 188 }; 189 190 /** 191 * struct zynqmp_disp - Display controller 192 * @dev: Device structure 193 * @drm: DRM core 194 * @dpsub: Display subsystem 195 * @crtc: DRM CRTC 196 * @blend: Blender (video rendering pipeline) 197 * @avbuf: Audio/video buffer manager 198 * @audio: Audio mixer 199 * @layers: Layers (planes) 200 * @event: Pending vblank event request 201 * @pclk: Pixel clock 202 * @pclk_from_ps: True of the video clock comes from PS, false from PL 203 */ 204 struct zynqmp_disp { 205 struct device *dev; 206 struct drm_device *drm; 207 struct zynqmp_dpsub *dpsub; 208 209 struct drm_crtc crtc; 210 211 struct zynqmp_disp_blend blend; 212 struct zynqmp_disp_avbuf avbuf; 213 struct zynqmp_disp_audio audio; 214 215 struct zynqmp_disp_layer layers[ZYNQMP_DISP_NUM_LAYERS]; 216 217 struct drm_pending_vblank_event *event; 218 219 struct clk *pclk; 220 bool pclk_from_ps; 221 }; 222 223 /* ----------------------------------------------------------------------------- 224 * Audio/Video Buffer Manager 225 */ 226 227 static const u32 scaling_factors_444[] = { 228 ZYNQMP_DISP_AV_BUF_4BIT_SF, 229 ZYNQMP_DISP_AV_BUF_4BIT_SF, 230 ZYNQMP_DISP_AV_BUF_4BIT_SF, 231 }; 232 233 static const u32 scaling_factors_555[] = { 234 ZYNQMP_DISP_AV_BUF_5BIT_SF, 235 ZYNQMP_DISP_AV_BUF_5BIT_SF, 236 ZYNQMP_DISP_AV_BUF_5BIT_SF, 237 }; 238 239 static const u32 scaling_factors_565[] = { 240 ZYNQMP_DISP_AV_BUF_5BIT_SF, 241 ZYNQMP_DISP_AV_BUF_6BIT_SF, 242 ZYNQMP_DISP_AV_BUF_5BIT_SF, 243 }; 244 245 static const u32 scaling_factors_888[] = { 246 ZYNQMP_DISP_AV_BUF_8BIT_SF, 247 ZYNQMP_DISP_AV_BUF_8BIT_SF, 248 ZYNQMP_DISP_AV_BUF_8BIT_SF, 249 }; 250 251 static const u32 scaling_factors_101010[] = { 252 ZYNQMP_DISP_AV_BUF_10BIT_SF, 253 ZYNQMP_DISP_AV_BUF_10BIT_SF, 254 ZYNQMP_DISP_AV_BUF_10BIT_SF, 255 }; 256 257 /* List of video layer formats */ 258 static const struct zynqmp_disp_format avbuf_vid_fmts[] = { 259 { 260 .drm_fmt = DRM_FORMAT_VYUY, 261 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY, 262 .swap = true, 263 .sf = scaling_factors_888, 264 }, { 265 .drm_fmt = DRM_FORMAT_UYVY, 266 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY, 267 .swap = false, 268 .sf = scaling_factors_888, 269 }, { 270 .drm_fmt = DRM_FORMAT_YUYV, 271 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV, 272 .swap = false, 273 .sf = scaling_factors_888, 274 }, { 275 .drm_fmt = DRM_FORMAT_YVYU, 276 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV, 277 .swap = true, 278 .sf = scaling_factors_888, 279 }, { 280 .drm_fmt = DRM_FORMAT_YUV422, 281 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16, 282 .swap = false, 283 .sf = scaling_factors_888, 284 }, { 285 .drm_fmt = DRM_FORMAT_YVU422, 286 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16, 287 .swap = true, 288 .sf = scaling_factors_888, 289 }, { 290 .drm_fmt = DRM_FORMAT_YUV444, 291 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24, 292 .swap = false, 293 .sf = scaling_factors_888, 294 }, { 295 .drm_fmt = DRM_FORMAT_YVU444, 296 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24, 297 .swap = true, 298 .sf = scaling_factors_888, 299 }, { 300 .drm_fmt = DRM_FORMAT_NV16, 301 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI, 302 .swap = false, 303 .sf = scaling_factors_888, 304 }, { 305 .drm_fmt = DRM_FORMAT_NV61, 306 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI, 307 .swap = true, 308 .sf = scaling_factors_888, 309 }, { 310 .drm_fmt = DRM_FORMAT_BGR888, 311 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888, 312 .swap = false, 313 .sf = scaling_factors_888, 314 }, { 315 .drm_fmt = DRM_FORMAT_RGB888, 316 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888, 317 .swap = true, 318 .sf = scaling_factors_888, 319 }, { 320 .drm_fmt = DRM_FORMAT_XBGR8888, 321 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880, 322 .swap = false, 323 .sf = scaling_factors_888, 324 }, { 325 .drm_fmt = DRM_FORMAT_XRGB8888, 326 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880, 327 .swap = true, 328 .sf = scaling_factors_888, 329 }, { 330 .drm_fmt = DRM_FORMAT_XBGR2101010, 331 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10, 332 .swap = false, 333 .sf = scaling_factors_101010, 334 }, { 335 .drm_fmt = DRM_FORMAT_XRGB2101010, 336 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10, 337 .swap = true, 338 .sf = scaling_factors_101010, 339 }, { 340 .drm_fmt = DRM_FORMAT_YUV420, 341 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420, 342 .swap = false, 343 .sf = scaling_factors_888, 344 }, { 345 .drm_fmt = DRM_FORMAT_YVU420, 346 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420, 347 .swap = true, 348 .sf = scaling_factors_888, 349 }, { 350 .drm_fmt = DRM_FORMAT_NV12, 351 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420, 352 .swap = false, 353 .sf = scaling_factors_888, 354 }, { 355 .drm_fmt = DRM_FORMAT_NV21, 356 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420, 357 .swap = true, 358 .sf = scaling_factors_888, 359 }, 360 }; 361 362 /* List of graphics layer formats */ 363 static const struct zynqmp_disp_format avbuf_gfx_fmts[] = { 364 { 365 .drm_fmt = DRM_FORMAT_ABGR8888, 366 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888, 367 .swap = false, 368 .sf = scaling_factors_888, 369 }, { 370 .drm_fmt = DRM_FORMAT_ARGB8888, 371 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888, 372 .swap = true, 373 .sf = scaling_factors_888, 374 }, { 375 .drm_fmt = DRM_FORMAT_RGBA8888, 376 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888, 377 .swap = false, 378 .sf = scaling_factors_888, 379 }, { 380 .drm_fmt = DRM_FORMAT_BGRA8888, 381 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888, 382 .swap = true, 383 .sf = scaling_factors_888, 384 }, { 385 .drm_fmt = DRM_FORMAT_BGR888, 386 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888, 387 .swap = false, 388 .sf = scaling_factors_888, 389 }, { 390 .drm_fmt = DRM_FORMAT_RGB888, 391 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888, 392 .swap = false, 393 .sf = scaling_factors_888, 394 }, { 395 .drm_fmt = DRM_FORMAT_RGBA5551, 396 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551, 397 .swap = false, 398 .sf = scaling_factors_555, 399 }, { 400 .drm_fmt = DRM_FORMAT_BGRA5551, 401 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551, 402 .swap = true, 403 .sf = scaling_factors_555, 404 }, { 405 .drm_fmt = DRM_FORMAT_RGBA4444, 406 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444, 407 .swap = false, 408 .sf = scaling_factors_444, 409 }, { 410 .drm_fmt = DRM_FORMAT_BGRA4444, 411 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444, 412 .swap = true, 413 .sf = scaling_factors_444, 414 }, { 415 .drm_fmt = DRM_FORMAT_RGB565, 416 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565, 417 .swap = false, 418 .sf = scaling_factors_565, 419 }, { 420 .drm_fmt = DRM_FORMAT_BGR565, 421 .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565, 422 .swap = true, 423 .sf = scaling_factors_565, 424 }, 425 }; 426 427 static u32 zynqmp_disp_avbuf_read(struct zynqmp_disp_avbuf *avbuf, int reg) 428 { 429 return readl(avbuf->base + reg); 430 } 431 432 static void zynqmp_disp_avbuf_write(struct zynqmp_disp_avbuf *avbuf, 433 int reg, u32 val) 434 { 435 writel(val, avbuf->base + reg); 436 } 437 438 /** 439 * zynqmp_disp_avbuf_set_format - Set the input format for a layer 440 * @avbuf: Audio/video buffer manager 441 * @layer: The layer ID 442 * @fmt: The format information 443 * 444 * Set the video buffer manager format for @layer to @fmt. 445 */ 446 static void zynqmp_disp_avbuf_set_format(struct zynqmp_disp_avbuf *avbuf, 447 enum zynqmp_disp_layer_id layer, 448 const struct zynqmp_disp_format *fmt) 449 { 450 unsigned int i; 451 u32 val; 452 453 val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_FMT); 454 val &= layer == ZYNQMP_DISP_LAYER_VID 455 ? ~ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK 456 : ~ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK; 457 val |= fmt->buf_fmt; 458 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_FMT, val); 459 460 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_SF; i++) { 461 unsigned int reg = layer == ZYNQMP_DISP_LAYER_VID 462 ? ZYNQMP_DISP_AV_BUF_VID_COMP_SF(i) 463 : ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(i); 464 465 zynqmp_disp_avbuf_write(avbuf, reg, fmt->sf[i]); 466 } 467 } 468 469 /** 470 * zynqmp_disp_avbuf_set_clocks_sources - Set the clocks sources 471 * @avbuf: Audio/video buffer manager 472 * @video_from_ps: True if the video clock originates from the PS 473 * @audio_from_ps: True if the audio clock originates from the PS 474 * @timings_internal: True if video timings are generated internally 475 * 476 * Set the source for the video and audio clocks, as well as for the video 477 * timings. Clocks can originate from the PS or PL, and timings can be 478 * generated internally or externally. 479 */ 480 static void 481 zynqmp_disp_avbuf_set_clocks_sources(struct zynqmp_disp_avbuf *avbuf, 482 bool video_from_ps, bool audio_from_ps, 483 bool timings_internal) 484 { 485 u32 val = 0; 486 487 if (video_from_ps) 488 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS; 489 if (audio_from_ps) 490 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS; 491 if (timings_internal) 492 val |= ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING; 493 494 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CLK_SRC, val); 495 } 496 497 /** 498 * zynqmp_disp_avbuf_enable_channels - Enable buffer channels 499 * @avbuf: Audio/video buffer manager 500 * 501 * Enable all (video and audio) buffer channels. 502 */ 503 static void zynqmp_disp_avbuf_enable_channels(struct zynqmp_disp_avbuf *avbuf) 504 { 505 unsigned int i; 506 u32 val; 507 508 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN | 509 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX << 510 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT); 511 512 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_VID_GFX_BUFFERS; i++) 513 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CHBUF(i), 514 val); 515 516 val = ZYNQMP_DISP_AV_BUF_CHBUF_EN | 517 (ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX << 518 ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT); 519 520 for (; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++) 521 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CHBUF(i), 522 val); 523 } 524 525 /** 526 * zynqmp_disp_avbuf_disable_channels - Disable buffer channels 527 * @avbuf: Audio/video buffer manager 528 * 529 * Disable all (video and audio) buffer channels. 530 */ 531 static void zynqmp_disp_avbuf_disable_channels(struct zynqmp_disp_avbuf *avbuf) 532 { 533 unsigned int i; 534 535 for (i = 0; i < ZYNQMP_DISP_AV_BUF_NUM_BUFFERS; i++) 536 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_CHBUF(i), 537 ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH); 538 } 539 540 /** 541 * zynqmp_disp_avbuf_enable_audio - Enable audio 542 * @avbuf: Audio/video buffer manager 543 * 544 * Enable all audio buffers with a non-live (memory) source. 545 */ 546 static void zynqmp_disp_avbuf_enable_audio(struct zynqmp_disp_avbuf *avbuf) 547 { 548 u32 val; 549 550 val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); 551 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; 552 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM; 553 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; 554 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 555 } 556 557 /** 558 * zynqmp_disp_avbuf_disable_audio - Disable audio 559 * @avbuf: Audio/video buffer manager 560 * 561 * Disable all audio buffers. 562 */ 563 static void zynqmp_disp_avbuf_disable_audio(struct zynqmp_disp_avbuf *avbuf) 564 { 565 u32 val; 566 567 val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); 568 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK; 569 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE; 570 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN; 571 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 572 } 573 574 /** 575 * zynqmp_disp_avbuf_enable_video - Enable a video layer 576 * @avbuf: Audio/video buffer manager 577 * @layer: The layer ID 578 * @mode: Operating mode of layer 579 * 580 * Enable the video/graphics buffer for @layer. 581 */ 582 static void zynqmp_disp_avbuf_enable_video(struct zynqmp_disp_avbuf *avbuf, 583 enum zynqmp_disp_layer_id layer, 584 enum zynqmp_disp_layer_mode mode) 585 { 586 u32 val; 587 588 val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); 589 if (layer == ZYNQMP_DISP_LAYER_VID) { 590 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; 591 if (mode == ZYNQMP_DISP_LAYER_NONLIVE) 592 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM; 593 else 594 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE; 595 } else { 596 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; 597 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; 598 if (mode == ZYNQMP_DISP_LAYER_NONLIVE) 599 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM; 600 else 601 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE; 602 } 603 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 604 } 605 606 /** 607 * zynqmp_disp_avbuf_disable_video - Disable a video layer 608 * @avbuf: Audio/video buffer manager 609 * @layer: The layer ID 610 * 611 * Disable the video/graphics buffer for @layer. 612 */ 613 static void zynqmp_disp_avbuf_disable_video(struct zynqmp_disp_avbuf *avbuf, 614 enum zynqmp_disp_layer_id layer) 615 { 616 u32 val; 617 618 val = zynqmp_disp_avbuf_read(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT); 619 if (layer == ZYNQMP_DISP_LAYER_VID) { 620 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK; 621 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE; 622 } else { 623 val &= ~ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK; 624 val |= ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE; 625 } 626 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_OUTPUT, val); 627 } 628 629 /** 630 * zynqmp_disp_avbuf_enable - Enable the video pipe 631 * @avbuf: Audio/video buffer manager 632 * 633 * De-assert the video pipe reset. 634 */ 635 static void zynqmp_disp_avbuf_enable(struct zynqmp_disp_avbuf *avbuf) 636 { 637 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_SRST_REG, 0); 638 } 639 640 /** 641 * zynqmp_disp_avbuf_disable - Disable the video pipe 642 * @avbuf: Audio/video buffer manager 643 * 644 * Assert the video pipe reset. 645 */ 646 static void zynqmp_disp_avbuf_disable(struct zynqmp_disp_avbuf *avbuf) 647 { 648 zynqmp_disp_avbuf_write(avbuf, ZYNQMP_DISP_AV_BUF_SRST_REG, 649 ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST); 650 } 651 652 /* ----------------------------------------------------------------------------- 653 * Blender (Video Pipeline) 654 */ 655 656 static void zynqmp_disp_blend_write(struct zynqmp_disp_blend *blend, 657 int reg, u32 val) 658 { 659 writel(val, blend->base + reg); 660 } 661 662 /* 663 * Colorspace conversion matrices. 664 * 665 * Hardcode RGB <-> YUV conversion to full-range SDTV for now. 666 */ 667 static const u16 csc_zero_matrix[] = { 668 0x0, 0x0, 0x0, 669 0x0, 0x0, 0x0, 670 0x0, 0x0, 0x0 671 }; 672 673 static const u16 csc_identity_matrix[] = { 674 0x1000, 0x0, 0x0, 675 0x0, 0x1000, 0x0, 676 0x0, 0x0, 0x1000 677 }; 678 679 static const u32 csc_zero_offsets[] = { 680 0, 0, 0 681 }; 682 683 static const u16 csc_rgb_to_sdtv_matrix[] = { 684 0x4c9, 0x864, 0x1d3, 685 0x7d4d, 0x7ab3, 0x800, 686 0x800, 0x794d, 0x7eb3 687 }; 688 689 static const u32 csc_rgb_to_sdtv_offsets[] = { 690 0x0, 0x8000000, 0x8000000 691 }; 692 693 static const u16 csc_sdtv_to_rgb_matrix[] = { 694 0x1000, 0x166f, 0x0, 695 0x1000, 0x7483, 0x7a7f, 696 0x1000, 0x0, 0x1c5a 697 }; 698 699 static const u32 csc_sdtv_to_rgb_offsets[] = { 700 0x0, 0x1800, 0x1800 701 }; 702 703 /** 704 * zynqmp_disp_blend_set_output_format - Set the output format of the blender 705 * @blend: Blender object 706 * @format: Output format 707 * 708 * Set the output format of the blender to @format. 709 */ 710 static void zynqmp_disp_blend_set_output_format(struct zynqmp_disp_blend *blend, 711 enum zynqmp_dpsub_format format) 712 { 713 static const unsigned int blend_output_fmts[] = { 714 [ZYNQMP_DPSUB_FORMAT_RGB] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB, 715 [ZYNQMP_DPSUB_FORMAT_YCRCB444] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444, 716 [ZYNQMP_DPSUB_FORMAT_YCRCB422] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422 717 | ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE, 718 [ZYNQMP_DPSUB_FORMAT_YONLY] = ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY, 719 }; 720 721 u32 fmt = blend_output_fmts[format]; 722 const u16 *coeffs; 723 const u32 *offsets; 724 unsigned int i; 725 726 zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT, fmt); 727 if (fmt == ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB) { 728 coeffs = csc_identity_matrix; 729 offsets = csc_zero_offsets; 730 } else { 731 coeffs = csc_rgb_to_sdtv_matrix; 732 offsets = csc_rgb_to_sdtv_offsets; 733 } 734 735 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i++) 736 zynqmp_disp_blend_write(blend, 737 ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(i), 738 coeffs[i]); 739 740 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++) 741 zynqmp_disp_blend_write(blend, 742 ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(i), 743 offsets[i]); 744 } 745 746 /** 747 * zynqmp_disp_blend_set_bg_color - Set the background color 748 * @blend: Blender object 749 * @rcr: Red/Cr color component 750 * @gy: Green/Y color component 751 * @bcb: Blue/Cb color component 752 * 753 * Set the background color to (@rcr, @gy, @bcb), corresponding to the R, G and 754 * B or Cr, Y and Cb components respectively depending on the selected output 755 * format. 756 */ 757 static void zynqmp_disp_blend_set_bg_color(struct zynqmp_disp_blend *blend, 758 u32 rcr, u32 gy, u32 bcb) 759 { 760 zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_BG_CLR_0, rcr); 761 zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_BG_CLR_1, gy); 762 zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_BG_CLR_2, bcb); 763 } 764 765 /** 766 * zynqmp_disp_blend_set_global_alpha - Configure global alpha blending 767 * @blend: Blender object 768 * @enable: True to enable global alpha blending 769 * @alpha: Global alpha value (ignored if @enabled is false) 770 */ 771 static void zynqmp_disp_blend_set_global_alpha(struct zynqmp_disp_blend *blend, 772 bool enable, u32 alpha) 773 { 774 zynqmp_disp_blend_write(blend, ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA, 775 ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(alpha) | 776 (enable ? ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN : 0)); 777 } 778 779 /** 780 * zynqmp_disp_blend_layer_set_csc - Configure colorspace conversion for layer 781 * @blend: Blender object 782 * @layer: The layer 783 * @coeffs: Colorspace conversion matrix 784 * @offsets: Colorspace conversion offsets 785 * 786 * Configure the input colorspace conversion matrix and offsets for the @layer. 787 * Columns of the matrix are automatically swapped based on the input format to 788 * handle RGB and YCrCb components permutations. 789 */ 790 static void zynqmp_disp_blend_layer_set_csc(struct zynqmp_disp_blend *blend, 791 struct zynqmp_disp_layer *layer, 792 const u16 *coeffs, 793 const u32 *offsets) 794 { 795 unsigned int swap[3] = { 0, 1, 2 }; 796 unsigned int reg; 797 unsigned int i; 798 799 if (layer->disp_fmt->swap) { 800 if (layer->drm_fmt->is_yuv) { 801 /* Swap U and V. */ 802 swap[1] = 2; 803 swap[2] = 1; 804 } else { 805 /* Swap R and B. */ 806 swap[0] = 2; 807 swap[2] = 0; 808 } 809 } 810 811 if (layer->id == ZYNQMP_DISP_LAYER_VID) 812 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(0); 813 else 814 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(0); 815 816 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_COEFF; i += 3, reg += 12) { 817 zynqmp_disp_blend_write(blend, reg + 0, coeffs[i + swap[0]]); 818 zynqmp_disp_blend_write(blend, reg + 4, coeffs[i + swap[1]]); 819 zynqmp_disp_blend_write(blend, reg + 8, coeffs[i + swap[2]]); 820 } 821 822 if (layer->id == ZYNQMP_DISP_LAYER_VID) 823 reg = ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(0); 824 else 825 reg = ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(0); 826 827 for (i = 0; i < ZYNQMP_DISP_V_BLEND_NUM_OFFSET; i++) 828 zynqmp_disp_blend_write(blend, reg + i * 4, offsets[i]); 829 } 830 831 /** 832 * zynqmp_disp_blend_layer_enable - Enable a layer 833 * @blend: Blender object 834 * @layer: The layer 835 */ 836 static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp_blend *blend, 837 struct zynqmp_disp_layer *layer) 838 { 839 const u16 *coeffs; 840 const u32 *offsets; 841 u32 val; 842 843 val = (layer->drm_fmt->is_yuv ? 844 0 : ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB) | 845 (layer->drm_fmt->hsub > 1 ? 846 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US : 0); 847 848 zynqmp_disp_blend_write(blend, 849 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id), 850 val); 851 852 if (layer->drm_fmt->is_yuv) { 853 coeffs = csc_sdtv_to_rgb_matrix; 854 offsets = csc_sdtv_to_rgb_offsets; 855 } else { 856 coeffs = csc_identity_matrix; 857 offsets = csc_zero_offsets; 858 } 859 860 zynqmp_disp_blend_layer_set_csc(blend, layer, coeffs, offsets); 861 } 862 863 /** 864 * zynqmp_disp_blend_layer_disable - Disable a layer 865 * @blend: Blender object 866 * @layer: The layer 867 */ 868 static void zynqmp_disp_blend_layer_disable(struct zynqmp_disp_blend *blend, 869 struct zynqmp_disp_layer *layer) 870 { 871 zynqmp_disp_blend_write(blend, 872 ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id), 873 0); 874 875 zynqmp_disp_blend_layer_set_csc(blend, layer, csc_zero_matrix, 876 csc_zero_offsets); 877 } 878 879 /* ----------------------------------------------------------------------------- 880 * Audio Mixer 881 */ 882 883 static void zynqmp_disp_audio_write(struct zynqmp_disp_audio *audio, 884 int reg, u32 val) 885 { 886 writel(val, audio->base + reg); 887 } 888 889 /** 890 * zynqmp_disp_audio_enable - Enable the audio mixer 891 * @audio: Audio mixer 892 * 893 * Enable the audio mixer by de-asserting the soft reset. The audio state is set to 894 * default values by the reset, set the default mixer volume explicitly. 895 */ 896 static void zynqmp_disp_audio_enable(struct zynqmp_disp_audio *audio) 897 { 898 /* Clear the audio soft reset register as it's an non-reset flop. */ 899 zynqmp_disp_audio_write(audio, ZYNQMP_DISP_AUD_SOFT_RESET, 0); 900 zynqmp_disp_audio_write(audio, ZYNQMP_DISP_AUD_MIXER_VOLUME, 901 ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE); 902 } 903 904 /** 905 * zynqmp_disp_audio_disable - Disable the audio mixer 906 * @audio: Audio mixer 907 * 908 * Disable the audio mixer by asserting its soft reset. 909 */ 910 static void zynqmp_disp_audio_disable(struct zynqmp_disp_audio *audio) 911 { 912 zynqmp_disp_audio_write(audio, ZYNQMP_DISP_AUD_SOFT_RESET, 913 ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST); 914 } 915 916 static void zynqmp_disp_audio_init(struct device *dev, 917 struct zynqmp_disp_audio *audio) 918 { 919 /* Try the live PL audio clock. */ 920 audio->clk = devm_clk_get(dev, "dp_live_audio_aclk"); 921 if (!IS_ERR(audio->clk)) { 922 audio->clk_from_ps = false; 923 return; 924 } 925 926 /* If the live PL audio clock is not valid, fall back to PS clock. */ 927 audio->clk = devm_clk_get(dev, "dp_aud_clk"); 928 if (!IS_ERR(audio->clk)) { 929 audio->clk_from_ps = true; 930 return; 931 } 932 933 dev_err(dev, "audio disabled due to missing clock\n"); 934 } 935 936 /* ----------------------------------------------------------------------------- 937 * ZynqMP Display external functions for zynqmp_dp 938 */ 939 940 /** 941 * zynqmp_disp_handle_vblank - Handle the vblank event 942 * @disp: Display controller 943 * 944 * This function handles the vblank interrupt, and sends an event to 945 * CRTC object. This will be called by the DP vblank interrupt handler. 946 */ 947 void zynqmp_disp_handle_vblank(struct zynqmp_disp *disp) 948 { 949 struct drm_crtc *crtc = &disp->crtc; 950 951 drm_crtc_handle_vblank(crtc); 952 } 953 954 /** 955 * zynqmp_disp_audio_enabled - If the audio is enabled 956 * @disp: Display controller 957 * 958 * Return if the audio is enabled depending on the audio clock. 959 * 960 * Return: true if audio is enabled, or false. 961 */ 962 bool zynqmp_disp_audio_enabled(struct zynqmp_disp *disp) 963 { 964 return !!disp->audio.clk; 965 } 966 967 /** 968 * zynqmp_disp_get_audio_clk_rate - Get the current audio clock rate 969 * @disp: Display controller 970 * 971 * Return: the current audio clock rate. 972 */ 973 unsigned int zynqmp_disp_get_audio_clk_rate(struct zynqmp_disp *disp) 974 { 975 if (zynqmp_disp_audio_enabled(disp)) 976 return 0; 977 return clk_get_rate(disp->audio.clk); 978 } 979 980 /** 981 * zynqmp_disp_get_crtc_mask - Return the CRTC bit mask 982 * @disp: Display controller 983 * 984 * Return: the crtc mask of the zyqnmp_disp CRTC. 985 */ 986 uint32_t zynqmp_disp_get_crtc_mask(struct zynqmp_disp *disp) 987 { 988 return drm_crtc_mask(&disp->crtc); 989 } 990 991 /* ----------------------------------------------------------------------------- 992 * ZynqMP Display Layer & DRM Plane 993 */ 994 995 /** 996 * zynqmp_disp_layer_find_format - Find format information for a DRM format 997 * @layer: The layer 998 * @drm_fmt: DRM format to search 999 * 1000 * Search display subsystem format information corresponding to the given DRM 1001 * format @drm_fmt for the @layer, and return a pointer to the format 1002 * descriptor. 1003 * 1004 * Return: A pointer to the format descriptor if found, NULL otherwise 1005 */ 1006 static const struct zynqmp_disp_format * 1007 zynqmp_disp_layer_find_format(struct zynqmp_disp_layer *layer, 1008 u32 drm_fmt) 1009 { 1010 unsigned int i; 1011 1012 for (i = 0; i < layer->info->num_formats; i++) { 1013 if (layer->info->formats[i].drm_fmt == drm_fmt) 1014 return &layer->info->formats[i]; 1015 } 1016 1017 return NULL; 1018 } 1019 1020 /** 1021 * zynqmp_disp_layer_enable - Enable a layer 1022 * @layer: The layer 1023 * 1024 * Enable the @layer in the audio/video buffer manager and the blender. DMA 1025 * channels are started separately by zynqmp_disp_layer_update(). 1026 */ 1027 static void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer) 1028 { 1029 zynqmp_disp_avbuf_enable_video(&layer->disp->avbuf, layer->id, 1030 ZYNQMP_DISP_LAYER_NONLIVE); 1031 zynqmp_disp_blend_layer_enable(&layer->disp->blend, layer); 1032 1033 layer->mode = ZYNQMP_DISP_LAYER_NONLIVE; 1034 } 1035 1036 /** 1037 * zynqmp_disp_layer_disable - Disable the layer 1038 * @layer: The layer 1039 * 1040 * Disable the layer by stopping its DMA channels and disabling it in the 1041 * audio/video buffer manager and the blender. 1042 */ 1043 static void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer) 1044 { 1045 unsigned int i; 1046 1047 for (i = 0; i < layer->drm_fmt->num_planes; i++) 1048 dmaengine_terminate_sync(layer->dmas[i].chan); 1049 1050 zynqmp_disp_avbuf_disable_video(&layer->disp->avbuf, layer->id); 1051 zynqmp_disp_blend_layer_disable(&layer->disp->blend, layer); 1052 } 1053 1054 /** 1055 * zynqmp_disp_layer_set_format - Set the layer format 1056 * @layer: The layer 1057 * @state: The plane state 1058 * 1059 * Set the format for @layer based on @state->fb->format. The layer must be 1060 * disabled. 1061 */ 1062 static void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer, 1063 struct drm_plane_state *state) 1064 { 1065 const struct drm_format_info *info = state->fb->format; 1066 unsigned int i; 1067 1068 layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format); 1069 layer->drm_fmt = info; 1070 1071 zynqmp_disp_avbuf_set_format(&layer->disp->avbuf, layer->id, 1072 layer->disp_fmt); 1073 1074 /* 1075 * Set slave_id for each DMA channel to indicate they're part of a 1076 * video group. 1077 */ 1078 for (i = 0; i < info->num_planes; i++) { 1079 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1080 struct dma_slave_config config = { 1081 .direction = DMA_MEM_TO_DEV, 1082 .slave_id = 1, 1083 }; 1084 1085 dmaengine_slave_config(dma->chan, &config); 1086 } 1087 } 1088 1089 /** 1090 * zynqmp_disp_layer_update - Update the layer framebuffer 1091 * @layer: The layer 1092 * @state: The plane state 1093 * 1094 * Update the framebuffer for the layer by issuing a new DMA engine transaction 1095 * for the new framebuffer. 1096 * 1097 * Return: 0 on success, or the DMA descriptor failure error otherwise 1098 */ 1099 static int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer, 1100 struct drm_plane_state *state) 1101 { 1102 const struct drm_format_info *info = layer->drm_fmt; 1103 unsigned int i; 1104 1105 for (i = 0; i < layer->drm_fmt->num_planes; i++) { 1106 unsigned int width = state->crtc_w / (i ? info->hsub : 1); 1107 unsigned int height = state->crtc_h / (i ? info->vsub : 1); 1108 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1109 struct dma_async_tx_descriptor *desc; 1110 dma_addr_t paddr; 1111 1112 paddr = drm_fb_cma_get_gem_addr(state->fb, state, i); 1113 1114 dma->xt.numf = height; 1115 dma->sgl.size = width * info->cpp[i]; 1116 dma->sgl.icg = state->fb->pitches[i] - dma->sgl.size; 1117 dma->xt.src_start = paddr; 1118 dma->xt.frame_size = 1; 1119 dma->xt.dir = DMA_MEM_TO_DEV; 1120 dma->xt.src_sgl = true; 1121 dma->xt.dst_sgl = false; 1122 1123 desc = dmaengine_prep_interleaved_dma(dma->chan, &dma->xt, 1124 DMA_CTRL_ACK | 1125 DMA_PREP_REPEAT | 1126 DMA_PREP_LOAD_EOT); 1127 if (!desc) { 1128 dev_err(layer->disp->dev, 1129 "failed to prepare DMA descriptor\n"); 1130 return -ENOMEM; 1131 } 1132 1133 dmaengine_submit(desc); 1134 dma_async_issue_pending(dma->chan); 1135 } 1136 1137 return 0; 1138 } 1139 1140 static inline struct zynqmp_disp_layer *plane_to_layer(struct drm_plane *plane) 1141 { 1142 return container_of(plane, struct zynqmp_disp_layer, plane); 1143 } 1144 1145 static int 1146 zynqmp_disp_plane_atomic_check(struct drm_plane *plane, 1147 struct drm_plane_state *state) 1148 { 1149 struct drm_crtc_state *crtc_state; 1150 1151 if (!state->crtc) 1152 return 0; 1153 1154 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 1155 if (IS_ERR(crtc_state)) 1156 return PTR_ERR(crtc_state); 1157 1158 return drm_atomic_helper_check_plane_state(state, crtc_state, 1159 DRM_PLANE_HELPER_NO_SCALING, 1160 DRM_PLANE_HELPER_NO_SCALING, 1161 false, false); 1162 } 1163 1164 static void 1165 zynqmp_disp_plane_atomic_disable(struct drm_plane *plane, 1166 struct drm_plane_state *old_state) 1167 { 1168 struct zynqmp_disp_layer *layer = plane_to_layer(plane); 1169 1170 if (!old_state->fb) 1171 return; 1172 1173 zynqmp_disp_layer_disable(layer); 1174 } 1175 1176 static void 1177 zynqmp_disp_plane_atomic_update(struct drm_plane *plane, 1178 struct drm_plane_state *old_state) 1179 { 1180 struct zynqmp_disp_layer *layer = plane_to_layer(plane); 1181 bool format_changed = false; 1182 1183 if (!old_state->fb || 1184 old_state->fb->format->format != plane->state->fb->format->format) 1185 format_changed = true; 1186 1187 /* 1188 * If the format has changed (including going from a previously 1189 * disabled state to any format), reconfigure the format. Disable the 1190 * plane first if needed. 1191 */ 1192 if (format_changed) { 1193 if (old_state->fb) 1194 zynqmp_disp_layer_disable(layer); 1195 1196 zynqmp_disp_layer_set_format(layer, plane->state); 1197 } 1198 1199 zynqmp_disp_layer_update(layer, plane->state); 1200 1201 /* Enable or re-enable the plane is the format has changed. */ 1202 if (format_changed) 1203 zynqmp_disp_layer_enable(layer); 1204 } 1205 1206 static const struct drm_plane_helper_funcs zynqmp_disp_plane_helper_funcs = { 1207 .atomic_check = zynqmp_disp_plane_atomic_check, 1208 .atomic_update = zynqmp_disp_plane_atomic_update, 1209 .atomic_disable = zynqmp_disp_plane_atomic_disable, 1210 }; 1211 1212 static const struct drm_plane_funcs zynqmp_disp_plane_funcs = { 1213 .update_plane = drm_atomic_helper_update_plane, 1214 .disable_plane = drm_atomic_helper_disable_plane, 1215 .destroy = drm_plane_cleanup, 1216 .reset = drm_atomic_helper_plane_reset, 1217 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 1218 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 1219 }; 1220 1221 static int zynqmp_disp_create_planes(struct zynqmp_disp *disp) 1222 { 1223 unsigned int i, j; 1224 int ret; 1225 1226 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) { 1227 struct zynqmp_disp_layer *layer = &disp->layers[i]; 1228 enum drm_plane_type type; 1229 u32 *drm_formats; 1230 1231 drm_formats = drmm_kcalloc(disp->drm, sizeof(*drm_formats), 1232 layer->info->num_formats, 1233 GFP_KERNEL); 1234 if (!drm_formats) 1235 return -ENOMEM; 1236 1237 for (j = 0; j < layer->info->num_formats; ++j) 1238 drm_formats[j] = layer->info->formats[j].drm_fmt; 1239 1240 /* Graphics layer is primary, and video layer is overlay. */ 1241 type = i == ZYNQMP_DISP_LAYER_GFX 1242 ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY; 1243 ret = drm_universal_plane_init(disp->drm, &layer->plane, 0, 1244 &zynqmp_disp_plane_funcs, 1245 drm_formats, 1246 layer->info->num_formats, 1247 NULL, type, NULL); 1248 if (ret) 1249 return ret; 1250 1251 drm_plane_helper_add(&layer->plane, 1252 &zynqmp_disp_plane_helper_funcs); 1253 } 1254 1255 return 0; 1256 } 1257 1258 /** 1259 * zynqmp_disp_layer_release_dma - Release DMA channels for a layer 1260 * @disp: Display controller 1261 * @layer: The layer 1262 * 1263 * Release the DMA channels associated with @layer. 1264 */ 1265 static void zynqmp_disp_layer_release_dma(struct zynqmp_disp *disp, 1266 struct zynqmp_disp_layer *layer) 1267 { 1268 unsigned int i; 1269 1270 if (!layer->info) 1271 return; 1272 1273 for (i = 0; i < layer->info->num_channels; i++) { 1274 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1275 1276 if (!dma->chan) 1277 continue; 1278 1279 /* Make sure the channel is terminated before release. */ 1280 dmaengine_terminate_sync(dma->chan); 1281 dma_release_channel(dma->chan); 1282 } 1283 } 1284 1285 /** 1286 * zynqmp_disp_destroy_layers - Destroy all layers 1287 * @disp: Display controller 1288 */ 1289 static void zynqmp_disp_destroy_layers(struct zynqmp_disp *disp) 1290 { 1291 unsigned int i; 1292 1293 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) 1294 zynqmp_disp_layer_release_dma(disp, &disp->layers[i]); 1295 } 1296 1297 /** 1298 * zynqmp_disp_layer_request_dma - Request DMA channels for a layer 1299 * @disp: Display controller 1300 * @layer: The layer 1301 * 1302 * Request all DMA engine channels needed by @layer. 1303 * 1304 * Return: 0 on success, or the DMA channel request error otherwise 1305 */ 1306 static int zynqmp_disp_layer_request_dma(struct zynqmp_disp *disp, 1307 struct zynqmp_disp_layer *layer) 1308 { 1309 static const char * const dma_names[] = { "vid", "gfx" }; 1310 unsigned int i; 1311 int ret; 1312 1313 for (i = 0; i < layer->info->num_channels; i++) { 1314 struct zynqmp_disp_layer_dma *dma = &layer->dmas[i]; 1315 char dma_channel_name[16]; 1316 1317 snprintf(dma_channel_name, sizeof(dma_channel_name), 1318 "%s%u", dma_names[layer->id], i); 1319 dma->chan = of_dma_request_slave_channel(disp->dev->of_node, 1320 dma_channel_name); 1321 if (IS_ERR(dma->chan)) { 1322 dev_err(disp->dev, "failed to request dma channel\n"); 1323 ret = PTR_ERR(dma->chan); 1324 dma->chan = NULL; 1325 return ret; 1326 } 1327 } 1328 1329 return 0; 1330 } 1331 1332 /** 1333 * zynqmp_disp_create_layers - Create and initialize all layers 1334 * @disp: Display controller 1335 * 1336 * Return: 0 on success, or the DMA channel request error otherwise 1337 */ 1338 static int zynqmp_disp_create_layers(struct zynqmp_disp *disp) 1339 { 1340 static const struct zynqmp_disp_layer_info layer_info[] = { 1341 [ZYNQMP_DISP_LAYER_VID] = { 1342 .formats = avbuf_vid_fmts, 1343 .num_formats = ARRAY_SIZE(avbuf_vid_fmts), 1344 .num_channels = 3, 1345 }, 1346 [ZYNQMP_DISP_LAYER_GFX] = { 1347 .formats = avbuf_gfx_fmts, 1348 .num_formats = ARRAY_SIZE(avbuf_gfx_fmts), 1349 .num_channels = 1, 1350 }, 1351 }; 1352 1353 unsigned int i; 1354 int ret; 1355 1356 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) { 1357 struct zynqmp_disp_layer *layer = &disp->layers[i]; 1358 1359 layer->id = i; 1360 layer->disp = disp; 1361 layer->info = &layer_info[i]; 1362 1363 ret = zynqmp_disp_layer_request_dma(disp, layer); 1364 if (ret) 1365 goto err; 1366 } 1367 1368 return 0; 1369 1370 err: 1371 zynqmp_disp_destroy_layers(disp); 1372 return ret; 1373 } 1374 1375 /* ----------------------------------------------------------------------------- 1376 * ZynqMP Display & DRM CRTC 1377 */ 1378 1379 /** 1380 * zynqmp_disp_enable - Enable the display controller 1381 * @disp: Display controller 1382 */ 1383 static void zynqmp_disp_enable(struct zynqmp_disp *disp) 1384 { 1385 zynqmp_disp_avbuf_enable(&disp->avbuf); 1386 /* Choose clock source based on the DT clock handle. */ 1387 zynqmp_disp_avbuf_set_clocks_sources(&disp->avbuf, disp->pclk_from_ps, 1388 disp->audio.clk_from_ps, true); 1389 zynqmp_disp_avbuf_enable_channels(&disp->avbuf); 1390 zynqmp_disp_avbuf_enable_audio(&disp->avbuf); 1391 1392 zynqmp_disp_audio_enable(&disp->audio); 1393 } 1394 1395 /** 1396 * zynqmp_disp_disable - Disable the display controller 1397 * @disp: Display controller 1398 */ 1399 static void zynqmp_disp_disable(struct zynqmp_disp *disp) 1400 { 1401 struct drm_crtc *crtc = &disp->crtc; 1402 1403 zynqmp_disp_audio_disable(&disp->audio); 1404 1405 zynqmp_disp_avbuf_disable_audio(&disp->avbuf); 1406 zynqmp_disp_avbuf_disable_channels(&disp->avbuf); 1407 zynqmp_disp_avbuf_disable(&disp->avbuf); 1408 1409 /* Mark the flip is done as crtc is disabled anyway */ 1410 if (crtc->state->event) { 1411 complete_all(crtc->state->event->base.completion); 1412 crtc->state->event = NULL; 1413 } 1414 } 1415 1416 static inline struct zynqmp_disp *crtc_to_disp(struct drm_crtc *crtc) 1417 { 1418 return container_of(crtc, struct zynqmp_disp, crtc); 1419 } 1420 1421 static int zynqmp_disp_crtc_setup_clock(struct drm_crtc *crtc, 1422 struct drm_display_mode *adjusted_mode) 1423 { 1424 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1425 unsigned long mode_clock = adjusted_mode->clock * 1000; 1426 unsigned long rate; 1427 long diff; 1428 int ret; 1429 1430 ret = clk_set_rate(disp->pclk, mode_clock); 1431 if (ret) { 1432 dev_err(disp->dev, "failed to set a pixel clock\n"); 1433 return ret; 1434 } 1435 1436 rate = clk_get_rate(disp->pclk); 1437 diff = rate - mode_clock; 1438 if (abs(diff) > mode_clock / 20) 1439 dev_info(disp->dev, 1440 "requested pixel rate: %lu actual rate: %lu\n", 1441 mode_clock, rate); 1442 else 1443 dev_dbg(disp->dev, 1444 "requested pixel rate: %lu actual rate: %lu\n", 1445 mode_clock, rate); 1446 1447 return 0; 1448 } 1449 1450 static void 1451 zynqmp_disp_crtc_atomic_enable(struct drm_crtc *crtc, 1452 struct drm_crtc_state *old_crtc_state) 1453 { 1454 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1455 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; 1456 int ret, vrefresh; 1457 1458 zynqmp_disp_crtc_setup_clock(crtc, adjusted_mode); 1459 1460 pm_runtime_get_sync(disp->dev); 1461 ret = clk_prepare_enable(disp->pclk); 1462 if (ret) { 1463 dev_err(disp->dev, "failed to enable a pixel clock\n"); 1464 pm_runtime_put_sync(disp->dev); 1465 return; 1466 } 1467 1468 zynqmp_disp_blend_set_output_format(&disp->blend, 1469 ZYNQMP_DPSUB_FORMAT_RGB); 1470 zynqmp_disp_blend_set_bg_color(&disp->blend, 0, 0, 0); 1471 zynqmp_disp_blend_set_global_alpha(&disp->blend, false, 0); 1472 1473 zynqmp_disp_enable(disp); 1474 1475 /* Delay of 3 vblank intervals for timing gen to be stable */ 1476 vrefresh = (adjusted_mode->clock * 1000) / 1477 (adjusted_mode->vtotal * adjusted_mode->htotal); 1478 msleep(3 * 1000 / vrefresh); 1479 } 1480 1481 static void 1482 zynqmp_disp_crtc_atomic_disable(struct drm_crtc *crtc, 1483 struct drm_crtc_state *old_crtc_state) 1484 { 1485 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1486 struct drm_plane_state *old_plane_state; 1487 1488 /* 1489 * Disable the plane if active. The old plane state can be NULL in the 1490 * .shutdown() path if the plane is already disabled, skip 1491 * zynqmp_disp_plane_atomic_disable() in that case. 1492 */ 1493 old_plane_state = drm_atomic_get_old_plane_state(old_crtc_state->state, 1494 crtc->primary); 1495 if (old_plane_state) 1496 zynqmp_disp_plane_atomic_disable(crtc->primary, old_plane_state); 1497 1498 zynqmp_disp_disable(disp); 1499 1500 drm_crtc_vblank_off(&disp->crtc); 1501 1502 clk_disable_unprepare(disp->pclk); 1503 pm_runtime_put_sync(disp->dev); 1504 } 1505 1506 static int zynqmp_disp_crtc_atomic_check(struct drm_crtc *crtc, 1507 struct drm_crtc_state *state) 1508 { 1509 return drm_atomic_add_affected_planes(state->state, crtc); 1510 } 1511 1512 static void 1513 zynqmp_disp_crtc_atomic_begin(struct drm_crtc *crtc, 1514 struct drm_crtc_state *old_crtc_state) 1515 { 1516 drm_crtc_vblank_on(crtc); 1517 } 1518 1519 static void 1520 zynqmp_disp_crtc_atomic_flush(struct drm_crtc *crtc, 1521 struct drm_crtc_state *old_crtc_state) 1522 { 1523 if (crtc->state->event) { 1524 struct drm_pending_vblank_event *event; 1525 1526 /* Consume the flip_done event from atomic helper. */ 1527 event = crtc->state->event; 1528 crtc->state->event = NULL; 1529 1530 event->pipe = drm_crtc_index(crtc); 1531 1532 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 1533 1534 spin_lock_irq(&crtc->dev->event_lock); 1535 drm_crtc_arm_vblank_event(crtc, event); 1536 spin_unlock_irq(&crtc->dev->event_lock); 1537 } 1538 } 1539 1540 static const struct drm_crtc_helper_funcs zynqmp_disp_crtc_helper_funcs = { 1541 .atomic_enable = zynqmp_disp_crtc_atomic_enable, 1542 .atomic_disable = zynqmp_disp_crtc_atomic_disable, 1543 .atomic_check = zynqmp_disp_crtc_atomic_check, 1544 .atomic_begin = zynqmp_disp_crtc_atomic_begin, 1545 .atomic_flush = zynqmp_disp_crtc_atomic_flush, 1546 }; 1547 1548 static int zynqmp_disp_crtc_enable_vblank(struct drm_crtc *crtc) 1549 { 1550 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1551 1552 zynqmp_dp_enable_vblank(disp->dpsub->dp); 1553 1554 return 0; 1555 } 1556 1557 static void zynqmp_disp_crtc_disable_vblank(struct drm_crtc *crtc) 1558 { 1559 struct zynqmp_disp *disp = crtc_to_disp(crtc); 1560 1561 zynqmp_dp_disable_vblank(disp->dpsub->dp); 1562 } 1563 1564 static const struct drm_crtc_funcs zynqmp_disp_crtc_funcs = { 1565 .destroy = drm_crtc_cleanup, 1566 .set_config = drm_atomic_helper_set_config, 1567 .page_flip = drm_atomic_helper_page_flip, 1568 .reset = drm_atomic_helper_crtc_reset, 1569 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 1570 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 1571 .enable_vblank = zynqmp_disp_crtc_enable_vblank, 1572 .disable_vblank = zynqmp_disp_crtc_disable_vblank, 1573 }; 1574 1575 static int zynqmp_disp_create_crtc(struct zynqmp_disp *disp) 1576 { 1577 struct drm_plane *plane = &disp->layers[ZYNQMP_DISP_LAYER_GFX].plane; 1578 int ret; 1579 1580 ret = drm_crtc_init_with_planes(disp->drm, &disp->crtc, plane, 1581 NULL, &zynqmp_disp_crtc_funcs, NULL); 1582 if (ret < 0) 1583 return ret; 1584 1585 drm_crtc_helper_add(&disp->crtc, &zynqmp_disp_crtc_helper_funcs); 1586 1587 /* Start with vertical blanking interrupt reporting disabled. */ 1588 drm_crtc_vblank_off(&disp->crtc); 1589 1590 return 0; 1591 } 1592 1593 static void zynqmp_disp_map_crtc_to_plane(struct zynqmp_disp *disp) 1594 { 1595 u32 possible_crtcs = drm_crtc_mask(&disp->crtc); 1596 unsigned int i; 1597 1598 for (i = 0; i < ZYNQMP_DISP_NUM_LAYERS; i++) 1599 disp->layers[i].plane.possible_crtcs = possible_crtcs; 1600 } 1601 1602 /* ----------------------------------------------------------------------------- 1603 * Initialization & Cleanup 1604 */ 1605 1606 int zynqmp_disp_drm_init(struct zynqmp_dpsub *dpsub) 1607 { 1608 struct zynqmp_disp *disp = dpsub->disp; 1609 int ret; 1610 1611 ret = zynqmp_disp_create_planes(disp); 1612 if (ret) 1613 return ret; 1614 1615 ret = zynqmp_disp_create_crtc(disp); 1616 if (ret < 0) 1617 return ret; 1618 1619 zynqmp_disp_map_crtc_to_plane(disp); 1620 1621 return 0; 1622 } 1623 1624 int zynqmp_disp_probe(struct zynqmp_dpsub *dpsub, struct drm_device *drm) 1625 { 1626 struct platform_device *pdev = to_platform_device(dpsub->dev); 1627 struct zynqmp_disp *disp; 1628 struct zynqmp_disp_layer *layer; 1629 struct resource *res; 1630 int ret; 1631 1632 disp = drmm_kzalloc(drm, sizeof(*disp), GFP_KERNEL); 1633 if (!disp) 1634 return -ENOMEM; 1635 1636 disp->dev = &pdev->dev; 1637 disp->dpsub = dpsub; 1638 disp->drm = drm; 1639 1640 dpsub->disp = disp; 1641 1642 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "blend"); 1643 disp->blend.base = devm_ioremap_resource(disp->dev, res); 1644 if (IS_ERR(disp->blend.base)) 1645 return PTR_ERR(disp->blend.base); 1646 1647 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "av_buf"); 1648 disp->avbuf.base = devm_ioremap_resource(disp->dev, res); 1649 if (IS_ERR(disp->avbuf.base)) 1650 return PTR_ERR(disp->avbuf.base); 1651 1652 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aud"); 1653 disp->audio.base = devm_ioremap_resource(disp->dev, res); 1654 if (IS_ERR(disp->audio.base)) 1655 return PTR_ERR(disp->audio.base); 1656 1657 /* Try the live PL video clock */ 1658 disp->pclk = devm_clk_get(disp->dev, "dp_live_video_in_clk"); 1659 if (!IS_ERR(disp->pclk)) 1660 disp->pclk_from_ps = false; 1661 else if (PTR_ERR(disp->pclk) == -EPROBE_DEFER) 1662 return PTR_ERR(disp->pclk); 1663 1664 /* If the live PL video clock is not valid, fall back to PS clock */ 1665 if (IS_ERR_OR_NULL(disp->pclk)) { 1666 disp->pclk = devm_clk_get(disp->dev, "dp_vtc_pixel_clk_in"); 1667 if (IS_ERR(disp->pclk)) { 1668 dev_err(disp->dev, "failed to init any video clock\n"); 1669 return PTR_ERR(disp->pclk); 1670 } 1671 disp->pclk_from_ps = true; 1672 } 1673 1674 zynqmp_disp_audio_init(disp->dev, &disp->audio); 1675 1676 ret = zynqmp_disp_create_layers(disp); 1677 if (ret) 1678 return ret; 1679 1680 layer = &disp->layers[ZYNQMP_DISP_LAYER_VID]; 1681 dpsub->dma_align = 1 << layer->dmas[0].chan->device->copy_align; 1682 1683 return 0; 1684 } 1685 1686 void zynqmp_disp_remove(struct zynqmp_dpsub *dpsub) 1687 { 1688 struct zynqmp_disp *disp = dpsub->disp; 1689 1690 zynqmp_disp_destroy_layers(disp); 1691 } 1692