1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /****************************************************************************** 3 * 4 * COPYRIGHT (C) 2014-2015 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 ******************************************************************************/ 27 28 #include "vmwgfx_kms.h" 29 #include "device_include/svga3d_surfacedefs.h" 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_atomic_helper.h> 33 #include <drm/drm_damage_helper.h> 34 35 #define vmw_crtc_to_stdu(x) \ 36 container_of(x, struct vmw_screen_target_display_unit, base.crtc) 37 #define vmw_encoder_to_stdu(x) \ 38 container_of(x, struct vmw_screen_target_display_unit, base.encoder) 39 #define vmw_connector_to_stdu(x) \ 40 container_of(x, struct vmw_screen_target_display_unit, base.connector) 41 42 43 44 enum stdu_content_type { 45 SAME_AS_DISPLAY = 0, 46 SEPARATE_SURFACE, 47 SEPARATE_BO 48 }; 49 50 /** 51 * struct vmw_stdu_dirty - closure structure for the update functions 52 * 53 * @base: The base type we derive from. Used by vmw_kms_helper_dirty(). 54 * @transfer: Transfer direction for DMA command. 55 * @left: Left side of bounding box. 56 * @right: Right side of bounding box. 57 * @top: Top side of bounding box. 58 * @bottom: Bottom side of bounding box. 59 * @fb_left: Left side of the framebuffer/content bounding box 60 * @fb_top: Top of the framebuffer/content bounding box 61 * @buf: buffer object when DMA-ing between buffer and screen targets. 62 * @sid: Surface ID when copying between surface and screen targets. 63 */ 64 struct vmw_stdu_dirty { 65 struct vmw_kms_dirty base; 66 SVGA3dTransferType transfer; 67 s32 left, right, top, bottom; 68 s32 fb_left, fb_top; 69 u32 pitch; 70 union { 71 struct vmw_buffer_object *buf; 72 u32 sid; 73 }; 74 }; 75 76 /* 77 * SVGA commands that are used by this code. Please see the device headers 78 * for explanation. 79 */ 80 struct vmw_stdu_update { 81 SVGA3dCmdHeader header; 82 SVGA3dCmdUpdateGBScreenTarget body; 83 }; 84 85 struct vmw_stdu_dma { 86 SVGA3dCmdHeader header; 87 SVGA3dCmdSurfaceDMA body; 88 }; 89 90 struct vmw_stdu_surface_copy { 91 SVGA3dCmdHeader header; 92 SVGA3dCmdSurfaceCopy body; 93 }; 94 95 struct vmw_stdu_update_gb_image { 96 SVGA3dCmdHeader header; 97 SVGA3dCmdUpdateGBImage body; 98 }; 99 100 /** 101 * struct vmw_screen_target_display_unit 102 * 103 * @base: VMW specific DU structure 104 * @display_srf: surface to be displayed. The dimension of this will always 105 * match the display mode. If the display mode matches 106 * content_vfbs dimensions, then this is a pointer into the 107 * corresponding field in content_vfbs. If not, then this 108 * is a separate buffer to which content_vfbs will blit to. 109 * @content_type: content_fb type 110 * @defined: true if the current display unit has been initialized 111 */ 112 struct vmw_screen_target_display_unit { 113 struct vmw_display_unit base; 114 struct vmw_surface *display_srf; 115 enum stdu_content_type content_fb_type; 116 s32 display_width, display_height; 117 118 bool defined; 119 120 /* For CPU Blit */ 121 unsigned int cpp; 122 }; 123 124 125 126 static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu); 127 128 129 130 /****************************************************************************** 131 * Screen Target Display Unit CRTC Functions 132 *****************************************************************************/ 133 134 135 /** 136 * vmw_stdu_crtc_destroy - cleans up the STDU 137 * 138 * @crtc: used to get a reference to the containing STDU 139 */ 140 static void vmw_stdu_crtc_destroy(struct drm_crtc *crtc) 141 { 142 vmw_stdu_destroy(vmw_crtc_to_stdu(crtc)); 143 } 144 145 /** 146 * vmw_stdu_define_st - Defines a Screen Target 147 * 148 * @dev_priv: VMW DRM device 149 * @stdu: display unit to create a Screen Target for 150 * @mode: The mode to set. 151 * @crtc_x: X coordinate of screen target relative to framebuffer origin. 152 * @crtc_y: Y coordinate of screen target relative to framebuffer origin. 153 * 154 * Creates a STDU that we can used later. This function is called whenever the 155 * framebuffer size changes. 156 * 157 * RETURNs: 158 * 0 on success, error code on failure 159 */ 160 static int vmw_stdu_define_st(struct vmw_private *dev_priv, 161 struct vmw_screen_target_display_unit *stdu, 162 struct drm_display_mode *mode, 163 int crtc_x, int crtc_y) 164 { 165 struct { 166 SVGA3dCmdHeader header; 167 SVGA3dCmdDefineGBScreenTarget body; 168 } *cmd; 169 170 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); 171 if (unlikely(cmd == NULL)) 172 return -ENOMEM; 173 174 cmd->header.id = SVGA_3D_CMD_DEFINE_GB_SCREENTARGET; 175 cmd->header.size = sizeof(cmd->body); 176 177 cmd->body.stid = stdu->base.unit; 178 cmd->body.width = mode->hdisplay; 179 cmd->body.height = mode->vdisplay; 180 cmd->body.flags = (0 == cmd->body.stid) ? SVGA_STFLAG_PRIMARY : 0; 181 cmd->body.dpi = 0; 182 cmd->body.xRoot = crtc_x; 183 cmd->body.yRoot = crtc_y; 184 185 stdu->base.set_gui_x = cmd->body.xRoot; 186 stdu->base.set_gui_y = cmd->body.yRoot; 187 188 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 189 190 stdu->defined = true; 191 stdu->display_width = mode->hdisplay; 192 stdu->display_height = mode->vdisplay; 193 194 return 0; 195 } 196 197 198 199 /** 200 * vmw_stdu_bind_st - Binds a surface to a Screen Target 201 * 202 * @dev_priv: VMW DRM device 203 * @stdu: display unit affected 204 * @res: Buffer to bind to the screen target. Set to NULL to blank screen. 205 * 206 * Binding a surface to a Screen Target the same as flipping 207 */ 208 static int vmw_stdu_bind_st(struct vmw_private *dev_priv, 209 struct vmw_screen_target_display_unit *stdu, 210 const struct vmw_resource *res) 211 { 212 SVGA3dSurfaceImageId image; 213 214 struct { 215 SVGA3dCmdHeader header; 216 SVGA3dCmdBindGBScreenTarget body; 217 } *cmd; 218 219 220 if (!stdu->defined) { 221 DRM_ERROR("No screen target defined\n"); 222 return -EINVAL; 223 } 224 225 /* Set up image using information in vfb */ 226 memset(&image, 0, sizeof(image)); 227 image.sid = res ? res->id : SVGA3D_INVALID_ID; 228 229 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); 230 if (unlikely(cmd == NULL)) 231 return -ENOMEM; 232 233 cmd->header.id = SVGA_3D_CMD_BIND_GB_SCREENTARGET; 234 cmd->header.size = sizeof(cmd->body); 235 236 cmd->body.stid = stdu->base.unit; 237 cmd->body.image = image; 238 239 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 240 241 return 0; 242 } 243 244 /** 245 * vmw_stdu_populate_update - populate an UPDATE_GB_SCREENTARGET command with a 246 * bounding box. 247 * 248 * @cmd: Pointer to command stream. 249 * @unit: Screen target unit. 250 * @left: Left side of bounding box. 251 * @right: Right side of bounding box. 252 * @top: Top side of bounding box. 253 * @bottom: Bottom side of bounding box. 254 */ 255 static void vmw_stdu_populate_update(void *cmd, int unit, 256 s32 left, s32 right, s32 top, s32 bottom) 257 { 258 struct vmw_stdu_update *update = cmd; 259 260 update->header.id = SVGA_3D_CMD_UPDATE_GB_SCREENTARGET; 261 update->header.size = sizeof(update->body); 262 263 update->body.stid = unit; 264 update->body.rect.x = left; 265 update->body.rect.y = top; 266 update->body.rect.w = right - left; 267 update->body.rect.h = bottom - top; 268 } 269 270 /** 271 * vmw_stdu_update_st - Full update of a Screen Target 272 * 273 * @dev_priv: VMW DRM device 274 * @stdu: display unit affected 275 * 276 * This function needs to be called whenever the content of a screen 277 * target has changed completely. Typically as a result of a backing 278 * surface change. 279 * 280 * RETURNS: 281 * 0 on success, error code on failure 282 */ 283 static int vmw_stdu_update_st(struct vmw_private *dev_priv, 284 struct vmw_screen_target_display_unit *stdu) 285 { 286 struct vmw_stdu_update *cmd; 287 288 if (!stdu->defined) { 289 DRM_ERROR("No screen target defined"); 290 return -EINVAL; 291 } 292 293 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); 294 if (unlikely(cmd == NULL)) 295 return -ENOMEM; 296 297 vmw_stdu_populate_update(cmd, stdu->base.unit, 298 0, stdu->display_width, 299 0, stdu->display_height); 300 301 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 302 303 return 0; 304 } 305 306 307 308 /** 309 * vmw_stdu_destroy_st - Destroy a Screen Target 310 * 311 * @dev_priv: VMW DRM device 312 * @stdu: display unit to destroy 313 */ 314 static int vmw_stdu_destroy_st(struct vmw_private *dev_priv, 315 struct vmw_screen_target_display_unit *stdu) 316 { 317 int ret; 318 319 struct { 320 SVGA3dCmdHeader header; 321 SVGA3dCmdDestroyGBScreenTarget body; 322 } *cmd; 323 324 325 /* Nothing to do if not successfully defined */ 326 if (unlikely(!stdu->defined)) 327 return 0; 328 329 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); 330 if (unlikely(cmd == NULL)) 331 return -ENOMEM; 332 333 cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SCREENTARGET; 334 cmd->header.size = sizeof(cmd->body); 335 336 cmd->body.stid = stdu->base.unit; 337 338 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 339 340 /* Force sync */ 341 ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ); 342 if (unlikely(ret != 0)) 343 DRM_ERROR("Failed to sync with HW"); 344 345 stdu->defined = false; 346 stdu->display_width = 0; 347 stdu->display_height = 0; 348 349 return ret; 350 } 351 352 353 /** 354 * vmw_stdu_crtc_mode_set_nofb - Updates screen target size 355 * 356 * @crtc: CRTC associated with the screen target 357 * 358 * This function defines/destroys a screen target 359 * 360 */ 361 static void vmw_stdu_crtc_mode_set_nofb(struct drm_crtc *crtc) 362 { 363 struct vmw_private *dev_priv; 364 struct vmw_screen_target_display_unit *stdu; 365 struct drm_connector_state *conn_state; 366 struct vmw_connector_state *vmw_conn_state; 367 int x, y, ret; 368 369 stdu = vmw_crtc_to_stdu(crtc); 370 dev_priv = vmw_priv(crtc->dev); 371 conn_state = stdu->base.connector.state; 372 vmw_conn_state = vmw_connector_state_to_vcs(conn_state); 373 374 if (stdu->defined) { 375 ret = vmw_stdu_bind_st(dev_priv, stdu, NULL); 376 if (ret) 377 DRM_ERROR("Failed to blank CRTC\n"); 378 379 (void) vmw_stdu_update_st(dev_priv, stdu); 380 381 ret = vmw_stdu_destroy_st(dev_priv, stdu); 382 if (ret) 383 DRM_ERROR("Failed to destroy Screen Target\n"); 384 385 stdu->content_fb_type = SAME_AS_DISPLAY; 386 } 387 388 if (!crtc->state->enable) 389 return; 390 391 x = vmw_conn_state->gui_x; 392 y = vmw_conn_state->gui_y; 393 394 vmw_svga_enable(dev_priv); 395 ret = vmw_stdu_define_st(dev_priv, stdu, &crtc->mode, x, y); 396 397 if (ret) 398 DRM_ERROR("Failed to define Screen Target of size %dx%d\n", 399 crtc->x, crtc->y); 400 } 401 402 403 static void vmw_stdu_crtc_helper_prepare(struct drm_crtc *crtc) 404 { 405 } 406 407 static void vmw_stdu_crtc_atomic_enable(struct drm_crtc *crtc, 408 struct drm_crtc_state *old_state) 409 { 410 } 411 412 static void vmw_stdu_crtc_atomic_disable(struct drm_crtc *crtc, 413 struct drm_crtc_state *old_state) 414 { 415 struct vmw_private *dev_priv; 416 struct vmw_screen_target_display_unit *stdu; 417 int ret; 418 419 420 if (!crtc) { 421 DRM_ERROR("CRTC is NULL\n"); 422 return; 423 } 424 425 stdu = vmw_crtc_to_stdu(crtc); 426 dev_priv = vmw_priv(crtc->dev); 427 428 if (stdu->defined) { 429 ret = vmw_stdu_bind_st(dev_priv, stdu, NULL); 430 if (ret) 431 DRM_ERROR("Failed to blank CRTC\n"); 432 433 (void) vmw_stdu_update_st(dev_priv, stdu); 434 435 ret = vmw_stdu_destroy_st(dev_priv, stdu); 436 if (ret) 437 DRM_ERROR("Failed to destroy Screen Target\n"); 438 439 stdu->content_fb_type = SAME_AS_DISPLAY; 440 } 441 } 442 443 /** 444 * vmw_stdu_bo_clip - Callback to encode a suface DMA command cliprect 445 * 446 * @dirty: The closure structure. 447 * 448 * Encodes a surface DMA command cliprect and updates the bounding box 449 * for the DMA. 450 */ 451 static void vmw_stdu_bo_clip(struct vmw_kms_dirty *dirty) 452 { 453 struct vmw_stdu_dirty *ddirty = 454 container_of(dirty, struct vmw_stdu_dirty, base); 455 struct vmw_stdu_dma *cmd = dirty->cmd; 456 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1]; 457 458 blit += dirty->num_hits; 459 blit->srcx = dirty->fb_x; 460 blit->srcy = dirty->fb_y; 461 blit->x = dirty->unit_x1; 462 blit->y = dirty->unit_y1; 463 blit->d = 1; 464 blit->w = dirty->unit_x2 - dirty->unit_x1; 465 blit->h = dirty->unit_y2 - dirty->unit_y1; 466 dirty->num_hits++; 467 468 if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM) 469 return; 470 471 /* Destination bounding box */ 472 ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1); 473 ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1); 474 ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2); 475 ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2); 476 } 477 478 /** 479 * vmw_stdu_bo_fifo_commit - Callback to fill in and submit a DMA command. 480 * 481 * @dirty: The closure structure. 482 * 483 * Fills in the missing fields in a DMA command, and optionally encodes 484 * a screen target update command, depending on transfer direction. 485 */ 486 static void vmw_stdu_bo_fifo_commit(struct vmw_kms_dirty *dirty) 487 { 488 struct vmw_stdu_dirty *ddirty = 489 container_of(dirty, struct vmw_stdu_dirty, base); 490 struct vmw_screen_target_display_unit *stdu = 491 container_of(dirty->unit, typeof(*stdu), base); 492 struct vmw_stdu_dma *cmd = dirty->cmd; 493 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1]; 494 SVGA3dCmdSurfaceDMASuffix *suffix = 495 (SVGA3dCmdSurfaceDMASuffix *) &blit[dirty->num_hits]; 496 size_t blit_size = sizeof(*blit) * dirty->num_hits + sizeof(*suffix); 497 498 if (!dirty->num_hits) { 499 vmw_fifo_commit(dirty->dev_priv, 0); 500 return; 501 } 502 503 cmd->header.id = SVGA_3D_CMD_SURFACE_DMA; 504 cmd->header.size = sizeof(cmd->body) + blit_size; 505 vmw_bo_get_guest_ptr(&ddirty->buf->base, &cmd->body.guest.ptr); 506 cmd->body.guest.pitch = ddirty->pitch; 507 cmd->body.host.sid = stdu->display_srf->res.id; 508 cmd->body.host.face = 0; 509 cmd->body.host.mipmap = 0; 510 cmd->body.transfer = ddirty->transfer; 511 suffix->suffixSize = sizeof(*suffix); 512 suffix->maximumOffset = ddirty->buf->base.num_pages * PAGE_SIZE; 513 514 if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM) { 515 blit_size += sizeof(struct vmw_stdu_update); 516 517 vmw_stdu_populate_update(&suffix[1], stdu->base.unit, 518 ddirty->left, ddirty->right, 519 ddirty->top, ddirty->bottom); 520 } 521 522 vmw_fifo_commit(dirty->dev_priv, sizeof(*cmd) + blit_size); 523 524 stdu->display_srf->res.res_dirty = true; 525 ddirty->left = ddirty->top = S32_MAX; 526 ddirty->right = ddirty->bottom = S32_MIN; 527 } 528 529 530 /** 531 * vmw_stdu_bo_cpu_clip - Callback to encode a CPU blit 532 * 533 * @dirty: The closure structure. 534 * 535 * This function calculates the bounding box for all the incoming clips. 536 */ 537 static void vmw_stdu_bo_cpu_clip(struct vmw_kms_dirty *dirty) 538 { 539 struct vmw_stdu_dirty *ddirty = 540 container_of(dirty, struct vmw_stdu_dirty, base); 541 542 dirty->num_hits = 1; 543 544 /* Calculate destination bounding box */ 545 ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1); 546 ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1); 547 ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2); 548 ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2); 549 550 /* 551 * Calculate content bounding box. We only need the top-left 552 * coordinate because width and height will be the same as the 553 * destination bounding box above 554 */ 555 ddirty->fb_left = min_t(s32, ddirty->fb_left, dirty->fb_x); 556 ddirty->fb_top = min_t(s32, ddirty->fb_top, dirty->fb_y); 557 } 558 559 560 /** 561 * vmw_stdu_bo_cpu_commit - Callback to do a CPU blit from buffer object 562 * 563 * @dirty: The closure structure. 564 * 565 * For the special case when we cannot create a proxy surface in a 566 * 2D VM, we have to do a CPU blit ourselves. 567 */ 568 static void vmw_stdu_bo_cpu_commit(struct vmw_kms_dirty *dirty) 569 { 570 struct vmw_stdu_dirty *ddirty = 571 container_of(dirty, struct vmw_stdu_dirty, base); 572 struct vmw_screen_target_display_unit *stdu = 573 container_of(dirty->unit, typeof(*stdu), base); 574 s32 width, height; 575 s32 src_pitch, dst_pitch; 576 struct ttm_buffer_object *src_bo, *dst_bo; 577 u32 src_offset, dst_offset; 578 struct vmw_diff_cpy diff = VMW_CPU_BLIT_DIFF_INITIALIZER(stdu->cpp); 579 580 if (!dirty->num_hits) 581 return; 582 583 width = ddirty->right - ddirty->left; 584 height = ddirty->bottom - ddirty->top; 585 586 if (width == 0 || height == 0) 587 return; 588 589 /* Assume we are blitting from Guest (bo) to Host (display_srf) */ 590 dst_pitch = stdu->display_srf->base_size.width * stdu->cpp; 591 dst_bo = &stdu->display_srf->res.backup->base; 592 dst_offset = ddirty->top * dst_pitch + ddirty->left * stdu->cpp; 593 594 src_pitch = ddirty->pitch; 595 src_bo = &ddirty->buf->base; 596 src_offset = ddirty->fb_top * src_pitch + ddirty->fb_left * stdu->cpp; 597 598 /* Swap src and dst if the assumption was wrong. */ 599 if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM) { 600 swap(dst_pitch, src_pitch); 601 swap(dst_bo, src_bo); 602 swap(src_offset, dst_offset); 603 } 604 605 (void) vmw_bo_cpu_blit(dst_bo, dst_offset, dst_pitch, 606 src_bo, src_offset, src_pitch, 607 width * stdu->cpp, height, &diff); 608 609 if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM && 610 drm_rect_visible(&diff.rect)) { 611 struct vmw_private *dev_priv; 612 struct vmw_stdu_update *cmd; 613 struct drm_clip_rect region; 614 int ret; 615 616 /* We are updating the actual surface, not a proxy */ 617 region.x1 = diff.rect.x1; 618 region.x2 = diff.rect.x2; 619 region.y1 = diff.rect.y1; 620 region.y2 = diff.rect.y2; 621 ret = vmw_kms_update_proxy(&stdu->display_srf->res, ®ion, 622 1, 1); 623 if (ret) 624 goto out_cleanup; 625 626 627 dev_priv = vmw_priv(stdu->base.crtc.dev); 628 cmd = VMW_FIFO_RESERVE(dev_priv, sizeof(*cmd)); 629 if (!cmd) 630 goto out_cleanup; 631 632 vmw_stdu_populate_update(cmd, stdu->base.unit, 633 region.x1, region.x2, 634 region.y1, region.y2); 635 636 vmw_fifo_commit(dev_priv, sizeof(*cmd)); 637 } 638 639 out_cleanup: 640 ddirty->left = ddirty->top = ddirty->fb_left = ddirty->fb_top = S32_MAX; 641 ddirty->right = ddirty->bottom = S32_MIN; 642 } 643 644 /** 645 * vmw_kms_stdu_dma - Perform a DMA transfer between a buffer-object backed 646 * framebuffer and the screen target system. 647 * 648 * @dev_priv: Pointer to the device private structure. 649 * @file_priv: Pointer to a struct drm-file identifying the caller. May be 650 * set to NULL, but then @user_fence_rep must also be set to NULL. 651 * @vfb: Pointer to the buffer-object backed framebuffer. 652 * @clips: Array of clip rects. Either @clips or @vclips must be NULL. 653 * @vclips: Alternate array of clip rects. Either @clips or @vclips must 654 * be NULL. 655 * @num_clips: Number of clip rects in @clips or @vclips. 656 * @increment: Increment to use when looping over @clips or @vclips. 657 * @to_surface: Whether to DMA to the screen target system as opposed to 658 * from the screen target system. 659 * @interruptible: Whether to perform waits interruptible if possible. 660 * @crtc: If crtc is passed, perform stdu dma on that crtc only. 661 * 662 * If DMA-ing till the screen target system, the function will also notify 663 * the screen target system that a bounding box of the cliprects has been 664 * updated. 665 * Returns 0 on success, negative error code on failure. -ERESTARTSYS if 666 * interrupted. 667 */ 668 int vmw_kms_stdu_dma(struct vmw_private *dev_priv, 669 struct drm_file *file_priv, 670 struct vmw_framebuffer *vfb, 671 struct drm_vmw_fence_rep __user *user_fence_rep, 672 struct drm_clip_rect *clips, 673 struct drm_vmw_rect *vclips, 674 uint32_t num_clips, 675 int increment, 676 bool to_surface, 677 bool interruptible, 678 struct drm_crtc *crtc) 679 { 680 struct vmw_buffer_object *buf = 681 container_of(vfb, struct vmw_framebuffer_bo, base)->buffer; 682 struct vmw_stdu_dirty ddirty; 683 int ret; 684 bool cpu_blit = !(dev_priv->capabilities & SVGA_CAP_3D); 685 DECLARE_VAL_CONTEXT(val_ctx, NULL, 0); 686 687 /* 688 * VMs without 3D support don't have the surface DMA command and 689 * we'll be using a CPU blit, and the framebuffer should be moved out 690 * of VRAM. 691 */ 692 ret = vmw_validation_add_bo(&val_ctx, buf, false, cpu_blit); 693 if (ret) 694 return ret; 695 696 ret = vmw_validation_prepare(&val_ctx, NULL, interruptible); 697 if (ret) 698 goto out_unref; 699 700 ddirty.transfer = (to_surface) ? SVGA3D_WRITE_HOST_VRAM : 701 SVGA3D_READ_HOST_VRAM; 702 ddirty.left = ddirty.top = S32_MAX; 703 ddirty.right = ddirty.bottom = S32_MIN; 704 ddirty.fb_left = ddirty.fb_top = S32_MAX; 705 ddirty.pitch = vfb->base.pitches[0]; 706 ddirty.buf = buf; 707 ddirty.base.fifo_commit = vmw_stdu_bo_fifo_commit; 708 ddirty.base.clip = vmw_stdu_bo_clip; 709 ddirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_dma) + 710 num_clips * sizeof(SVGA3dCopyBox) + 711 sizeof(SVGA3dCmdSurfaceDMASuffix); 712 if (to_surface) 713 ddirty.base.fifo_reserve_size += sizeof(struct vmw_stdu_update); 714 715 716 if (cpu_blit) { 717 ddirty.base.fifo_commit = vmw_stdu_bo_cpu_commit; 718 ddirty.base.clip = vmw_stdu_bo_cpu_clip; 719 ddirty.base.fifo_reserve_size = 0; 720 } 721 722 ddirty.base.crtc = crtc; 723 724 ret = vmw_kms_helper_dirty(dev_priv, vfb, clips, vclips, 725 0, 0, num_clips, increment, &ddirty.base); 726 727 vmw_kms_helper_validation_finish(dev_priv, file_priv, &val_ctx, NULL, 728 user_fence_rep); 729 return ret; 730 731 out_unref: 732 vmw_validation_unref_lists(&val_ctx); 733 return ret; 734 } 735 736 /** 737 * vmw_stdu_surface_clip - Callback to encode a surface copy command cliprect 738 * 739 * @dirty: The closure structure. 740 * 741 * Encodes a surface copy command cliprect and updates the bounding box 742 * for the copy. 743 */ 744 static void vmw_kms_stdu_surface_clip(struct vmw_kms_dirty *dirty) 745 { 746 struct vmw_stdu_dirty *sdirty = 747 container_of(dirty, struct vmw_stdu_dirty, base); 748 struct vmw_stdu_surface_copy *cmd = dirty->cmd; 749 struct vmw_screen_target_display_unit *stdu = 750 container_of(dirty->unit, typeof(*stdu), base); 751 752 if (sdirty->sid != stdu->display_srf->res.id) { 753 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1]; 754 755 blit += dirty->num_hits; 756 blit->srcx = dirty->fb_x; 757 blit->srcy = dirty->fb_y; 758 blit->x = dirty->unit_x1; 759 blit->y = dirty->unit_y1; 760 blit->d = 1; 761 blit->w = dirty->unit_x2 - dirty->unit_x1; 762 blit->h = dirty->unit_y2 - dirty->unit_y1; 763 } 764 765 dirty->num_hits++; 766 767 /* Destination bounding box */ 768 sdirty->left = min_t(s32, sdirty->left, dirty->unit_x1); 769 sdirty->top = min_t(s32, sdirty->top, dirty->unit_y1); 770 sdirty->right = max_t(s32, sdirty->right, dirty->unit_x2); 771 sdirty->bottom = max_t(s32, sdirty->bottom, dirty->unit_y2); 772 } 773 774 /** 775 * vmw_stdu_surface_fifo_commit - Callback to fill in and submit a surface 776 * copy command. 777 * 778 * @dirty: The closure structure. 779 * 780 * Fills in the missing fields in a surface copy command, and encodes a screen 781 * target update command. 782 */ 783 static void vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty *dirty) 784 { 785 struct vmw_stdu_dirty *sdirty = 786 container_of(dirty, struct vmw_stdu_dirty, base); 787 struct vmw_screen_target_display_unit *stdu = 788 container_of(dirty->unit, typeof(*stdu), base); 789 struct vmw_stdu_surface_copy *cmd = dirty->cmd; 790 struct vmw_stdu_update *update; 791 size_t blit_size = sizeof(SVGA3dCopyBox) * dirty->num_hits; 792 size_t commit_size; 793 794 if (!dirty->num_hits) { 795 vmw_fifo_commit(dirty->dev_priv, 0); 796 return; 797 } 798 799 if (sdirty->sid != stdu->display_srf->res.id) { 800 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1]; 801 802 cmd->header.id = SVGA_3D_CMD_SURFACE_COPY; 803 cmd->header.size = sizeof(cmd->body) + blit_size; 804 cmd->body.src.sid = sdirty->sid; 805 cmd->body.dest.sid = stdu->display_srf->res.id; 806 update = (struct vmw_stdu_update *) &blit[dirty->num_hits]; 807 commit_size = sizeof(*cmd) + blit_size + sizeof(*update); 808 stdu->display_srf->res.res_dirty = true; 809 } else { 810 update = dirty->cmd; 811 commit_size = sizeof(*update); 812 } 813 814 vmw_stdu_populate_update(update, stdu->base.unit, sdirty->left, 815 sdirty->right, sdirty->top, sdirty->bottom); 816 817 vmw_fifo_commit(dirty->dev_priv, commit_size); 818 819 sdirty->left = sdirty->top = S32_MAX; 820 sdirty->right = sdirty->bottom = S32_MIN; 821 } 822 823 /** 824 * vmw_kms_stdu_surface_dirty - Dirty part of a surface backed framebuffer 825 * 826 * @dev_priv: Pointer to the device private structure. 827 * @framebuffer: Pointer to the surface-buffer backed framebuffer. 828 * @clips: Array of clip rects. Either @clips or @vclips must be NULL. 829 * @vclips: Alternate array of clip rects. Either @clips or @vclips must 830 * be NULL. 831 * @srf: Pointer to surface to blit from. If NULL, the surface attached 832 * to @framebuffer will be used. 833 * @dest_x: X coordinate offset to align @srf with framebuffer coordinates. 834 * @dest_y: Y coordinate offset to align @srf with framebuffer coordinates. 835 * @num_clips: Number of clip rects in @clips. 836 * @inc: Increment to use when looping over @clips. 837 * @out_fence: If non-NULL, will return a ref-counted pointer to a 838 * struct vmw_fence_obj. The returned fence pointer may be NULL in which 839 * case the device has already synchronized. 840 * @crtc: If crtc is passed, perform surface dirty on that crtc only. 841 * 842 * Returns 0 on success, negative error code on failure. -ERESTARTSYS if 843 * interrupted. 844 */ 845 int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv, 846 struct vmw_framebuffer *framebuffer, 847 struct drm_clip_rect *clips, 848 struct drm_vmw_rect *vclips, 849 struct vmw_resource *srf, 850 s32 dest_x, 851 s32 dest_y, 852 unsigned num_clips, int inc, 853 struct vmw_fence_obj **out_fence, 854 struct drm_crtc *crtc) 855 { 856 struct vmw_framebuffer_surface *vfbs = 857 container_of(framebuffer, typeof(*vfbs), base); 858 struct vmw_stdu_dirty sdirty; 859 DECLARE_VAL_CONTEXT(val_ctx, NULL, 0); 860 int ret; 861 862 if (!srf) 863 srf = &vfbs->surface->res; 864 865 ret = vmw_validation_add_resource(&val_ctx, srf, 0, VMW_RES_DIRTY_NONE, 866 NULL, NULL); 867 if (ret) 868 return ret; 869 870 ret = vmw_validation_prepare(&val_ctx, &dev_priv->cmdbuf_mutex, true); 871 if (ret) 872 goto out_unref; 873 874 if (vfbs->is_bo_proxy) { 875 ret = vmw_kms_update_proxy(srf, clips, num_clips, inc); 876 if (ret) 877 goto out_finish; 878 } 879 880 sdirty.base.fifo_commit = vmw_kms_stdu_surface_fifo_commit; 881 sdirty.base.clip = vmw_kms_stdu_surface_clip; 882 sdirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_surface_copy) + 883 sizeof(SVGA3dCopyBox) * num_clips + 884 sizeof(struct vmw_stdu_update); 885 sdirty.base.crtc = crtc; 886 sdirty.sid = srf->id; 887 sdirty.left = sdirty.top = S32_MAX; 888 sdirty.right = sdirty.bottom = S32_MIN; 889 890 ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips, 891 dest_x, dest_y, num_clips, inc, 892 &sdirty.base); 893 out_finish: 894 vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence, 895 NULL); 896 897 return ret; 898 899 out_unref: 900 vmw_validation_unref_lists(&val_ctx); 901 return ret; 902 } 903 904 905 /* 906 * Screen Target CRTC dispatch table 907 */ 908 static const struct drm_crtc_funcs vmw_stdu_crtc_funcs = { 909 .gamma_set = vmw_du_crtc_gamma_set, 910 .destroy = vmw_stdu_crtc_destroy, 911 .reset = vmw_du_crtc_reset, 912 .atomic_duplicate_state = vmw_du_crtc_duplicate_state, 913 .atomic_destroy_state = vmw_du_crtc_destroy_state, 914 .set_config = drm_atomic_helper_set_config, 915 .page_flip = drm_atomic_helper_page_flip, 916 }; 917 918 919 920 /****************************************************************************** 921 * Screen Target Display Unit Encoder Functions 922 *****************************************************************************/ 923 924 /** 925 * vmw_stdu_encoder_destroy - cleans up the STDU 926 * 927 * @encoder: used the get the containing STDU 928 * 929 * vmwgfx cleans up crtc/encoder/connector all at the same time so technically 930 * this can be a no-op. Nevertheless, it doesn't hurt of have this in case 931 * the common KMS code changes and somehow vmw_stdu_crtc_destroy() doesn't 932 * get called. 933 */ 934 static void vmw_stdu_encoder_destroy(struct drm_encoder *encoder) 935 { 936 vmw_stdu_destroy(vmw_encoder_to_stdu(encoder)); 937 } 938 939 static const struct drm_encoder_funcs vmw_stdu_encoder_funcs = { 940 .destroy = vmw_stdu_encoder_destroy, 941 }; 942 943 944 945 /****************************************************************************** 946 * Screen Target Display Unit Connector Functions 947 *****************************************************************************/ 948 949 /** 950 * vmw_stdu_connector_destroy - cleans up the STDU 951 * 952 * @connector: used to get the containing STDU 953 * 954 * vmwgfx cleans up crtc/encoder/connector all at the same time so technically 955 * this can be a no-op. Nevertheless, it doesn't hurt of have this in case 956 * the common KMS code changes and somehow vmw_stdu_crtc_destroy() doesn't 957 * get called. 958 */ 959 static void vmw_stdu_connector_destroy(struct drm_connector *connector) 960 { 961 vmw_stdu_destroy(vmw_connector_to_stdu(connector)); 962 } 963 964 965 966 static const struct drm_connector_funcs vmw_stdu_connector_funcs = { 967 .dpms = vmw_du_connector_dpms, 968 .detect = vmw_du_connector_detect, 969 .fill_modes = vmw_du_connector_fill_modes, 970 .destroy = vmw_stdu_connector_destroy, 971 .reset = vmw_du_connector_reset, 972 .atomic_duplicate_state = vmw_du_connector_duplicate_state, 973 .atomic_destroy_state = vmw_du_connector_destroy_state, 974 }; 975 976 977 static const struct 978 drm_connector_helper_funcs vmw_stdu_connector_helper_funcs = { 979 }; 980 981 982 983 /****************************************************************************** 984 * Screen Target Display Plane Functions 985 *****************************************************************************/ 986 987 988 989 /** 990 * vmw_stdu_primary_plane_cleanup_fb - Unpins the display surface 991 * 992 * @plane: display plane 993 * @old_state: Contains the FB to clean up 994 * 995 * Unpins the display surface 996 * 997 * Returns 0 on success 998 */ 999 static void 1000 vmw_stdu_primary_plane_cleanup_fb(struct drm_plane *plane, 1001 struct drm_plane_state *old_state) 1002 { 1003 struct vmw_plane_state *vps = vmw_plane_state_to_vps(old_state); 1004 1005 if (vps->surf) 1006 WARN_ON(!vps->pinned); 1007 1008 vmw_du_plane_cleanup_fb(plane, old_state); 1009 1010 vps->content_fb_type = SAME_AS_DISPLAY; 1011 vps->cpp = 0; 1012 } 1013 1014 1015 1016 /** 1017 * vmw_stdu_primary_plane_prepare_fb - Readies the display surface 1018 * 1019 * @plane: display plane 1020 * @new_state: info on the new plane state, including the FB 1021 * 1022 * This function allocates a new display surface if the content is 1023 * backed by a buffer object. The display surface is pinned here, and it'll 1024 * be unpinned in .cleanup_fb() 1025 * 1026 * Returns 0 on success 1027 */ 1028 static int 1029 vmw_stdu_primary_plane_prepare_fb(struct drm_plane *plane, 1030 struct drm_plane_state *new_state) 1031 { 1032 struct vmw_private *dev_priv = vmw_priv(plane->dev); 1033 struct drm_framebuffer *new_fb = new_state->fb; 1034 struct vmw_framebuffer *vfb; 1035 struct vmw_plane_state *vps = vmw_plane_state_to_vps(new_state); 1036 enum stdu_content_type new_content_type; 1037 struct vmw_framebuffer_surface *new_vfbs; 1038 struct drm_crtc *crtc = new_state->crtc; 1039 uint32_t hdisplay = new_state->crtc_w, vdisplay = new_state->crtc_h; 1040 int ret; 1041 1042 /* No FB to prepare */ 1043 if (!new_fb) { 1044 if (vps->surf) { 1045 WARN_ON(vps->pinned != 0); 1046 vmw_surface_unreference(&vps->surf); 1047 } 1048 1049 return 0; 1050 } 1051 1052 vfb = vmw_framebuffer_to_vfb(new_fb); 1053 new_vfbs = (vfb->bo) ? NULL : vmw_framebuffer_to_vfbs(new_fb); 1054 1055 if (new_vfbs && new_vfbs->surface->base_size.width == hdisplay && 1056 new_vfbs->surface->base_size.height == vdisplay) 1057 new_content_type = SAME_AS_DISPLAY; 1058 else if (vfb->bo) 1059 new_content_type = SEPARATE_BO; 1060 else 1061 new_content_type = SEPARATE_SURFACE; 1062 1063 if (new_content_type != SAME_AS_DISPLAY) { 1064 struct vmw_surface content_srf; 1065 struct drm_vmw_size display_base_size = {0}; 1066 1067 display_base_size.width = hdisplay; 1068 display_base_size.height = vdisplay; 1069 display_base_size.depth = 1; 1070 1071 /* 1072 * If content buffer is a buffer object, then we have to 1073 * construct surface info 1074 */ 1075 if (new_content_type == SEPARATE_BO) { 1076 1077 switch (new_fb->format->cpp[0]*8) { 1078 case 32: 1079 content_srf.format = SVGA3D_X8R8G8B8; 1080 break; 1081 1082 case 16: 1083 content_srf.format = SVGA3D_R5G6B5; 1084 break; 1085 1086 case 8: 1087 content_srf.format = SVGA3D_P8; 1088 break; 1089 1090 default: 1091 DRM_ERROR("Invalid format\n"); 1092 return -EINVAL; 1093 } 1094 1095 content_srf.flags = 0; 1096 content_srf.mip_levels[0] = 1; 1097 content_srf.multisample_count = 0; 1098 content_srf.multisample_pattern = 1099 SVGA3D_MS_PATTERN_NONE; 1100 content_srf.quality_level = SVGA3D_MS_QUALITY_NONE; 1101 } else { 1102 content_srf = *new_vfbs->surface; 1103 } 1104 1105 if (vps->surf) { 1106 struct drm_vmw_size cur_base_size = vps->surf->base_size; 1107 1108 if (cur_base_size.width != display_base_size.width || 1109 cur_base_size.height != display_base_size.height || 1110 vps->surf->format != content_srf.format) { 1111 WARN_ON(vps->pinned != 0); 1112 vmw_surface_unreference(&vps->surf); 1113 } 1114 1115 } 1116 1117 if (!vps->surf) { 1118 ret = vmw_surface_gb_priv_define 1119 (crtc->dev, 1120 /* Kernel visible only */ 1121 0, 1122 content_srf.flags, 1123 content_srf.format, 1124 true, /* a scanout buffer */ 1125 content_srf.mip_levels[0], 1126 content_srf.multisample_count, 1127 0, 1128 display_base_size, 1129 content_srf.multisample_pattern, 1130 content_srf.quality_level, 1131 &vps->surf); 1132 if (ret != 0) { 1133 DRM_ERROR("Couldn't allocate STDU surface.\n"); 1134 return ret; 1135 } 1136 } 1137 } else { 1138 /* 1139 * prepare_fb and clean_fb should only take care of pinning 1140 * and unpinning. References are tracked by state objects. 1141 * The only time we add a reference in prepare_fb is if the 1142 * state object doesn't have a reference to begin with 1143 */ 1144 if (vps->surf) { 1145 WARN_ON(vps->pinned != 0); 1146 vmw_surface_unreference(&vps->surf); 1147 } 1148 1149 vps->surf = vmw_surface_reference(new_vfbs->surface); 1150 } 1151 1152 if (vps->surf) { 1153 1154 /* Pin new surface before flipping */ 1155 ret = vmw_resource_pin(&vps->surf->res, false); 1156 if (ret) 1157 goto out_srf_unref; 1158 1159 vps->pinned++; 1160 } 1161 1162 vps->content_fb_type = new_content_type; 1163 1164 /* 1165 * This should only happen if the buffer object is too large to create a 1166 * proxy surface for. 1167 * If we are a 2D VM with a buffer object then we have to use CPU blit 1168 * so cache these mappings 1169 */ 1170 if (vps->content_fb_type == SEPARATE_BO && 1171 !(dev_priv->capabilities & SVGA_CAP_3D)) 1172 vps->cpp = new_fb->pitches[0] / new_fb->width; 1173 1174 return 0; 1175 1176 out_srf_unref: 1177 vmw_surface_unreference(&vps->surf); 1178 return ret; 1179 } 1180 1181 static uint32_t vmw_stdu_bo_fifo_size(struct vmw_du_update_plane *update, 1182 uint32_t num_hits) 1183 { 1184 return sizeof(struct vmw_stdu_dma) + sizeof(SVGA3dCopyBox) * num_hits + 1185 sizeof(SVGA3dCmdSurfaceDMASuffix) + 1186 sizeof(struct vmw_stdu_update); 1187 } 1188 1189 static uint32_t vmw_stdu_bo_fifo_size_cpu(struct vmw_du_update_plane *update, 1190 uint32_t num_hits) 1191 { 1192 return sizeof(struct vmw_stdu_update_gb_image) + 1193 sizeof(struct vmw_stdu_update); 1194 } 1195 1196 static uint32_t vmw_stdu_bo_populate_dma(struct vmw_du_update_plane *update, 1197 void *cmd, uint32_t num_hits) 1198 { 1199 struct vmw_screen_target_display_unit *stdu; 1200 struct vmw_framebuffer_bo *vfbbo; 1201 struct vmw_stdu_dma *cmd_dma = cmd; 1202 1203 stdu = container_of(update->du, typeof(*stdu), base); 1204 vfbbo = container_of(update->vfb, typeof(*vfbbo), base); 1205 1206 cmd_dma->header.id = SVGA_3D_CMD_SURFACE_DMA; 1207 cmd_dma->header.size = sizeof(cmd_dma->body) + 1208 sizeof(struct SVGA3dCopyBox) * num_hits + 1209 sizeof(SVGA3dCmdSurfaceDMASuffix); 1210 vmw_bo_get_guest_ptr(&vfbbo->buffer->base, &cmd_dma->body.guest.ptr); 1211 cmd_dma->body.guest.pitch = update->vfb->base.pitches[0]; 1212 cmd_dma->body.host.sid = stdu->display_srf->res.id; 1213 cmd_dma->body.host.face = 0; 1214 cmd_dma->body.host.mipmap = 0; 1215 cmd_dma->body.transfer = SVGA3D_WRITE_HOST_VRAM; 1216 1217 return sizeof(*cmd_dma); 1218 } 1219 1220 static uint32_t vmw_stdu_bo_populate_clip(struct vmw_du_update_plane *update, 1221 void *cmd, struct drm_rect *clip, 1222 uint32_t fb_x, uint32_t fb_y) 1223 { 1224 struct SVGA3dCopyBox *box = cmd; 1225 1226 box->srcx = fb_x; 1227 box->srcy = fb_y; 1228 box->srcz = 0; 1229 box->x = clip->x1; 1230 box->y = clip->y1; 1231 box->z = 0; 1232 box->w = drm_rect_width(clip); 1233 box->h = drm_rect_height(clip); 1234 box->d = 1; 1235 1236 return sizeof(*box); 1237 } 1238 1239 static uint32_t vmw_stdu_bo_populate_update(struct vmw_du_update_plane *update, 1240 void *cmd, struct drm_rect *bb) 1241 { 1242 struct vmw_screen_target_display_unit *stdu; 1243 struct vmw_framebuffer_bo *vfbbo; 1244 SVGA3dCmdSurfaceDMASuffix *suffix = cmd; 1245 1246 stdu = container_of(update->du, typeof(*stdu), base); 1247 vfbbo = container_of(update->vfb, typeof(*vfbbo), base); 1248 1249 suffix->suffixSize = sizeof(*suffix); 1250 suffix->maximumOffset = vfbbo->buffer->base.num_pages * PAGE_SIZE; 1251 1252 vmw_stdu_populate_update(&suffix[1], stdu->base.unit, bb->x1, bb->x2, 1253 bb->y1, bb->y2); 1254 1255 return sizeof(*suffix) + sizeof(struct vmw_stdu_update); 1256 } 1257 1258 static uint32_t vmw_stdu_bo_pre_clip_cpu(struct vmw_du_update_plane *update, 1259 void *cmd, uint32_t num_hits) 1260 { 1261 struct vmw_du_update_plane_buffer *bo_update = 1262 container_of(update, typeof(*bo_update), base); 1263 1264 bo_update->fb_left = INT_MAX; 1265 bo_update->fb_top = INT_MAX; 1266 1267 return 0; 1268 } 1269 1270 static uint32_t vmw_stdu_bo_clip_cpu(struct vmw_du_update_plane *update, 1271 void *cmd, struct drm_rect *clip, 1272 uint32_t fb_x, uint32_t fb_y) 1273 { 1274 struct vmw_du_update_plane_buffer *bo_update = 1275 container_of(update, typeof(*bo_update), base); 1276 1277 bo_update->fb_left = min_t(int, bo_update->fb_left, fb_x); 1278 bo_update->fb_top = min_t(int, bo_update->fb_top, fb_y); 1279 1280 return 0; 1281 } 1282 1283 static uint32_t 1284 vmw_stdu_bo_populate_update_cpu(struct vmw_du_update_plane *update, void *cmd, 1285 struct drm_rect *bb) 1286 { 1287 struct vmw_du_update_plane_buffer *bo_update; 1288 struct vmw_screen_target_display_unit *stdu; 1289 struct vmw_framebuffer_bo *vfbbo; 1290 struct vmw_diff_cpy diff = VMW_CPU_BLIT_DIFF_INITIALIZER(0); 1291 struct vmw_stdu_update_gb_image *cmd_img = cmd; 1292 struct vmw_stdu_update *cmd_update; 1293 struct ttm_buffer_object *src_bo, *dst_bo; 1294 u32 src_offset, dst_offset; 1295 s32 src_pitch, dst_pitch; 1296 s32 width, height; 1297 1298 bo_update = container_of(update, typeof(*bo_update), base); 1299 stdu = container_of(update->du, typeof(*stdu), base); 1300 vfbbo = container_of(update->vfb, typeof(*vfbbo), base); 1301 1302 width = bb->x2 - bb->x1; 1303 height = bb->y2 - bb->y1; 1304 1305 diff.cpp = stdu->cpp; 1306 1307 dst_bo = &stdu->display_srf->res.backup->base; 1308 dst_pitch = stdu->display_srf->base_size.width * stdu->cpp; 1309 dst_offset = bb->y1 * dst_pitch + bb->x1 * stdu->cpp; 1310 1311 src_bo = &vfbbo->buffer->base; 1312 src_pitch = update->vfb->base.pitches[0]; 1313 src_offset = bo_update->fb_top * src_pitch + bo_update->fb_left * 1314 stdu->cpp; 1315 1316 (void) vmw_bo_cpu_blit(dst_bo, dst_offset, dst_pitch, src_bo, 1317 src_offset, src_pitch, width * stdu->cpp, height, 1318 &diff); 1319 1320 if (drm_rect_visible(&diff.rect)) { 1321 SVGA3dBox *box = &cmd_img->body.box; 1322 1323 cmd_img->header.id = SVGA_3D_CMD_UPDATE_GB_IMAGE; 1324 cmd_img->header.size = sizeof(cmd_img->body); 1325 cmd_img->body.image.sid = stdu->display_srf->res.id; 1326 cmd_img->body.image.face = 0; 1327 cmd_img->body.image.mipmap = 0; 1328 1329 box->x = diff.rect.x1; 1330 box->y = diff.rect.y1; 1331 box->z = 0; 1332 box->w = drm_rect_width(&diff.rect); 1333 box->h = drm_rect_height(&diff.rect); 1334 box->d = 1; 1335 1336 cmd_update = (struct vmw_stdu_update *)&cmd_img[1]; 1337 vmw_stdu_populate_update(cmd_update, stdu->base.unit, 1338 diff.rect.x1, diff.rect.x2, 1339 diff.rect.y1, diff.rect.y2); 1340 1341 return sizeof(*cmd_img) + sizeof(*cmd_update); 1342 } 1343 1344 return 0; 1345 } 1346 1347 /** 1348 * vmw_stdu_plane_update_bo - Update display unit for bo backed fb. 1349 * @dev_priv: device private. 1350 * @plane: plane state. 1351 * @old_state: old plane state. 1352 * @vfb: framebuffer which is blitted to display unit. 1353 * @out_fence: If non-NULL, will return a ref-counted pointer to vmw_fence_obj. 1354 * The returned fence pointer may be NULL in which case the device 1355 * has already synchronized. 1356 * 1357 * Return: 0 on success or a negative error code on failure. 1358 */ 1359 static int vmw_stdu_plane_update_bo(struct vmw_private *dev_priv, 1360 struct drm_plane *plane, 1361 struct drm_plane_state *old_state, 1362 struct vmw_framebuffer *vfb, 1363 struct vmw_fence_obj **out_fence) 1364 { 1365 struct vmw_du_update_plane_buffer bo_update; 1366 1367 memset(&bo_update, 0, sizeof(struct vmw_du_update_plane_buffer)); 1368 bo_update.base.plane = plane; 1369 bo_update.base.old_state = old_state; 1370 bo_update.base.dev_priv = dev_priv; 1371 bo_update.base.du = vmw_crtc_to_du(plane->state->crtc); 1372 bo_update.base.vfb = vfb; 1373 bo_update.base.out_fence = out_fence; 1374 bo_update.base.mutex = NULL; 1375 bo_update.base.cpu_blit = !(dev_priv->capabilities & SVGA_CAP_3D); 1376 bo_update.base.intr = false; 1377 1378 /* 1379 * VM without 3D support don't have surface DMA command and framebuffer 1380 * should be moved out of VRAM. 1381 */ 1382 if (bo_update.base.cpu_blit) { 1383 bo_update.base.calc_fifo_size = vmw_stdu_bo_fifo_size_cpu; 1384 bo_update.base.pre_clip = vmw_stdu_bo_pre_clip_cpu; 1385 bo_update.base.clip = vmw_stdu_bo_clip_cpu; 1386 bo_update.base.post_clip = vmw_stdu_bo_populate_update_cpu; 1387 } else { 1388 bo_update.base.calc_fifo_size = vmw_stdu_bo_fifo_size; 1389 bo_update.base.pre_clip = vmw_stdu_bo_populate_dma; 1390 bo_update.base.clip = vmw_stdu_bo_populate_clip; 1391 bo_update.base.post_clip = vmw_stdu_bo_populate_update; 1392 } 1393 1394 return vmw_du_helper_plane_update(&bo_update.base); 1395 } 1396 1397 static uint32_t 1398 vmw_stdu_surface_fifo_size_same_display(struct vmw_du_update_plane *update, 1399 uint32_t num_hits) 1400 { 1401 struct vmw_framebuffer_surface *vfbs; 1402 uint32_t size = 0; 1403 1404 vfbs = container_of(update->vfb, typeof(*vfbs), base); 1405 1406 if (vfbs->is_bo_proxy) 1407 size += sizeof(struct vmw_stdu_update_gb_image) * num_hits; 1408 1409 size += sizeof(struct vmw_stdu_update); 1410 1411 return size; 1412 } 1413 1414 static uint32_t vmw_stdu_surface_fifo_size(struct vmw_du_update_plane *update, 1415 uint32_t num_hits) 1416 { 1417 struct vmw_framebuffer_surface *vfbs; 1418 uint32_t size = 0; 1419 1420 vfbs = container_of(update->vfb, typeof(*vfbs), base); 1421 1422 if (vfbs->is_bo_proxy) 1423 size += sizeof(struct vmw_stdu_update_gb_image) * num_hits; 1424 1425 size += sizeof(struct vmw_stdu_surface_copy) + sizeof(SVGA3dCopyBox) * 1426 num_hits + sizeof(struct vmw_stdu_update); 1427 1428 return size; 1429 } 1430 1431 static uint32_t 1432 vmw_stdu_surface_update_proxy(struct vmw_du_update_plane *update, void *cmd) 1433 { 1434 struct vmw_framebuffer_surface *vfbs; 1435 struct drm_plane_state *state = update->plane->state; 1436 struct drm_plane_state *old_state = update->old_state; 1437 struct vmw_stdu_update_gb_image *cmd_update = cmd; 1438 struct drm_atomic_helper_damage_iter iter; 1439 struct drm_rect clip; 1440 uint32_t copy_size = 0; 1441 1442 vfbs = container_of(update->vfb, typeof(*vfbs), base); 1443 1444 /* 1445 * proxy surface is special where a buffer object type fb is wrapped 1446 * in a surface and need an update gb image command to sync with device. 1447 */ 1448 drm_atomic_helper_damage_iter_init(&iter, old_state, state); 1449 drm_atomic_for_each_plane_damage(&iter, &clip) { 1450 SVGA3dBox *box = &cmd_update->body.box; 1451 1452 cmd_update->header.id = SVGA_3D_CMD_UPDATE_GB_IMAGE; 1453 cmd_update->header.size = sizeof(cmd_update->body); 1454 cmd_update->body.image.sid = vfbs->surface->res.id; 1455 cmd_update->body.image.face = 0; 1456 cmd_update->body.image.mipmap = 0; 1457 1458 box->x = clip.x1; 1459 box->y = clip.y1; 1460 box->z = 0; 1461 box->w = drm_rect_width(&clip); 1462 box->h = drm_rect_height(&clip); 1463 box->d = 1; 1464 1465 copy_size += sizeof(*cmd_update); 1466 cmd_update++; 1467 } 1468 1469 return copy_size; 1470 } 1471 1472 static uint32_t 1473 vmw_stdu_surface_populate_copy(struct vmw_du_update_plane *update, void *cmd, 1474 uint32_t num_hits) 1475 { 1476 struct vmw_screen_target_display_unit *stdu; 1477 struct vmw_framebuffer_surface *vfbs; 1478 struct vmw_stdu_surface_copy *cmd_copy = cmd; 1479 1480 stdu = container_of(update->du, typeof(*stdu), base); 1481 vfbs = container_of(update->vfb, typeof(*vfbs), base); 1482 1483 cmd_copy->header.id = SVGA_3D_CMD_SURFACE_COPY; 1484 cmd_copy->header.size = sizeof(cmd_copy->body) + sizeof(SVGA3dCopyBox) * 1485 num_hits; 1486 cmd_copy->body.src.sid = vfbs->surface->res.id; 1487 cmd_copy->body.dest.sid = stdu->display_srf->res.id; 1488 1489 return sizeof(*cmd_copy); 1490 } 1491 1492 static uint32_t 1493 vmw_stdu_surface_populate_clip(struct vmw_du_update_plane *update, void *cmd, 1494 struct drm_rect *clip, uint32_t fb_x, 1495 uint32_t fb_y) 1496 { 1497 struct SVGA3dCopyBox *box = cmd; 1498 1499 box->srcx = fb_x; 1500 box->srcy = fb_y; 1501 box->srcz = 0; 1502 box->x = clip->x1; 1503 box->y = clip->y1; 1504 box->z = 0; 1505 box->w = drm_rect_width(clip); 1506 box->h = drm_rect_height(clip); 1507 box->d = 1; 1508 1509 return sizeof(*box); 1510 } 1511 1512 static uint32_t 1513 vmw_stdu_surface_populate_update(struct vmw_du_update_plane *update, void *cmd, 1514 struct drm_rect *bb) 1515 { 1516 vmw_stdu_populate_update(cmd, update->du->unit, bb->x1, bb->x2, bb->y1, 1517 bb->y2); 1518 1519 return sizeof(struct vmw_stdu_update); 1520 } 1521 1522 /** 1523 * vmw_stdu_plane_update_surface - Update display unit for surface backed fb 1524 * @dev_priv: Device private 1525 * @plane: Plane state 1526 * @old_state: Old plane state 1527 * @vfb: Framebuffer which is blitted to display unit 1528 * @out_fence: If non-NULL, will return a ref-counted pointer to vmw_fence_obj. 1529 * The returned fence pointer may be NULL in which case the device 1530 * has already synchronized. 1531 * 1532 * Return: 0 on success or a negative error code on failure. 1533 */ 1534 static int vmw_stdu_plane_update_surface(struct vmw_private *dev_priv, 1535 struct drm_plane *plane, 1536 struct drm_plane_state *old_state, 1537 struct vmw_framebuffer *vfb, 1538 struct vmw_fence_obj **out_fence) 1539 { 1540 struct vmw_du_update_plane srf_update; 1541 struct vmw_screen_target_display_unit *stdu; 1542 struct vmw_framebuffer_surface *vfbs; 1543 1544 stdu = vmw_crtc_to_stdu(plane->state->crtc); 1545 vfbs = container_of(vfb, typeof(*vfbs), base); 1546 1547 memset(&srf_update, 0, sizeof(struct vmw_du_update_plane)); 1548 srf_update.plane = plane; 1549 srf_update.old_state = old_state; 1550 srf_update.dev_priv = dev_priv; 1551 srf_update.du = vmw_crtc_to_du(plane->state->crtc); 1552 srf_update.vfb = vfb; 1553 srf_update.out_fence = out_fence; 1554 srf_update.mutex = &dev_priv->cmdbuf_mutex; 1555 srf_update.cpu_blit = false; 1556 srf_update.intr = true; 1557 1558 if (vfbs->is_bo_proxy) 1559 srf_update.post_prepare = vmw_stdu_surface_update_proxy; 1560 1561 if (vfbs->surface->res.id != stdu->display_srf->res.id) { 1562 srf_update.calc_fifo_size = vmw_stdu_surface_fifo_size; 1563 srf_update.pre_clip = vmw_stdu_surface_populate_copy; 1564 srf_update.clip = vmw_stdu_surface_populate_clip; 1565 } else { 1566 srf_update.calc_fifo_size = 1567 vmw_stdu_surface_fifo_size_same_display; 1568 } 1569 1570 srf_update.post_clip = vmw_stdu_surface_populate_update; 1571 1572 return vmw_du_helper_plane_update(&srf_update); 1573 } 1574 1575 /** 1576 * vmw_stdu_primary_plane_atomic_update - formally switches STDU to new plane 1577 * @plane: display plane 1578 * @old_state: Only used to get crtc info 1579 * 1580 * Formally update stdu->display_srf to the new plane, and bind the new 1581 * plane STDU. This function is called during the commit phase when 1582 * all the preparation have been done and all the configurations have 1583 * been checked. 1584 */ 1585 static void 1586 vmw_stdu_primary_plane_atomic_update(struct drm_plane *plane, 1587 struct drm_plane_state *old_state) 1588 { 1589 struct vmw_plane_state *vps = vmw_plane_state_to_vps(plane->state); 1590 struct drm_crtc *crtc = plane->state->crtc; 1591 struct vmw_screen_target_display_unit *stdu; 1592 struct drm_pending_vblank_event *event; 1593 struct vmw_fence_obj *fence = NULL; 1594 struct vmw_private *dev_priv; 1595 int ret; 1596 1597 /* If case of device error, maintain consistent atomic state */ 1598 if (crtc && plane->state->fb) { 1599 struct vmw_framebuffer *vfb = 1600 vmw_framebuffer_to_vfb(plane->state->fb); 1601 stdu = vmw_crtc_to_stdu(crtc); 1602 dev_priv = vmw_priv(crtc->dev); 1603 1604 stdu->display_srf = vps->surf; 1605 stdu->content_fb_type = vps->content_fb_type; 1606 stdu->cpp = vps->cpp; 1607 1608 ret = vmw_stdu_bind_st(dev_priv, stdu, &stdu->display_srf->res); 1609 if (ret) 1610 DRM_ERROR("Failed to bind surface to STDU.\n"); 1611 1612 if (vfb->bo) 1613 ret = vmw_stdu_plane_update_bo(dev_priv, plane, 1614 old_state, vfb, &fence); 1615 else 1616 ret = vmw_stdu_plane_update_surface(dev_priv, plane, 1617 old_state, vfb, 1618 &fence); 1619 if (ret) 1620 DRM_ERROR("Failed to update STDU.\n"); 1621 } else { 1622 crtc = old_state->crtc; 1623 stdu = vmw_crtc_to_stdu(crtc); 1624 dev_priv = vmw_priv(crtc->dev); 1625 1626 /* Blank STDU when fb and crtc are NULL */ 1627 if (!stdu->defined) 1628 return; 1629 1630 ret = vmw_stdu_bind_st(dev_priv, stdu, NULL); 1631 if (ret) 1632 DRM_ERROR("Failed to blank STDU\n"); 1633 1634 ret = vmw_stdu_update_st(dev_priv, stdu); 1635 if (ret) 1636 DRM_ERROR("Failed to update STDU.\n"); 1637 1638 return; 1639 } 1640 1641 /* In case of error, vblank event is send in vmw_du_crtc_atomic_flush */ 1642 event = crtc->state->event; 1643 if (event && fence) { 1644 struct drm_file *file_priv = event->base.file_priv; 1645 1646 ret = vmw_event_fence_action_queue(file_priv, 1647 fence, 1648 &event->base, 1649 &event->event.vbl.tv_sec, 1650 &event->event.vbl.tv_usec, 1651 true); 1652 if (ret) 1653 DRM_ERROR("Failed to queue event on fence.\n"); 1654 else 1655 crtc->state->event = NULL; 1656 } 1657 1658 if (fence) 1659 vmw_fence_obj_unreference(&fence); 1660 } 1661 1662 1663 static const struct drm_plane_funcs vmw_stdu_plane_funcs = { 1664 .update_plane = drm_atomic_helper_update_plane, 1665 .disable_plane = drm_atomic_helper_disable_plane, 1666 .destroy = vmw_du_primary_plane_destroy, 1667 .reset = vmw_du_plane_reset, 1668 .atomic_duplicate_state = vmw_du_plane_duplicate_state, 1669 .atomic_destroy_state = vmw_du_plane_destroy_state, 1670 }; 1671 1672 static const struct drm_plane_funcs vmw_stdu_cursor_funcs = { 1673 .update_plane = drm_atomic_helper_update_plane, 1674 .disable_plane = drm_atomic_helper_disable_plane, 1675 .destroy = vmw_du_cursor_plane_destroy, 1676 .reset = vmw_du_plane_reset, 1677 .atomic_duplicate_state = vmw_du_plane_duplicate_state, 1678 .atomic_destroy_state = vmw_du_plane_destroy_state, 1679 }; 1680 1681 1682 /* 1683 * Atomic Helpers 1684 */ 1685 static const struct 1686 drm_plane_helper_funcs vmw_stdu_cursor_plane_helper_funcs = { 1687 .atomic_check = vmw_du_cursor_plane_atomic_check, 1688 .atomic_update = vmw_du_cursor_plane_atomic_update, 1689 .prepare_fb = vmw_du_cursor_plane_prepare_fb, 1690 .cleanup_fb = vmw_du_plane_cleanup_fb, 1691 }; 1692 1693 static const struct 1694 drm_plane_helper_funcs vmw_stdu_primary_plane_helper_funcs = { 1695 .atomic_check = vmw_du_primary_plane_atomic_check, 1696 .atomic_update = vmw_stdu_primary_plane_atomic_update, 1697 .prepare_fb = vmw_stdu_primary_plane_prepare_fb, 1698 .cleanup_fb = vmw_stdu_primary_plane_cleanup_fb, 1699 }; 1700 1701 static const struct drm_crtc_helper_funcs vmw_stdu_crtc_helper_funcs = { 1702 .prepare = vmw_stdu_crtc_helper_prepare, 1703 .mode_set_nofb = vmw_stdu_crtc_mode_set_nofb, 1704 .atomic_check = vmw_du_crtc_atomic_check, 1705 .atomic_begin = vmw_du_crtc_atomic_begin, 1706 .atomic_flush = vmw_du_crtc_atomic_flush, 1707 .atomic_enable = vmw_stdu_crtc_atomic_enable, 1708 .atomic_disable = vmw_stdu_crtc_atomic_disable, 1709 }; 1710 1711 1712 /** 1713 * vmw_stdu_init - Sets up a Screen Target Display Unit 1714 * 1715 * @dev_priv: VMW DRM device 1716 * @unit: unit number range from 0 to VMWGFX_NUM_DISPLAY_UNITS 1717 * 1718 * This function is called once per CRTC, and allocates one Screen Target 1719 * display unit to represent that CRTC. Since the SVGA device does not separate 1720 * out encoder and connector, they are represented as part of the STDU as well. 1721 */ 1722 static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit) 1723 { 1724 struct vmw_screen_target_display_unit *stdu; 1725 struct drm_device *dev = dev_priv->dev; 1726 struct drm_connector *connector; 1727 struct drm_encoder *encoder; 1728 struct drm_plane *primary, *cursor; 1729 struct drm_crtc *crtc; 1730 int ret; 1731 1732 1733 stdu = kzalloc(sizeof(*stdu), GFP_KERNEL); 1734 if (!stdu) 1735 return -ENOMEM; 1736 1737 stdu->base.unit = unit; 1738 crtc = &stdu->base.crtc; 1739 encoder = &stdu->base.encoder; 1740 connector = &stdu->base.connector; 1741 primary = &stdu->base.primary; 1742 cursor = &stdu->base.cursor; 1743 1744 stdu->base.pref_active = (unit == 0); 1745 stdu->base.pref_width = dev_priv->initial_width; 1746 stdu->base.pref_height = dev_priv->initial_height; 1747 stdu->base.is_implicit = false; 1748 1749 /* Initialize primary plane */ 1750 vmw_du_plane_reset(primary); 1751 1752 ret = drm_universal_plane_init(dev, primary, 1753 0, &vmw_stdu_plane_funcs, 1754 vmw_primary_plane_formats, 1755 ARRAY_SIZE(vmw_primary_plane_formats), 1756 NULL, DRM_PLANE_TYPE_PRIMARY, NULL); 1757 if (ret) { 1758 DRM_ERROR("Failed to initialize primary plane"); 1759 goto err_free; 1760 } 1761 1762 drm_plane_helper_add(primary, &vmw_stdu_primary_plane_helper_funcs); 1763 drm_plane_enable_fb_damage_clips(primary); 1764 1765 /* Initialize cursor plane */ 1766 vmw_du_plane_reset(cursor); 1767 1768 ret = drm_universal_plane_init(dev, cursor, 1769 0, &vmw_stdu_cursor_funcs, 1770 vmw_cursor_plane_formats, 1771 ARRAY_SIZE(vmw_cursor_plane_formats), 1772 NULL, DRM_PLANE_TYPE_CURSOR, NULL); 1773 if (ret) { 1774 DRM_ERROR("Failed to initialize cursor plane"); 1775 drm_plane_cleanup(&stdu->base.primary); 1776 goto err_free; 1777 } 1778 1779 drm_plane_helper_add(cursor, &vmw_stdu_cursor_plane_helper_funcs); 1780 1781 vmw_du_connector_reset(connector); 1782 1783 ret = drm_connector_init(dev, connector, &vmw_stdu_connector_funcs, 1784 DRM_MODE_CONNECTOR_VIRTUAL); 1785 if (ret) { 1786 DRM_ERROR("Failed to initialize connector\n"); 1787 goto err_free; 1788 } 1789 1790 drm_connector_helper_add(connector, &vmw_stdu_connector_helper_funcs); 1791 connector->status = vmw_du_connector_detect(connector, false); 1792 1793 ret = drm_encoder_init(dev, encoder, &vmw_stdu_encoder_funcs, 1794 DRM_MODE_ENCODER_VIRTUAL, NULL); 1795 if (ret) { 1796 DRM_ERROR("Failed to initialize encoder\n"); 1797 goto err_free_connector; 1798 } 1799 1800 (void) drm_connector_attach_encoder(connector, encoder); 1801 encoder->possible_crtcs = (1 << unit); 1802 encoder->possible_clones = 0; 1803 1804 ret = drm_connector_register(connector); 1805 if (ret) { 1806 DRM_ERROR("Failed to register connector\n"); 1807 goto err_free_encoder; 1808 } 1809 1810 vmw_du_crtc_reset(crtc); 1811 ret = drm_crtc_init_with_planes(dev, crtc, &stdu->base.primary, 1812 &stdu->base.cursor, 1813 &vmw_stdu_crtc_funcs, NULL); 1814 if (ret) { 1815 DRM_ERROR("Failed to initialize CRTC\n"); 1816 goto err_free_unregister; 1817 } 1818 1819 drm_crtc_helper_add(crtc, &vmw_stdu_crtc_helper_funcs); 1820 1821 drm_mode_crtc_set_gamma_size(crtc, 256); 1822 1823 drm_object_attach_property(&connector->base, 1824 dev_priv->hotplug_mode_update_property, 1); 1825 drm_object_attach_property(&connector->base, 1826 dev->mode_config.suggested_x_property, 0); 1827 drm_object_attach_property(&connector->base, 1828 dev->mode_config.suggested_y_property, 0); 1829 return 0; 1830 1831 err_free_unregister: 1832 drm_connector_unregister(connector); 1833 err_free_encoder: 1834 drm_encoder_cleanup(encoder); 1835 err_free_connector: 1836 drm_connector_cleanup(connector); 1837 err_free: 1838 kfree(stdu); 1839 return ret; 1840 } 1841 1842 1843 1844 /** 1845 * vmw_stdu_destroy - Cleans up a vmw_screen_target_display_unit 1846 * 1847 * @stdu: Screen Target Display Unit to be destroyed 1848 * 1849 * Clean up after vmw_stdu_init 1850 */ 1851 static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu) 1852 { 1853 vmw_du_cleanup(&stdu->base); 1854 kfree(stdu); 1855 } 1856 1857 1858 1859 /****************************************************************************** 1860 * Screen Target Display KMS Functions 1861 * 1862 * These functions are called by the common KMS code in vmwgfx_kms.c 1863 *****************************************************************************/ 1864 1865 /** 1866 * vmw_kms_stdu_init_display - Initializes a Screen Target based display 1867 * 1868 * @dev_priv: VMW DRM device 1869 * 1870 * This function initialize a Screen Target based display device. It checks 1871 * the capability bits to make sure the underlying hardware can support 1872 * screen targets, and then creates the maximum number of CRTCs, a.k.a Display 1873 * Units, as supported by the display hardware. 1874 * 1875 * RETURNS: 1876 * 0 on success, error code otherwise 1877 */ 1878 int vmw_kms_stdu_init_display(struct vmw_private *dev_priv) 1879 { 1880 struct drm_device *dev = dev_priv->dev; 1881 int i, ret; 1882 1883 1884 /* Do nothing if Screen Target support is turned off */ 1885 if (!VMWGFX_ENABLE_SCREEN_TARGET_OTABLE) 1886 return -ENOSYS; 1887 1888 if (!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS)) 1889 return -ENOSYS; 1890 1891 ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS); 1892 if (unlikely(ret != 0)) 1893 return ret; 1894 1895 dev_priv->active_display_unit = vmw_du_screen_target; 1896 1897 for (i = 0; i < VMWGFX_NUM_DISPLAY_UNITS; ++i) { 1898 ret = vmw_stdu_init(dev_priv, i); 1899 1900 if (unlikely(ret != 0)) { 1901 DRM_ERROR("Failed to initialize STDU %d", i); 1902 return ret; 1903 } 1904 } 1905 1906 DRM_INFO("Screen Target Display device initialized\n"); 1907 1908 return 0; 1909 } 1910