1*523375c9SZack Rusin // SPDX-License-Identifier: GPL-2.0 OR MIT
2*523375c9SZack Rusin /*
3*523375c9SZack Rusin * Copyright 2021 VMware, Inc., Palo Alto, CA., USA
4*523375c9SZack Rusin *
5*523375c9SZack Rusin * Permission is hereby granted, free of charge, to any person obtaining a
6*523375c9SZack Rusin * copy of this software and associated documentation files (the
7*523375c9SZack Rusin * "Software"), to deal in the Software without restriction, including
8*523375c9SZack Rusin * without limitation the rights to use, copy, modify, merge, publish,
9*523375c9SZack Rusin * distribute, sub license, and/or sell copies of the Software, and to
10*523375c9SZack Rusin * permit persons to whom the Software is furnished to do so, subject to
11*523375c9SZack Rusin * the following conditions:
12*523375c9SZack Rusin *
13*523375c9SZack Rusin * The above copyright notice and this permission notice (including the
14*523375c9SZack Rusin * next paragraph) shall be included in all copies or substantial portions
15*523375c9SZack Rusin * of the Software.
16*523375c9SZack Rusin *
17*523375c9SZack Rusin * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18*523375c9SZack Rusin * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19*523375c9SZack Rusin * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20*523375c9SZack Rusin * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
21*523375c9SZack Rusin * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22*523375c9SZack Rusin * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23*523375c9SZack Rusin * USE OR OTHER DEALINGS IN THE SOFTWARE.
24*523375c9SZack Rusin *
25*523375c9SZack Rusin */
26*523375c9SZack Rusin #ifndef _VMWGFX_MSG_ARM64_H
27*523375c9SZack Rusin #define _VMWGFX_MSG_ARM64_H
28*523375c9SZack Rusin
29*523375c9SZack Rusin #if defined(__aarch64__)
30*523375c9SZack Rusin
31*523375c9SZack Rusin #define VMWARE_HYPERVISOR_PORT 0x5658
32*523375c9SZack Rusin #define VMWARE_HYPERVISOR_PORT_HB 0x5659
33*523375c9SZack Rusin
34*523375c9SZack Rusin #define VMWARE_HYPERVISOR_HB BIT(0)
35*523375c9SZack Rusin #define VMWARE_HYPERVISOR_OUT BIT(1)
36*523375c9SZack Rusin
37*523375c9SZack Rusin #define X86_IO_MAGIC 0x86
38*523375c9SZack Rusin
39*523375c9SZack Rusin #define X86_IO_W7_SIZE_SHIFT 0
40*523375c9SZack Rusin #define X86_IO_W7_SIZE_MASK (0x3 << X86_IO_W7_SIZE_SHIFT)
41*523375c9SZack Rusin #define X86_IO_W7_DIR (1 << 2)
42*523375c9SZack Rusin #define X86_IO_W7_WITH (1 << 3)
43*523375c9SZack Rusin #define X86_IO_W7_STR (1 << 4)
44*523375c9SZack Rusin #define X86_IO_W7_DF (1 << 5)
45*523375c9SZack Rusin #define X86_IO_W7_IMM_SHIFT 5
46*523375c9SZack Rusin #define X86_IO_W7_IMM_MASK (0xff << X86_IO_W7_IMM_SHIFT)
47*523375c9SZack Rusin
vmw_port(unsigned long cmd,unsigned long in_ebx,unsigned long in_si,unsigned long in_di,unsigned long flags,unsigned long magic,unsigned long * eax,unsigned long * ebx,unsigned long * ecx,unsigned long * edx,unsigned long * si,unsigned long * di)48*523375c9SZack Rusin static inline void vmw_port(unsigned long cmd, unsigned long in_ebx,
49*523375c9SZack Rusin unsigned long in_si, unsigned long in_di,
50*523375c9SZack Rusin unsigned long flags, unsigned long magic,
51*523375c9SZack Rusin unsigned long *eax, unsigned long *ebx,
52*523375c9SZack Rusin unsigned long *ecx, unsigned long *edx,
53*523375c9SZack Rusin unsigned long *si, unsigned long *di)
54*523375c9SZack Rusin {
55*523375c9SZack Rusin register u64 x0 asm("x0") = magic;
56*523375c9SZack Rusin register u64 x1 asm("x1") = in_ebx;
57*523375c9SZack Rusin register u64 x2 asm("x2") = cmd;
58*523375c9SZack Rusin register u64 x3 asm("x3") = flags | VMWARE_HYPERVISOR_PORT;
59*523375c9SZack Rusin register u64 x4 asm("x4") = in_si;
60*523375c9SZack Rusin register u64 x5 asm("x5") = in_di;
61*523375c9SZack Rusin
62*523375c9SZack Rusin register u64 x7 asm("x7") = ((u64)X86_IO_MAGIC << 32) |
63*523375c9SZack Rusin X86_IO_W7_WITH |
64*523375c9SZack Rusin X86_IO_W7_DIR |
65*523375c9SZack Rusin (2 << X86_IO_W7_SIZE_SHIFT);
66*523375c9SZack Rusin
67*523375c9SZack Rusin asm volatile("mrs xzr, mdccsr_el0 \n\t"
68*523375c9SZack Rusin : "+r"(x0), "+r"(x1), "+r"(x2),
69*523375c9SZack Rusin "+r"(x3), "+r"(x4), "+r"(x5)
70*523375c9SZack Rusin : "r"(x7)
71*523375c9SZack Rusin :);
72*523375c9SZack Rusin *eax = x0;
73*523375c9SZack Rusin *ebx = x1;
74*523375c9SZack Rusin *ecx = x2;
75*523375c9SZack Rusin *edx = x3;
76*523375c9SZack Rusin *si = x4;
77*523375c9SZack Rusin *di = x5;
78*523375c9SZack Rusin }
79*523375c9SZack Rusin
vmw_port_hb(unsigned long cmd,unsigned long in_ecx,unsigned long in_si,unsigned long in_di,unsigned long flags,unsigned long magic,unsigned long bp,u32 w7dir,unsigned long * eax,unsigned long * ebx,unsigned long * ecx,unsigned long * edx,unsigned long * si,unsigned long * di)80*523375c9SZack Rusin static inline void vmw_port_hb(unsigned long cmd, unsigned long in_ecx,
81*523375c9SZack Rusin unsigned long in_si, unsigned long in_di,
82*523375c9SZack Rusin unsigned long flags, unsigned long magic,
83*523375c9SZack Rusin unsigned long bp, u32 w7dir,
84*523375c9SZack Rusin unsigned long *eax, unsigned long *ebx,
85*523375c9SZack Rusin unsigned long *ecx, unsigned long *edx,
86*523375c9SZack Rusin unsigned long *si, unsigned long *di)
87*523375c9SZack Rusin {
88*523375c9SZack Rusin register u64 x0 asm("x0") = magic;
89*523375c9SZack Rusin register u64 x1 asm("x1") = cmd;
90*523375c9SZack Rusin register u64 x2 asm("x2") = in_ecx;
91*523375c9SZack Rusin register u64 x3 asm("x3") = flags | VMWARE_HYPERVISOR_PORT_HB;
92*523375c9SZack Rusin register u64 x4 asm("x4") = in_si;
93*523375c9SZack Rusin register u64 x5 asm("x5") = in_di;
94*523375c9SZack Rusin register u64 x6 asm("x6") = bp;
95*523375c9SZack Rusin register u64 x7 asm("x7") = ((u64)X86_IO_MAGIC << 32) |
96*523375c9SZack Rusin X86_IO_W7_STR |
97*523375c9SZack Rusin X86_IO_W7_WITH |
98*523375c9SZack Rusin w7dir;
99*523375c9SZack Rusin
100*523375c9SZack Rusin asm volatile("mrs xzr, mdccsr_el0 \n\t"
101*523375c9SZack Rusin : "+r"(x0), "+r"(x1), "+r"(x2),
102*523375c9SZack Rusin "+r"(x3), "+r"(x4), "+r"(x5)
103*523375c9SZack Rusin : "r"(x6), "r"(x7)
104*523375c9SZack Rusin :);
105*523375c9SZack Rusin *eax = x0;
106*523375c9SZack Rusin *ebx = x1;
107*523375c9SZack Rusin *ecx = x2;
108*523375c9SZack Rusin *edx = x3;
109*523375c9SZack Rusin *si = x4;
110*523375c9SZack Rusin *di = x5;
111*523375c9SZack Rusin }
112*523375c9SZack Rusin
113*523375c9SZack Rusin #define VMW_PORT(cmd, in_ebx, in_si, in_di, flags, magic, eax, ebx, ecx, edx, \
114*523375c9SZack Rusin si, di) \
115*523375c9SZack Rusin vmw_port(cmd, in_ebx, in_si, in_di, flags, magic, &eax, &ebx, &ecx, \
116*523375c9SZack Rusin &edx, &si, &di)
117*523375c9SZack Rusin
118*523375c9SZack Rusin #define VMW_PORT_HB_OUT(cmd, in_ecx, in_si, in_di, flags, magic, bp, eax, ebx, \
119*523375c9SZack Rusin ecx, edx, si, di) \
120*523375c9SZack Rusin vmw_port_hb(cmd, in_ecx, in_si, in_di, flags, magic, bp, \
121*523375c9SZack Rusin 0, &eax, &ebx, &ecx, &edx, &si, &di)
122*523375c9SZack Rusin
123*523375c9SZack Rusin #define VMW_PORT_HB_IN(cmd, in_ecx, in_si, in_di, flags, magic, bp, eax, ebx, \
124*523375c9SZack Rusin ecx, edx, si, di) \
125*523375c9SZack Rusin vmw_port_hb(cmd, in_ecx, in_si, in_di, flags, magic, bp, \
126*523375c9SZack Rusin X86_IO_W7_DIR, &eax, &ebx, &ecx, &edx, &si, &di)
127*523375c9SZack Rusin
128*523375c9SZack Rusin #endif
129*523375c9SZack Rusin
130*523375c9SZack Rusin #endif /* _VMWGFX_MSG_ARM64_H */
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