1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /**************************************************************************
3  *
4  * Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
25  *
26  **************************************************************************/
27 
28 #include <linux/sched/signal.h>
29 
30 #include "vmwgfx_drv.h"
31 
32 #define VMW_FENCE_WRAP (1 << 24)
33 
34 /**
35  * vmw_thread_fn - Deferred (process context) irq handler
36  *
37  * @irq: irq number
38  * @arg: Closure argument. Pointer to a struct drm_device cast to void *
39  *
40  * This function implements the deferred part of irq processing.
41  * The function is guaranteed to run at least once after the
42  * vmw_irq_handler has returned with IRQ_WAKE_THREAD.
43  *
44  */
45 static irqreturn_t vmw_thread_fn(int irq, void *arg)
46 {
47 	struct drm_device *dev = (struct drm_device *)arg;
48 	struct vmw_private *dev_priv = vmw_priv(dev);
49 	irqreturn_t ret = IRQ_NONE;
50 
51 	if (test_and_clear_bit(VMW_IRQTHREAD_FENCE,
52 			       dev_priv->irqthread_pending)) {
53 		vmw_fences_update(dev_priv->fman);
54 		wake_up_all(&dev_priv->fence_queue);
55 		ret = IRQ_HANDLED;
56 	}
57 
58 	if (test_and_clear_bit(VMW_IRQTHREAD_CMDBUF,
59 			       dev_priv->irqthread_pending)) {
60 		vmw_cmdbuf_irqthread(dev_priv->cman);
61 		ret = IRQ_HANDLED;
62 	}
63 
64 	return ret;
65 }
66 
67 /**
68  * vmw_irq_handler irq handler
69  *
70  * @irq: irq number
71  * @arg: Closure argument. Pointer to a struct drm_device cast to void *
72  *
73  * This function implements the quick part of irq processing.
74  * The function performs fast actions like clearing the device interrupt
75  * flags and also reasonably quick actions like waking processes waiting for
76  * FIFO space. Other IRQ actions are deferred to the IRQ thread.
77  */
78 static irqreturn_t vmw_irq_handler(int irq, void *arg)
79 {
80 	struct drm_device *dev = (struct drm_device *)arg;
81 	struct vmw_private *dev_priv = vmw_priv(dev);
82 	uint32_t status, masked_status;
83 	irqreturn_t ret = IRQ_HANDLED;
84 
85 	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
86 	masked_status = status & READ_ONCE(dev_priv->irq_mask);
87 
88 	if (likely(status))
89 		outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
90 
91 	if (!status)
92 		return IRQ_NONE;
93 
94 	if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS)
95 		wake_up_all(&dev_priv->fifo_queue);
96 
97 	if ((masked_status & (SVGA_IRQFLAG_ANY_FENCE |
98 			      SVGA_IRQFLAG_FENCE_GOAL)) &&
99 	    !test_and_set_bit(VMW_IRQTHREAD_FENCE, dev_priv->irqthread_pending))
100 		ret = IRQ_WAKE_THREAD;
101 
102 	if ((masked_status & (SVGA_IRQFLAG_COMMAND_BUFFER |
103 			      SVGA_IRQFLAG_ERROR)) &&
104 	    !test_and_set_bit(VMW_IRQTHREAD_CMDBUF,
105 			      dev_priv->irqthread_pending))
106 		ret = IRQ_WAKE_THREAD;
107 
108 	return ret;
109 }
110 
111 static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno)
112 {
113 
114 	return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0);
115 }
116 
117 void vmw_update_seqno(struct vmw_private *dev_priv,
118 			 struct vmw_fifo_state *fifo_state)
119 {
120 	uint32_t seqno = vmw_fifo_mem_read(dev_priv, SVGA_FIFO_FENCE);
121 
122 	if (dev_priv->last_read_seqno != seqno) {
123 		dev_priv->last_read_seqno = seqno;
124 		vmw_fences_update(dev_priv->fman);
125 	}
126 }
127 
128 bool vmw_seqno_passed(struct vmw_private *dev_priv,
129 			 uint32_t seqno)
130 {
131 	struct vmw_fifo_state *fifo_state;
132 	bool ret;
133 
134 	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
135 		return true;
136 
137 	fifo_state = &dev_priv->fifo;
138 	vmw_update_seqno(dev_priv, fifo_state);
139 	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
140 		return true;
141 
142 	if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE) &&
143 	    vmw_fifo_idle(dev_priv, seqno))
144 		return true;
145 
146 	/**
147 	 * Then check if the seqno is higher than what we've actually
148 	 * emitted. Then the fence is stale and signaled.
149 	 */
150 
151 	ret = ((atomic_read(&dev_priv->marker_seq) - seqno)
152 	       > VMW_FENCE_WRAP);
153 
154 	return ret;
155 }
156 
157 int vmw_fallback_wait(struct vmw_private *dev_priv,
158 		      bool lazy,
159 		      bool fifo_idle,
160 		      uint32_t seqno,
161 		      bool interruptible,
162 		      unsigned long timeout)
163 {
164 	struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
165 
166 	uint32_t count = 0;
167 	uint32_t signal_seq;
168 	int ret;
169 	unsigned long end_jiffies = jiffies + timeout;
170 	bool (*wait_condition)(struct vmw_private *, uint32_t);
171 	DEFINE_WAIT(__wait);
172 
173 	wait_condition = (fifo_idle) ? &vmw_fifo_idle :
174 		&vmw_seqno_passed;
175 
176 	/**
177 	 * Block command submission while waiting for idle.
178 	 */
179 
180 	if (fifo_idle) {
181 		down_read(&fifo_state->rwsem);
182 		if (dev_priv->cman) {
183 			ret = vmw_cmdbuf_idle(dev_priv->cman, interruptible,
184 					      10*HZ);
185 			if (ret)
186 				goto out_err;
187 		}
188 	}
189 
190 	signal_seq = atomic_read(&dev_priv->marker_seq);
191 	ret = 0;
192 
193 	for (;;) {
194 		prepare_to_wait(&dev_priv->fence_queue, &__wait,
195 				(interruptible) ?
196 				TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
197 		if (wait_condition(dev_priv, seqno))
198 			break;
199 		if (time_after_eq(jiffies, end_jiffies)) {
200 			DRM_ERROR("SVGA device lockup.\n");
201 			break;
202 		}
203 		if (lazy)
204 			schedule_timeout(1);
205 		else if ((++count & 0x0F) == 0) {
206 			/**
207 			 * FIXME: Use schedule_hr_timeout here for
208 			 * newer kernels and lower CPU utilization.
209 			 */
210 
211 			__set_current_state(TASK_RUNNING);
212 			schedule();
213 			__set_current_state((interruptible) ?
214 					    TASK_INTERRUPTIBLE :
215 					    TASK_UNINTERRUPTIBLE);
216 		}
217 		if (interruptible && signal_pending(current)) {
218 			ret = -ERESTARTSYS;
219 			break;
220 		}
221 	}
222 	finish_wait(&dev_priv->fence_queue, &__wait);
223 	if (ret == 0 && fifo_idle)
224 		vmw_fifo_mem_write(dev_priv, SVGA_FIFO_FENCE, signal_seq);
225 
226 	wake_up_all(&dev_priv->fence_queue);
227 out_err:
228 	if (fifo_idle)
229 		up_read(&fifo_state->rwsem);
230 
231 	return ret;
232 }
233 
234 void vmw_generic_waiter_add(struct vmw_private *dev_priv,
235 			    u32 flag, int *waiter_count)
236 {
237 	spin_lock_bh(&dev_priv->waiter_lock);
238 	if ((*waiter_count)++ == 0) {
239 		outl(flag, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
240 		dev_priv->irq_mask |= flag;
241 		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
242 	}
243 	spin_unlock_bh(&dev_priv->waiter_lock);
244 }
245 
246 void vmw_generic_waiter_remove(struct vmw_private *dev_priv,
247 			       u32 flag, int *waiter_count)
248 {
249 	spin_lock_bh(&dev_priv->waiter_lock);
250 	if (--(*waiter_count) == 0) {
251 		dev_priv->irq_mask &= ~flag;
252 		vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
253 	}
254 	spin_unlock_bh(&dev_priv->waiter_lock);
255 }
256 
257 void vmw_seqno_waiter_add(struct vmw_private *dev_priv)
258 {
259 	vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ANY_FENCE,
260 			       &dev_priv->fence_queue_waiters);
261 }
262 
263 void vmw_seqno_waiter_remove(struct vmw_private *dev_priv)
264 {
265 	vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_ANY_FENCE,
266 				  &dev_priv->fence_queue_waiters);
267 }
268 
269 void vmw_goal_waiter_add(struct vmw_private *dev_priv)
270 {
271 	vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
272 			       &dev_priv->goal_queue_waiters);
273 }
274 
275 void vmw_goal_waiter_remove(struct vmw_private *dev_priv)
276 {
277 	vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FENCE_GOAL,
278 				  &dev_priv->goal_queue_waiters);
279 }
280 
281 int vmw_wait_seqno(struct vmw_private *dev_priv,
282 		      bool lazy, uint32_t seqno,
283 		      bool interruptible, unsigned long timeout)
284 {
285 	long ret;
286 	struct vmw_fifo_state *fifo = &dev_priv->fifo;
287 
288 	if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP))
289 		return 0;
290 
291 	if (likely(vmw_seqno_passed(dev_priv, seqno)))
292 		return 0;
293 
294 	vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
295 
296 	if (!(fifo->capabilities & SVGA_FIFO_CAP_FENCE))
297 		return vmw_fallback_wait(dev_priv, lazy, true, seqno,
298 					 interruptible, timeout);
299 
300 	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
301 		return vmw_fallback_wait(dev_priv, lazy, false, seqno,
302 					 interruptible, timeout);
303 
304 	vmw_seqno_waiter_add(dev_priv);
305 
306 	if (interruptible)
307 		ret = wait_event_interruptible_timeout
308 		    (dev_priv->fence_queue,
309 		     vmw_seqno_passed(dev_priv, seqno),
310 		     timeout);
311 	else
312 		ret = wait_event_timeout
313 		    (dev_priv->fence_queue,
314 		     vmw_seqno_passed(dev_priv, seqno),
315 		     timeout);
316 
317 	vmw_seqno_waiter_remove(dev_priv);
318 
319 	if (unlikely(ret == 0))
320 		ret = -EBUSY;
321 	else if (likely(ret > 0))
322 		ret = 0;
323 
324 	return ret;
325 }
326 
327 static void vmw_irq_preinstall(struct drm_device *dev)
328 {
329 	struct vmw_private *dev_priv = vmw_priv(dev);
330 	uint32_t status;
331 
332 	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
333 	outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
334 }
335 
336 void vmw_irq_uninstall(struct drm_device *dev)
337 {
338 	struct vmw_private *dev_priv = vmw_priv(dev);
339 	uint32_t status;
340 
341 	if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
342 		return;
343 
344 	if (!dev->irq_enabled)
345 		return;
346 
347 	vmw_write(dev_priv, SVGA_REG_IRQMASK, 0);
348 
349 	status = inl(dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
350 	outl(status, dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
351 
352 	dev->irq_enabled = false;
353 	free_irq(dev->irq, dev);
354 }
355 
356 /**
357  * vmw_irq_install - Install the irq handlers
358  *
359  * @dev:  Pointer to the drm device.
360  * @irq:  The irq number.
361  * Return:  Zero if successful. Negative number otherwise.
362  */
363 int vmw_irq_install(struct drm_device *dev, int irq)
364 {
365 	int ret;
366 
367 	if (dev->irq_enabled)
368 		return -EBUSY;
369 
370 	vmw_irq_preinstall(dev);
371 
372 	ret = request_threaded_irq(irq, vmw_irq_handler, vmw_thread_fn,
373 				   IRQF_SHARED, VMWGFX_DRIVER_NAME, dev);
374 	if (ret < 0)
375 		return ret;
376 
377 	dev->irq_enabled = true;
378 	dev->irq = irq;
379 
380 	return ret;
381 }
382