1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2015 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include <linux/sched/signal.h> 29 30 #include "vmwgfx_drv.h" 31 32 #define VMW_FENCE_WRAP (1 << 24) 33 34 /** 35 * vmw_thread_fn - Deferred (process context) irq handler 36 * 37 * @irq: irq number 38 * @arg: Closure argument. Pointer to a struct drm_device cast to void * 39 * 40 * This function implements the deferred part of irq processing. 41 * The function is guaranteed to run at least once after the 42 * vmw_irq_handler has returned with IRQ_WAKE_THREAD. 43 * 44 */ 45 static irqreturn_t vmw_thread_fn(int irq, void *arg) 46 { 47 struct drm_device *dev = (struct drm_device *)arg; 48 struct vmw_private *dev_priv = vmw_priv(dev); 49 irqreturn_t ret = IRQ_NONE; 50 51 if (test_and_clear_bit(VMW_IRQTHREAD_FENCE, 52 dev_priv->irqthread_pending)) { 53 vmw_fences_update(dev_priv->fman); 54 wake_up_all(&dev_priv->fence_queue); 55 ret = IRQ_HANDLED; 56 } 57 58 if (test_and_clear_bit(VMW_IRQTHREAD_CMDBUF, 59 dev_priv->irqthread_pending)) { 60 vmw_cmdbuf_irqthread(dev_priv->cman); 61 ret = IRQ_HANDLED; 62 } 63 64 return ret; 65 } 66 67 /** 68 * vmw_irq_handler: irq handler 69 * 70 * @irq: irq number 71 * @arg: Closure argument. Pointer to a struct drm_device cast to void * 72 * 73 * This function implements the quick part of irq processing. 74 * The function performs fast actions like clearing the device interrupt 75 * flags and also reasonably quick actions like waking processes waiting for 76 * FIFO space. Other IRQ actions are deferred to the IRQ thread. 77 */ 78 static irqreturn_t vmw_irq_handler(int irq, void *arg) 79 { 80 struct drm_device *dev = (struct drm_device *)arg; 81 struct vmw_private *dev_priv = vmw_priv(dev); 82 uint32_t status, masked_status; 83 irqreturn_t ret = IRQ_HANDLED; 84 85 status = vmw_irq_status_read(dev_priv); 86 masked_status = status & READ_ONCE(dev_priv->irq_mask); 87 88 if (likely(status)) 89 vmw_irq_status_write(dev_priv, status); 90 91 if (!status) 92 return IRQ_NONE; 93 94 if (masked_status & SVGA_IRQFLAG_FIFO_PROGRESS) 95 wake_up_all(&dev_priv->fifo_queue); 96 97 if ((masked_status & (SVGA_IRQFLAG_ANY_FENCE | 98 SVGA_IRQFLAG_FENCE_GOAL)) && 99 !test_and_set_bit(VMW_IRQTHREAD_FENCE, dev_priv->irqthread_pending)) 100 ret = IRQ_WAKE_THREAD; 101 102 if ((masked_status & (SVGA_IRQFLAG_COMMAND_BUFFER | 103 SVGA_IRQFLAG_ERROR)) && 104 !test_and_set_bit(VMW_IRQTHREAD_CMDBUF, 105 dev_priv->irqthread_pending)) 106 ret = IRQ_WAKE_THREAD; 107 108 return ret; 109 } 110 111 static bool vmw_fifo_idle(struct vmw_private *dev_priv, uint32_t seqno) 112 { 113 114 return (vmw_read(dev_priv, SVGA_REG_BUSY) == 0); 115 } 116 117 void vmw_update_seqno(struct vmw_private *dev_priv) 118 { 119 uint32_t seqno = vmw_fence_read(dev_priv); 120 121 if (dev_priv->last_read_seqno != seqno) { 122 dev_priv->last_read_seqno = seqno; 123 vmw_fences_update(dev_priv->fman); 124 } 125 } 126 127 bool vmw_seqno_passed(struct vmw_private *dev_priv, 128 uint32_t seqno) 129 { 130 bool ret; 131 132 if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) 133 return true; 134 135 vmw_update_seqno(dev_priv); 136 if (likely(dev_priv->last_read_seqno - seqno < VMW_FENCE_WRAP)) 137 return true; 138 139 if (!(vmw_fifo_caps(dev_priv) & SVGA_FIFO_CAP_FENCE) && 140 vmw_fifo_idle(dev_priv, seqno)) 141 return true; 142 143 /** 144 * Then check if the seqno is higher than what we've actually 145 * emitted. Then the fence is stale and signaled. 146 */ 147 148 ret = ((atomic_read(&dev_priv->marker_seq) - seqno) 149 > VMW_FENCE_WRAP); 150 151 return ret; 152 } 153 154 int vmw_fallback_wait(struct vmw_private *dev_priv, 155 bool lazy, 156 bool fifo_idle, 157 uint32_t seqno, 158 bool interruptible, 159 unsigned long timeout) 160 { 161 struct vmw_fifo_state *fifo_state = dev_priv->fifo; 162 163 uint32_t count = 0; 164 uint32_t signal_seq; 165 int ret; 166 unsigned long end_jiffies = jiffies + timeout; 167 bool (*wait_condition)(struct vmw_private *, uint32_t); 168 DEFINE_WAIT(__wait); 169 170 wait_condition = (fifo_idle) ? &vmw_fifo_idle : 171 &vmw_seqno_passed; 172 173 /** 174 * Block command submission while waiting for idle. 175 */ 176 177 if (fifo_idle) { 178 down_read(&fifo_state->rwsem); 179 if (dev_priv->cman) { 180 ret = vmw_cmdbuf_idle(dev_priv->cman, interruptible, 181 10*HZ); 182 if (ret) 183 goto out_err; 184 } 185 } 186 187 signal_seq = atomic_read(&dev_priv->marker_seq); 188 ret = 0; 189 190 for (;;) { 191 prepare_to_wait(&dev_priv->fence_queue, &__wait, 192 (interruptible) ? 193 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); 194 if (wait_condition(dev_priv, seqno)) 195 break; 196 if (time_after_eq(jiffies, end_jiffies)) { 197 DRM_ERROR("SVGA device lockup.\n"); 198 break; 199 } 200 if (lazy) 201 schedule_timeout(1); 202 else if ((++count & 0x0F) == 0) { 203 /** 204 * FIXME: Use schedule_hr_timeout here for 205 * newer kernels and lower CPU utilization. 206 */ 207 208 __set_current_state(TASK_RUNNING); 209 schedule(); 210 __set_current_state((interruptible) ? 211 TASK_INTERRUPTIBLE : 212 TASK_UNINTERRUPTIBLE); 213 } 214 if (interruptible && signal_pending(current)) { 215 ret = -ERESTARTSYS; 216 break; 217 } 218 } 219 finish_wait(&dev_priv->fence_queue, &__wait); 220 if (ret == 0 && fifo_idle) 221 vmw_fence_write(dev_priv, signal_seq); 222 223 wake_up_all(&dev_priv->fence_queue); 224 out_err: 225 if (fifo_idle) 226 up_read(&fifo_state->rwsem); 227 228 return ret; 229 } 230 231 void vmw_generic_waiter_add(struct vmw_private *dev_priv, 232 u32 flag, int *waiter_count) 233 { 234 spin_lock_bh(&dev_priv->waiter_lock); 235 if ((*waiter_count)++ == 0) { 236 vmw_irq_status_write(dev_priv, flag); 237 dev_priv->irq_mask |= flag; 238 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); 239 } 240 spin_unlock_bh(&dev_priv->waiter_lock); 241 } 242 243 void vmw_generic_waiter_remove(struct vmw_private *dev_priv, 244 u32 flag, int *waiter_count) 245 { 246 spin_lock_bh(&dev_priv->waiter_lock); 247 if (--(*waiter_count) == 0) { 248 dev_priv->irq_mask &= ~flag; 249 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); 250 } 251 spin_unlock_bh(&dev_priv->waiter_lock); 252 } 253 254 void vmw_seqno_waiter_add(struct vmw_private *dev_priv) 255 { 256 vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_ANY_FENCE, 257 &dev_priv->fence_queue_waiters); 258 } 259 260 void vmw_seqno_waiter_remove(struct vmw_private *dev_priv) 261 { 262 vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_ANY_FENCE, 263 &dev_priv->fence_queue_waiters); 264 } 265 266 void vmw_goal_waiter_add(struct vmw_private *dev_priv) 267 { 268 vmw_generic_waiter_add(dev_priv, SVGA_IRQFLAG_FENCE_GOAL, 269 &dev_priv->goal_queue_waiters); 270 } 271 272 void vmw_goal_waiter_remove(struct vmw_private *dev_priv) 273 { 274 vmw_generic_waiter_remove(dev_priv, SVGA_IRQFLAG_FENCE_GOAL, 275 &dev_priv->goal_queue_waiters); 276 } 277 278 static void vmw_irq_preinstall(struct drm_device *dev) 279 { 280 struct vmw_private *dev_priv = vmw_priv(dev); 281 uint32_t status; 282 283 status = vmw_irq_status_read(dev_priv); 284 vmw_irq_status_write(dev_priv, status); 285 } 286 287 void vmw_irq_uninstall(struct drm_device *dev) 288 { 289 struct vmw_private *dev_priv = vmw_priv(dev); 290 uint32_t status; 291 292 if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK)) 293 return; 294 295 if (!dev->irq_enabled) 296 return; 297 298 vmw_write(dev_priv, SVGA_REG_IRQMASK, 0); 299 300 status = vmw_irq_status_read(dev_priv); 301 vmw_irq_status_write(dev_priv, status); 302 303 dev->irq_enabled = false; 304 free_irq(dev->irq, dev); 305 } 306 307 /** 308 * vmw_irq_install - Install the irq handlers 309 * 310 * @dev: Pointer to the drm device. 311 * @irq: The irq number. 312 * Return: Zero if successful. Negative number otherwise. 313 */ 314 int vmw_irq_install(struct drm_device *dev, int irq) 315 { 316 int ret; 317 318 if (dev->irq_enabled) 319 return -EBUSY; 320 321 vmw_irq_preinstall(dev); 322 323 ret = request_threaded_irq(irq, vmw_irq_handler, vmw_thread_fn, 324 IRQF_SHARED, VMWGFX_DRIVER_NAME, dev); 325 if (ret < 0) 326 return ret; 327 328 dev->irq_enabled = true; 329 dev->irq = irq; 330 331 return ret; 332 } 333