1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 #include <linux/module.h> 28 #include <linux/console.h> 29 #include <linux/dma-mapping.h> 30 31 #include <drm/drmP.h> 32 #include "vmwgfx_drv.h" 33 #include "vmwgfx_binding.h" 34 #include "ttm_object.h" 35 #include <drm/ttm/ttm_placement.h> 36 #include <drm/ttm/ttm_bo_driver.h> 37 #include <drm/ttm/ttm_module.h> 38 39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 40 #define VMWGFX_CHIP_SVGAII 0 41 #define VMW_FB_RESERVATION 0 42 43 #define VMW_MIN_INITIAL_WIDTH 800 44 #define VMW_MIN_INITIAL_HEIGHT 600 45 46 #ifndef VMWGFX_GIT_VERSION 47 #define VMWGFX_GIT_VERSION "Unknown" 48 #endif 49 50 #define VMWGFX_REPO "In Tree" 51 52 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 53 54 55 /** 56 * Fully encoded drm commands. Might move to vmw_drm.h 57 */ 58 59 #define DRM_IOCTL_VMW_GET_PARAM \ 60 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 61 struct drm_vmw_getparam_arg) 62 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 63 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 64 union drm_vmw_alloc_dmabuf_arg) 65 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 66 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 67 struct drm_vmw_unref_dmabuf_arg) 68 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 69 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 70 struct drm_vmw_cursor_bypass_arg) 71 72 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 73 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 74 struct drm_vmw_control_stream_arg) 75 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 76 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 77 struct drm_vmw_stream_arg) 78 #define DRM_IOCTL_VMW_UNREF_STREAM \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 80 struct drm_vmw_stream_arg) 81 82 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 83 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 84 struct drm_vmw_context_arg) 85 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 86 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 87 struct drm_vmw_context_arg) 88 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 89 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 90 union drm_vmw_surface_create_arg) 91 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 93 struct drm_vmw_surface_arg) 94 #define DRM_IOCTL_VMW_REF_SURFACE \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 96 union drm_vmw_surface_reference_arg) 97 #define DRM_IOCTL_VMW_EXECBUF \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 99 struct drm_vmw_execbuf_arg) 100 #define DRM_IOCTL_VMW_GET_3D_CAP \ 101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 102 struct drm_vmw_get_3d_cap_arg) 103 #define DRM_IOCTL_VMW_FENCE_WAIT \ 104 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 105 struct drm_vmw_fence_wait_arg) 106 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 107 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 108 struct drm_vmw_fence_signaled_arg) 109 #define DRM_IOCTL_VMW_FENCE_UNREF \ 110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 111 struct drm_vmw_fence_arg) 112 #define DRM_IOCTL_VMW_FENCE_EVENT \ 113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 114 struct drm_vmw_fence_event_arg) 115 #define DRM_IOCTL_VMW_PRESENT \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 117 struct drm_vmw_present_arg) 118 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 120 struct drm_vmw_present_readback_arg) 121 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 123 struct drm_vmw_update_layout_arg) 124 #define DRM_IOCTL_VMW_CREATE_SHADER \ 125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 126 struct drm_vmw_shader_create_arg) 127 #define DRM_IOCTL_VMW_UNREF_SHADER \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 129 struct drm_vmw_shader_arg) 130 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 132 union drm_vmw_gb_surface_create_arg) 133 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 134 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 135 union drm_vmw_gb_surface_reference_arg) 136 #define DRM_IOCTL_VMW_SYNCCPU \ 137 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 138 struct drm_vmw_synccpu_arg) 139 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 141 struct drm_vmw_context_arg) 142 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 143 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 144 union drm_vmw_gb_surface_create_ext_arg) 145 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 147 union drm_vmw_gb_surface_reference_ext_arg) 148 149 /** 150 * The core DRM version of this macro doesn't account for 151 * DRM_COMMAND_BASE. 152 */ 153 154 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 155 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 156 157 /** 158 * Ioctl definitions. 159 */ 160 161 static const struct drm_ioctl_desc vmw_ioctls[] = { 162 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 163 DRM_AUTH | DRM_RENDER_ALLOW), 164 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 165 DRM_AUTH | DRM_RENDER_ALLOW), 166 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 167 DRM_RENDER_ALLOW), 168 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 169 vmw_kms_cursor_bypass_ioctl, 170 DRM_MASTER), 171 172 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 173 DRM_MASTER), 174 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 175 DRM_MASTER), 176 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 177 DRM_MASTER), 178 179 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 180 DRM_AUTH | DRM_RENDER_ALLOW), 181 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 182 DRM_RENDER_ALLOW), 183 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 184 DRM_AUTH | DRM_RENDER_ALLOW), 185 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 186 DRM_RENDER_ALLOW), 187 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 188 DRM_AUTH | DRM_RENDER_ALLOW), 189 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | 190 DRM_RENDER_ALLOW), 191 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 192 DRM_RENDER_ALLOW), 193 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 194 vmw_fence_obj_signaled_ioctl, 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 197 DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 199 DRM_AUTH | DRM_RENDER_ALLOW), 200 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 201 DRM_AUTH | DRM_RENDER_ALLOW), 202 203 /* these allow direct access to the framebuffers mark as master only */ 204 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 205 DRM_MASTER | DRM_AUTH), 206 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 207 vmw_present_readback_ioctl, 208 DRM_MASTER | DRM_AUTH), 209 /* 210 * The permissions of the below ioctl are overridden in 211 * vmw_generic_ioctl(). We require either 212 * DRM_MASTER or capable(CAP_SYS_ADMIN). 213 */ 214 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 215 vmw_kms_update_layout_ioctl, 216 DRM_RENDER_ALLOW), 217 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 218 vmw_shader_define_ioctl, 219 DRM_AUTH | DRM_RENDER_ALLOW), 220 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 221 vmw_shader_destroy_ioctl, 222 DRM_RENDER_ALLOW), 223 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 224 vmw_gb_surface_define_ioctl, 225 DRM_AUTH | DRM_RENDER_ALLOW), 226 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 227 vmw_gb_surface_reference_ioctl, 228 DRM_AUTH | DRM_RENDER_ALLOW), 229 VMW_IOCTL_DEF(VMW_SYNCCPU, 230 vmw_user_bo_synccpu_ioctl, 231 DRM_RENDER_ALLOW), 232 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 233 vmw_extended_context_define_ioctl, 234 DRM_AUTH | DRM_RENDER_ALLOW), 235 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 236 vmw_gb_surface_define_ext_ioctl, 237 DRM_AUTH | DRM_RENDER_ALLOW), 238 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 239 vmw_gb_surface_reference_ext_ioctl, 240 DRM_AUTH | DRM_RENDER_ALLOW), 241 }; 242 243 static const struct pci_device_id vmw_pci_id_list[] = { 244 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 245 {0, 0, 0} 246 }; 247 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 248 249 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 250 static int vmw_force_iommu; 251 static int vmw_restrict_iommu; 252 static int vmw_force_coherent; 253 static int vmw_restrict_dma_mask; 254 static int vmw_assume_16bpp; 255 256 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 257 static void vmw_master_init(struct vmw_master *); 258 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 259 void *ptr); 260 261 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 262 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 263 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 264 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 265 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 266 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 267 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 268 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 269 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 270 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 271 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 272 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 273 274 275 static void vmw_print_capabilities2(uint32_t capabilities2) 276 { 277 DRM_INFO("Capabilities2:\n"); 278 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 279 DRM_INFO(" Grow oTable.\n"); 280 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 281 DRM_INFO(" IntraSurface copy.\n"); 282 } 283 284 static void vmw_print_capabilities(uint32_t capabilities) 285 { 286 DRM_INFO("Capabilities:\n"); 287 if (capabilities & SVGA_CAP_RECT_COPY) 288 DRM_INFO(" Rect copy.\n"); 289 if (capabilities & SVGA_CAP_CURSOR) 290 DRM_INFO(" Cursor.\n"); 291 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 292 DRM_INFO(" Cursor bypass.\n"); 293 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 294 DRM_INFO(" Cursor bypass 2.\n"); 295 if (capabilities & SVGA_CAP_8BIT_EMULATION) 296 DRM_INFO(" 8bit emulation.\n"); 297 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 298 DRM_INFO(" Alpha cursor.\n"); 299 if (capabilities & SVGA_CAP_3D) 300 DRM_INFO(" 3D.\n"); 301 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 302 DRM_INFO(" Extended Fifo.\n"); 303 if (capabilities & SVGA_CAP_MULTIMON) 304 DRM_INFO(" Multimon.\n"); 305 if (capabilities & SVGA_CAP_PITCHLOCK) 306 DRM_INFO(" Pitchlock.\n"); 307 if (capabilities & SVGA_CAP_IRQMASK) 308 DRM_INFO(" Irq mask.\n"); 309 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 310 DRM_INFO(" Display Topology.\n"); 311 if (capabilities & SVGA_CAP_GMR) 312 DRM_INFO(" GMR.\n"); 313 if (capabilities & SVGA_CAP_TRACES) 314 DRM_INFO(" Traces.\n"); 315 if (capabilities & SVGA_CAP_GMR2) 316 DRM_INFO(" GMR2.\n"); 317 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 318 DRM_INFO(" Screen Object 2.\n"); 319 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 320 DRM_INFO(" Command Buffers.\n"); 321 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 322 DRM_INFO(" Command Buffers 2.\n"); 323 if (capabilities & SVGA_CAP_GBOBJECTS) 324 DRM_INFO(" Guest Backed Resources.\n"); 325 if (capabilities & SVGA_CAP_DX) 326 DRM_INFO(" DX Features.\n"); 327 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 328 DRM_INFO(" HP Command Queue.\n"); 329 } 330 331 /** 332 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 333 * 334 * @dev_priv: A device private structure. 335 * 336 * This function creates a small buffer object that holds the query 337 * result for dummy queries emitted as query barriers. 338 * The function will then map the first page and initialize a pending 339 * occlusion query result structure, Finally it will unmap the buffer. 340 * No interruptible waits are done within this function. 341 * 342 * Returns an error if bo creation or initialization fails. 343 */ 344 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 345 { 346 int ret; 347 struct vmw_buffer_object *vbo; 348 struct ttm_bo_kmap_obj map; 349 volatile SVGA3dQueryResult *result; 350 bool dummy; 351 352 /* 353 * Create the vbo as pinned, so that a tryreserve will 354 * immediately succeed. This is because we're the only 355 * user of the bo currently. 356 */ 357 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 358 if (!vbo) 359 return -ENOMEM; 360 361 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 362 &vmw_sys_ne_placement, false, 363 &vmw_bo_bo_free); 364 if (unlikely(ret != 0)) 365 return ret; 366 367 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 368 BUG_ON(ret != 0); 369 vmw_bo_pin_reserved(vbo, true); 370 371 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 372 if (likely(ret == 0)) { 373 result = ttm_kmap_obj_virtual(&map, &dummy); 374 result->totalSize = sizeof(*result); 375 result->state = SVGA3D_QUERYSTATE_PENDING; 376 result->result32 = 0xff; 377 ttm_bo_kunmap(&map); 378 } 379 vmw_bo_pin_reserved(vbo, false); 380 ttm_bo_unreserve(&vbo->base); 381 382 if (unlikely(ret != 0)) { 383 DRM_ERROR("Dummy query buffer map failed.\n"); 384 vmw_bo_unreference(&vbo); 385 } else 386 dev_priv->dummy_query_bo = vbo; 387 388 return ret; 389 } 390 391 /** 392 * vmw_request_device_late - Perform late device setup 393 * 394 * @dev_priv: Pointer to device private. 395 * 396 * This function performs setup of otables and enables large command 397 * buffer submission. These tasks are split out to a separate function 398 * because it reverts vmw_release_device_early and is intended to be used 399 * by an error path in the hibernation code. 400 */ 401 static int vmw_request_device_late(struct vmw_private *dev_priv) 402 { 403 int ret; 404 405 if (dev_priv->has_mob) { 406 ret = vmw_otables_setup(dev_priv); 407 if (unlikely(ret != 0)) { 408 DRM_ERROR("Unable to initialize " 409 "guest Memory OBjects.\n"); 410 return ret; 411 } 412 } 413 414 if (dev_priv->cman) { 415 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 416 256*4096, 2*4096); 417 if (ret) { 418 struct vmw_cmdbuf_man *man = dev_priv->cman; 419 420 dev_priv->cman = NULL; 421 vmw_cmdbuf_man_destroy(man); 422 } 423 } 424 425 return 0; 426 } 427 428 static int vmw_request_device(struct vmw_private *dev_priv) 429 { 430 int ret; 431 432 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 433 if (unlikely(ret != 0)) { 434 DRM_ERROR("Unable to initialize FIFO.\n"); 435 return ret; 436 } 437 vmw_fence_fifo_up(dev_priv->fman); 438 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 439 if (IS_ERR(dev_priv->cman)) { 440 dev_priv->cman = NULL; 441 dev_priv->has_dx = false; 442 } 443 444 ret = vmw_request_device_late(dev_priv); 445 if (ret) 446 goto out_no_mob; 447 448 ret = vmw_dummy_query_bo_create(dev_priv); 449 if (unlikely(ret != 0)) 450 goto out_no_query_bo; 451 452 return 0; 453 454 out_no_query_bo: 455 if (dev_priv->cman) 456 vmw_cmdbuf_remove_pool(dev_priv->cman); 457 if (dev_priv->has_mob) { 458 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 459 vmw_otables_takedown(dev_priv); 460 } 461 if (dev_priv->cman) 462 vmw_cmdbuf_man_destroy(dev_priv->cman); 463 out_no_mob: 464 vmw_fence_fifo_down(dev_priv->fman); 465 vmw_fifo_release(dev_priv, &dev_priv->fifo); 466 return ret; 467 } 468 469 /** 470 * vmw_release_device_early - Early part of fifo takedown. 471 * 472 * @dev_priv: Pointer to device private struct. 473 * 474 * This is the first part of command submission takedown, to be called before 475 * buffer management is taken down. 476 */ 477 static void vmw_release_device_early(struct vmw_private *dev_priv) 478 { 479 /* 480 * Previous destructions should've released 481 * the pinned bo. 482 */ 483 484 BUG_ON(dev_priv->pinned_bo != NULL); 485 486 vmw_bo_unreference(&dev_priv->dummy_query_bo); 487 if (dev_priv->cman) 488 vmw_cmdbuf_remove_pool(dev_priv->cman); 489 490 if (dev_priv->has_mob) { 491 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 492 vmw_otables_takedown(dev_priv); 493 } 494 } 495 496 /** 497 * vmw_release_device_late - Late part of fifo takedown. 498 * 499 * @dev_priv: Pointer to device private struct. 500 * 501 * This is the last part of the command submission takedown, to be called when 502 * command submission is no longer needed. It may wait on pending fences. 503 */ 504 static void vmw_release_device_late(struct vmw_private *dev_priv) 505 { 506 vmw_fence_fifo_down(dev_priv->fman); 507 if (dev_priv->cman) 508 vmw_cmdbuf_man_destroy(dev_priv->cman); 509 510 vmw_fifo_release(dev_priv, &dev_priv->fifo); 511 } 512 513 /** 514 * Sets the initial_[width|height] fields on the given vmw_private. 515 * 516 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 517 * clamping the value to fb_max_[width|height] fields and the 518 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 519 * If the values appear to be invalid, set them to 520 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 521 */ 522 static void vmw_get_initial_size(struct vmw_private *dev_priv) 523 { 524 uint32_t width; 525 uint32_t height; 526 527 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 528 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 529 530 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 531 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 532 533 if (width > dev_priv->fb_max_width || 534 height > dev_priv->fb_max_height) { 535 536 /* 537 * This is a host error and shouldn't occur. 538 */ 539 540 width = VMW_MIN_INITIAL_WIDTH; 541 height = VMW_MIN_INITIAL_HEIGHT; 542 } 543 544 dev_priv->initial_width = width; 545 dev_priv->initial_height = height; 546 } 547 548 /** 549 * vmw_assume_iommu - Figure out whether coherent dma-remapping might be 550 * taking place. 551 * @dev: Pointer to the struct drm_device. 552 * 553 * Return: true if iommu present, false otherwise. 554 */ 555 static bool vmw_assume_iommu(struct drm_device *dev) 556 { 557 const struct dma_map_ops *ops = get_dma_ops(dev->dev); 558 559 return !dma_is_direct(ops) && ops && 560 ops->map_page != dma_direct_map_page; 561 } 562 563 /** 564 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 565 * system. 566 * 567 * @dev_priv: Pointer to a struct vmw_private 568 * 569 * This functions tries to determine the IOMMU setup and what actions 570 * need to be taken by the driver to make system pages visible to the 571 * device. 572 * If this function decides that DMA is not possible, it returns -EINVAL. 573 * The driver may then try to disable features of the device that require 574 * DMA. 575 */ 576 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 577 { 578 static const char *names[vmw_dma_map_max] = { 579 [vmw_dma_phys] = "Using physical TTM page addresses.", 580 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 581 [vmw_dma_map_populate] = "Keeping DMA mappings.", 582 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 583 584 if (vmw_force_coherent) 585 dev_priv->map_mode = vmw_dma_alloc_coherent; 586 else if (vmw_assume_iommu(dev_priv->dev)) 587 dev_priv->map_mode = vmw_dma_map_populate; 588 else if (!vmw_force_iommu) 589 dev_priv->map_mode = vmw_dma_phys; 590 else if (IS_ENABLED(CONFIG_SWIOTLB) && swiotlb_nr_tbl()) 591 dev_priv->map_mode = vmw_dma_alloc_coherent; 592 else 593 dev_priv->map_mode = vmw_dma_map_populate; 594 595 if (dev_priv->map_mode == vmw_dma_map_populate && vmw_restrict_iommu) 596 dev_priv->map_mode = vmw_dma_map_bind; 597 598 /* No TTM coherent page pool? FIXME: Ask TTM instead! */ 599 if (!(IS_ENABLED(CONFIG_SWIOTLB) || IS_ENABLED(CONFIG_INTEL_IOMMU)) && 600 (dev_priv->map_mode == vmw_dma_alloc_coherent)) 601 return -EINVAL; 602 603 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 604 return 0; 605 } 606 607 /** 608 * vmw_dma_masks - set required page- and dma masks 609 * 610 * @dev: Pointer to struct drm-device 611 * 612 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 613 * restriction also for 64-bit systems. 614 */ 615 static int vmw_dma_masks(struct vmw_private *dev_priv) 616 { 617 struct drm_device *dev = dev_priv->dev; 618 int ret = 0; 619 620 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 621 if (dev_priv->map_mode != vmw_dma_phys && 622 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 623 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 624 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 625 } 626 627 return ret; 628 } 629 630 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 631 { 632 struct vmw_private *dev_priv; 633 int ret; 634 uint32_t svga_id; 635 enum vmw_res_type i; 636 bool refuse_dma = false; 637 char host_log[100] = {0}; 638 639 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 640 if (unlikely(!dev_priv)) { 641 DRM_ERROR("Failed allocating a device private struct.\n"); 642 return -ENOMEM; 643 } 644 645 pci_set_master(dev->pdev); 646 647 dev_priv->dev = dev; 648 dev_priv->vmw_chipset = chipset; 649 dev_priv->last_read_seqno = (uint32_t) -100; 650 mutex_init(&dev_priv->cmdbuf_mutex); 651 mutex_init(&dev_priv->release_mutex); 652 mutex_init(&dev_priv->binding_mutex); 653 mutex_init(&dev_priv->global_kms_state_mutex); 654 ttm_lock_init(&dev_priv->reservation_sem); 655 spin_lock_init(&dev_priv->resource_lock); 656 spin_lock_init(&dev_priv->hw_lock); 657 spin_lock_init(&dev_priv->waiter_lock); 658 spin_lock_init(&dev_priv->cap_lock); 659 spin_lock_init(&dev_priv->svga_lock); 660 spin_lock_init(&dev_priv->cursor_lock); 661 662 for (i = vmw_res_context; i < vmw_res_max; ++i) { 663 idr_init(&dev_priv->res_idr[i]); 664 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 665 } 666 667 mutex_init(&dev_priv->init_mutex); 668 init_waitqueue_head(&dev_priv->fence_queue); 669 init_waitqueue_head(&dev_priv->fifo_queue); 670 dev_priv->fence_queue_waiters = 0; 671 dev_priv->fifo_queue_waiters = 0; 672 673 dev_priv->used_memory_size = 0; 674 675 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 676 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 677 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 678 679 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 680 681 dev_priv->enable_fb = enable_fbdev; 682 683 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 684 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 685 if (svga_id != SVGA_ID_2) { 686 ret = -ENOSYS; 687 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 688 goto out_err0; 689 } 690 691 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 692 693 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 694 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 695 } 696 697 698 ret = vmw_dma_select_mode(dev_priv); 699 if (unlikely(ret != 0)) { 700 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 701 refuse_dma = true; 702 } 703 704 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 705 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 706 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 707 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 708 709 vmw_get_initial_size(dev_priv); 710 711 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 712 dev_priv->max_gmr_ids = 713 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 714 dev_priv->max_gmr_pages = 715 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 716 dev_priv->memory_size = 717 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 718 dev_priv->memory_size -= dev_priv->vram_size; 719 } else { 720 /* 721 * An arbitrary limit of 512MiB on surface 722 * memory. But all HWV8 hardware supports GMR2. 723 */ 724 dev_priv->memory_size = 512*1024*1024; 725 } 726 dev_priv->max_mob_pages = 0; 727 dev_priv->max_mob_size = 0; 728 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 729 uint64_t mem_size = 730 vmw_read(dev_priv, 731 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 732 733 /* 734 * Workaround for low memory 2D VMs to compensate for the 735 * allocation taken by fbdev 736 */ 737 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 738 mem_size *= 3; 739 740 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 741 dev_priv->prim_bb_mem = 742 vmw_read(dev_priv, 743 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 744 dev_priv->max_mob_size = 745 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 746 dev_priv->stdu_max_width = 747 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 748 dev_priv->stdu_max_height = 749 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 750 751 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 752 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 753 dev_priv->texture_max_width = vmw_read(dev_priv, 754 SVGA_REG_DEV_CAP); 755 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 756 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 757 dev_priv->texture_max_height = vmw_read(dev_priv, 758 SVGA_REG_DEV_CAP); 759 } else { 760 dev_priv->texture_max_width = 8192; 761 dev_priv->texture_max_height = 8192; 762 dev_priv->prim_bb_mem = dev_priv->vram_size; 763 } 764 765 vmw_print_capabilities(dev_priv->capabilities); 766 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 767 vmw_print_capabilities2(dev_priv->capabilities2); 768 769 ret = vmw_dma_masks(dev_priv); 770 if (unlikely(ret != 0)) 771 goto out_err0; 772 773 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 774 DRM_INFO("Max GMR ids is %u\n", 775 (unsigned)dev_priv->max_gmr_ids); 776 DRM_INFO("Max number of GMR pages is %u\n", 777 (unsigned)dev_priv->max_gmr_pages); 778 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 779 (unsigned)dev_priv->memory_size / 1024); 780 } 781 DRM_INFO("Maximum display memory size is %u kiB\n", 782 dev_priv->prim_bb_mem / 1024); 783 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 784 dev_priv->vram_start, dev_priv->vram_size / 1024); 785 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 786 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 787 788 vmw_master_init(&dev_priv->fbdev_master); 789 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 790 dev_priv->active_master = &dev_priv->fbdev_master; 791 792 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 793 dev_priv->mmio_size, MEMREMAP_WB); 794 795 if (unlikely(dev_priv->mmio_virt == NULL)) { 796 ret = -ENOMEM; 797 DRM_ERROR("Failed mapping MMIO.\n"); 798 goto out_err0; 799 } 800 801 /* Need mmio memory to check for fifo pitchlock cap. */ 802 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 803 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 804 !vmw_fifo_have_pitchlock(dev_priv)) { 805 ret = -ENOSYS; 806 DRM_ERROR("Hardware has no pitchlock\n"); 807 goto out_err4; 808 } 809 810 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 811 &vmw_prime_dmabuf_ops); 812 813 if (unlikely(dev_priv->tdev == NULL)) { 814 DRM_ERROR("Unable to initialize TTM object management.\n"); 815 ret = -ENOMEM; 816 goto out_err4; 817 } 818 819 dev->dev_private = dev_priv; 820 821 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 822 dev_priv->stealth = (ret != 0); 823 if (dev_priv->stealth) { 824 /** 825 * Request at least the mmio PCI resource. 826 */ 827 828 DRM_INFO("It appears like vesafb is loaded. " 829 "Ignore above error if any.\n"); 830 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 831 if (unlikely(ret != 0)) { 832 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 833 goto out_no_device; 834 } 835 } 836 837 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 838 ret = vmw_irq_install(dev, dev->pdev->irq); 839 if (ret != 0) { 840 DRM_ERROR("Failed installing irq: %d\n", ret); 841 goto out_no_irq; 842 } 843 } 844 845 dev_priv->fman = vmw_fence_manager_init(dev_priv); 846 if (unlikely(dev_priv->fman == NULL)) { 847 ret = -ENOMEM; 848 goto out_no_fman; 849 } 850 851 ret = ttm_bo_device_init(&dev_priv->bdev, 852 &vmw_bo_driver, 853 dev->anon_inode->i_mapping, 854 VMWGFX_FILE_PAGE_OFFSET, 855 false); 856 if (unlikely(ret != 0)) { 857 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 858 goto out_no_bdev; 859 } 860 861 /* 862 * Enable VRAM, but initially don't use it until SVGA is enabled and 863 * unhidden. 864 */ 865 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 866 (dev_priv->vram_size >> PAGE_SHIFT)); 867 if (unlikely(ret != 0)) { 868 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 869 goto out_no_vram; 870 } 871 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 872 873 dev_priv->has_gmr = true; 874 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 875 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 876 VMW_PL_GMR) != 0) { 877 DRM_INFO("No GMR memory available. " 878 "Graphics memory resources are very limited.\n"); 879 dev_priv->has_gmr = false; 880 } 881 882 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 883 dev_priv->has_mob = true; 884 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 885 VMW_PL_MOB) != 0) { 886 DRM_INFO("No MOB memory available. " 887 "3D will be disabled.\n"); 888 dev_priv->has_mob = false; 889 } 890 } 891 892 if (dev_priv->has_mob) { 893 spin_lock(&dev_priv->cap_lock); 894 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 895 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 896 spin_unlock(&dev_priv->cap_lock); 897 } 898 899 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 900 ret = vmw_kms_init(dev_priv); 901 if (unlikely(ret != 0)) 902 goto out_no_kms; 903 vmw_overlay_init(dev_priv); 904 905 ret = vmw_request_device(dev_priv); 906 if (ret) 907 goto out_no_fifo; 908 909 if (dev_priv->has_dx) { 910 /* 911 * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 912 * support 913 */ 914 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) { 915 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 916 SVGA3D_DEVCAP_SM41); 917 dev_priv->has_sm4_1 = vmw_read(dev_priv, 918 SVGA_REG_DEV_CAP); 919 } 920 } 921 922 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 923 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 924 ? "yes." : "no."); 925 DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no."); 926 927 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 928 VMWGFX_REPO, VMWGFX_GIT_VERSION); 929 vmw_host_log(host_log); 930 931 memset(host_log, 0, sizeof(host_log)); 932 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 933 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 934 VMWGFX_DRIVER_PATCHLEVEL); 935 vmw_host_log(host_log); 936 937 if (dev_priv->enable_fb) { 938 vmw_fifo_resource_inc(dev_priv); 939 vmw_svga_enable(dev_priv); 940 vmw_fb_init(dev_priv); 941 } 942 943 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 944 register_pm_notifier(&dev_priv->pm_nb); 945 946 return 0; 947 948 out_no_fifo: 949 vmw_overlay_close(dev_priv); 950 vmw_kms_close(dev_priv); 951 out_no_kms: 952 if (dev_priv->has_mob) 953 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 954 if (dev_priv->has_gmr) 955 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 956 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 957 out_no_vram: 958 (void)ttm_bo_device_release(&dev_priv->bdev); 959 out_no_bdev: 960 vmw_fence_manager_takedown(dev_priv->fman); 961 out_no_fman: 962 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 963 vmw_irq_uninstall(dev_priv->dev); 964 out_no_irq: 965 if (dev_priv->stealth) 966 pci_release_region(dev->pdev, 2); 967 else 968 pci_release_regions(dev->pdev); 969 out_no_device: 970 ttm_object_device_release(&dev_priv->tdev); 971 out_err4: 972 memunmap(dev_priv->mmio_virt); 973 out_err0: 974 for (i = vmw_res_context; i < vmw_res_max; ++i) 975 idr_destroy(&dev_priv->res_idr[i]); 976 977 if (dev_priv->ctx.staged_bindings) 978 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 979 kfree(dev_priv); 980 return ret; 981 } 982 983 static void vmw_driver_unload(struct drm_device *dev) 984 { 985 struct vmw_private *dev_priv = vmw_priv(dev); 986 enum vmw_res_type i; 987 988 unregister_pm_notifier(&dev_priv->pm_nb); 989 990 if (dev_priv->ctx.res_ht_initialized) 991 drm_ht_remove(&dev_priv->ctx.res_ht); 992 vfree(dev_priv->ctx.cmd_bounce); 993 if (dev_priv->enable_fb) { 994 vmw_fb_off(dev_priv); 995 vmw_fb_close(dev_priv); 996 vmw_fifo_resource_dec(dev_priv); 997 vmw_svga_disable(dev_priv); 998 } 999 1000 vmw_kms_close(dev_priv); 1001 vmw_overlay_close(dev_priv); 1002 1003 if (dev_priv->has_gmr) 1004 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 1005 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 1006 1007 vmw_release_device_early(dev_priv); 1008 if (dev_priv->has_mob) 1009 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 1010 (void) ttm_bo_device_release(&dev_priv->bdev); 1011 vmw_release_device_late(dev_priv); 1012 vmw_fence_manager_takedown(dev_priv->fman); 1013 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1014 vmw_irq_uninstall(dev_priv->dev); 1015 if (dev_priv->stealth) 1016 pci_release_region(dev->pdev, 2); 1017 else 1018 pci_release_regions(dev->pdev); 1019 1020 ttm_object_device_release(&dev_priv->tdev); 1021 memunmap(dev_priv->mmio_virt); 1022 if (dev_priv->ctx.staged_bindings) 1023 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1024 1025 for (i = vmw_res_context; i < vmw_res_max; ++i) 1026 idr_destroy(&dev_priv->res_idr[i]); 1027 1028 kfree(dev_priv); 1029 } 1030 1031 static void vmw_postclose(struct drm_device *dev, 1032 struct drm_file *file_priv) 1033 { 1034 struct vmw_fpriv *vmw_fp; 1035 1036 vmw_fp = vmw_fpriv(file_priv); 1037 1038 if (vmw_fp->locked_master) { 1039 struct vmw_master *vmaster = 1040 vmw_master(vmw_fp->locked_master); 1041 1042 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1043 ttm_vt_unlock(&vmaster->lock); 1044 drm_master_put(&vmw_fp->locked_master); 1045 } 1046 1047 ttm_object_file_release(&vmw_fp->tfile); 1048 kfree(vmw_fp); 1049 } 1050 1051 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1052 { 1053 struct vmw_private *dev_priv = vmw_priv(dev); 1054 struct vmw_fpriv *vmw_fp; 1055 int ret = -ENOMEM; 1056 1057 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1058 if (unlikely(!vmw_fp)) 1059 return ret; 1060 1061 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1062 if (unlikely(vmw_fp->tfile == NULL)) 1063 goto out_no_tfile; 1064 1065 file_priv->driver_priv = vmw_fp; 1066 1067 return 0; 1068 1069 out_no_tfile: 1070 kfree(vmw_fp); 1071 return ret; 1072 } 1073 1074 static struct vmw_master *vmw_master_check(struct drm_device *dev, 1075 struct drm_file *file_priv, 1076 unsigned int flags) 1077 { 1078 int ret; 1079 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1080 struct vmw_master *vmaster; 1081 1082 if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH)) 1083 return NULL; 1084 1085 ret = mutex_lock_interruptible(&dev->master_mutex); 1086 if (unlikely(ret != 0)) 1087 return ERR_PTR(-ERESTARTSYS); 1088 1089 if (drm_is_current_master(file_priv)) { 1090 mutex_unlock(&dev->master_mutex); 1091 return NULL; 1092 } 1093 1094 /* 1095 * Check if we were previously master, but now dropped. In that 1096 * case, allow at least render node functionality. 1097 */ 1098 if (vmw_fp->locked_master) { 1099 mutex_unlock(&dev->master_mutex); 1100 1101 if (flags & DRM_RENDER_ALLOW) 1102 return NULL; 1103 1104 DRM_ERROR("Dropped master trying to access ioctl that " 1105 "requires authentication.\n"); 1106 return ERR_PTR(-EACCES); 1107 } 1108 mutex_unlock(&dev->master_mutex); 1109 1110 /* 1111 * Take the TTM lock. Possibly sleep waiting for the authenticating 1112 * master to become master again, or for a SIGTERM if the 1113 * authenticating master exits. 1114 */ 1115 vmaster = vmw_master(file_priv->master); 1116 ret = ttm_read_lock(&vmaster->lock, true); 1117 if (unlikely(ret != 0)) 1118 vmaster = ERR_PTR(ret); 1119 1120 return vmaster; 1121 } 1122 1123 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1124 unsigned long arg, 1125 long (*ioctl_func)(struct file *, unsigned int, 1126 unsigned long)) 1127 { 1128 struct drm_file *file_priv = filp->private_data; 1129 struct drm_device *dev = file_priv->minor->dev; 1130 unsigned int nr = DRM_IOCTL_NR(cmd); 1131 struct vmw_master *vmaster; 1132 unsigned int flags; 1133 long ret; 1134 1135 /* 1136 * Do extra checking on driver private ioctls. 1137 */ 1138 1139 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1140 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1141 const struct drm_ioctl_desc *ioctl = 1142 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1143 1144 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1145 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); 1146 if (unlikely(ret != 0)) 1147 return ret; 1148 1149 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) 1150 goto out_io_encoding; 1151 1152 return (long) vmw_execbuf_ioctl(dev, arg, file_priv, 1153 _IOC_SIZE(cmd)); 1154 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1155 if (!drm_is_current_master(file_priv) && 1156 !capable(CAP_SYS_ADMIN)) 1157 return -EACCES; 1158 } 1159 1160 if (unlikely(ioctl->cmd != cmd)) 1161 goto out_io_encoding; 1162 1163 flags = ioctl->flags; 1164 } else if (!drm_ioctl_flags(nr, &flags)) 1165 return -EINVAL; 1166 1167 vmaster = vmw_master_check(dev, file_priv, flags); 1168 if (IS_ERR(vmaster)) { 1169 ret = PTR_ERR(vmaster); 1170 1171 if (ret != -ERESTARTSYS) 1172 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", 1173 nr, ret); 1174 return ret; 1175 } 1176 1177 ret = ioctl_func(filp, cmd, arg); 1178 if (vmaster) 1179 ttm_read_unlock(&vmaster->lock); 1180 1181 return ret; 1182 1183 out_io_encoding: 1184 DRM_ERROR("Invalid command format, ioctl %d\n", 1185 nr - DRM_COMMAND_BASE); 1186 1187 return -EINVAL; 1188 } 1189 1190 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1191 unsigned long arg) 1192 { 1193 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1194 } 1195 1196 #ifdef CONFIG_COMPAT 1197 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1198 unsigned long arg) 1199 { 1200 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1201 } 1202 #endif 1203 1204 static void vmw_lastclose(struct drm_device *dev) 1205 { 1206 } 1207 1208 static void vmw_master_init(struct vmw_master *vmaster) 1209 { 1210 ttm_lock_init(&vmaster->lock); 1211 } 1212 1213 static int vmw_master_create(struct drm_device *dev, 1214 struct drm_master *master) 1215 { 1216 struct vmw_master *vmaster; 1217 1218 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); 1219 if (unlikely(!vmaster)) 1220 return -ENOMEM; 1221 1222 vmw_master_init(vmaster); 1223 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1224 master->driver_priv = vmaster; 1225 1226 return 0; 1227 } 1228 1229 static void vmw_master_destroy(struct drm_device *dev, 1230 struct drm_master *master) 1231 { 1232 struct vmw_master *vmaster = vmw_master(master); 1233 1234 master->driver_priv = NULL; 1235 kfree(vmaster); 1236 } 1237 1238 static int vmw_master_set(struct drm_device *dev, 1239 struct drm_file *file_priv, 1240 bool from_open) 1241 { 1242 struct vmw_private *dev_priv = vmw_priv(dev); 1243 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1244 struct vmw_master *active = dev_priv->active_master; 1245 struct vmw_master *vmaster = vmw_master(file_priv->master); 1246 int ret = 0; 1247 1248 if (active) { 1249 BUG_ON(active != &dev_priv->fbdev_master); 1250 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 1251 if (unlikely(ret != 0)) 1252 return ret; 1253 1254 ttm_lock_set_kill(&active->lock, true, SIGTERM); 1255 dev_priv->active_master = NULL; 1256 } 1257 1258 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1259 if (!from_open) { 1260 ttm_vt_unlock(&vmaster->lock); 1261 BUG_ON(vmw_fp->locked_master != file_priv->master); 1262 drm_master_put(&vmw_fp->locked_master); 1263 } 1264 1265 dev_priv->active_master = vmaster; 1266 drm_sysfs_hotplug_event(dev); 1267 1268 return 0; 1269 } 1270 1271 static void vmw_master_drop(struct drm_device *dev, 1272 struct drm_file *file_priv) 1273 { 1274 struct vmw_private *dev_priv = vmw_priv(dev); 1275 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1276 struct vmw_master *vmaster = vmw_master(file_priv->master); 1277 int ret; 1278 1279 /** 1280 * Make sure the master doesn't disappear while we have 1281 * it locked. 1282 */ 1283 1284 vmw_fp->locked_master = drm_master_get(file_priv->master); 1285 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 1286 vmw_kms_legacy_hotspot_clear(dev_priv); 1287 if (unlikely((ret != 0))) { 1288 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 1289 drm_master_put(&vmw_fp->locked_master); 1290 } 1291 1292 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1293 1294 if (!dev_priv->enable_fb) 1295 vmw_svga_disable(dev_priv); 1296 1297 dev_priv->active_master = &dev_priv->fbdev_master; 1298 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 1299 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 1300 } 1301 1302 /** 1303 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1304 * 1305 * @dev_priv: Pointer to device private struct. 1306 * Needs the reservation sem to be held in non-exclusive mode. 1307 */ 1308 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1309 { 1310 spin_lock(&dev_priv->svga_lock); 1311 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1312 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1313 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1314 } 1315 spin_unlock(&dev_priv->svga_lock); 1316 } 1317 1318 /** 1319 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1320 * 1321 * @dev_priv: Pointer to device private struct. 1322 */ 1323 void vmw_svga_enable(struct vmw_private *dev_priv) 1324 { 1325 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1326 __vmw_svga_enable(dev_priv); 1327 ttm_read_unlock(&dev_priv->reservation_sem); 1328 } 1329 1330 /** 1331 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1332 * 1333 * @dev_priv: Pointer to device private struct. 1334 * Needs the reservation sem to be held in exclusive mode. 1335 * Will not empty VRAM. VRAM must be emptied by caller. 1336 */ 1337 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1338 { 1339 spin_lock(&dev_priv->svga_lock); 1340 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1341 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1342 vmw_write(dev_priv, SVGA_REG_ENABLE, 1343 SVGA_REG_ENABLE_HIDE | 1344 SVGA_REG_ENABLE_ENABLE); 1345 } 1346 spin_unlock(&dev_priv->svga_lock); 1347 } 1348 1349 /** 1350 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1351 * running. 1352 * 1353 * @dev_priv: Pointer to device private struct. 1354 * Will empty VRAM. 1355 */ 1356 void vmw_svga_disable(struct vmw_private *dev_priv) 1357 { 1358 /* 1359 * Disabling SVGA will turn off device modesetting capabilities, so 1360 * notify KMS about that so that it doesn't cache atomic state that 1361 * isn't valid anymore, for example crtcs turned on. 1362 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1363 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1364 * end up with lock order reversal. Thus, a master may actually perform 1365 * a new modeset just after we call vmw_kms_lost_device() and race with 1366 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1367 * to be inconsistent with the device, causing modesetting problems. 1368 * 1369 */ 1370 vmw_kms_lost_device(dev_priv->dev); 1371 ttm_write_lock(&dev_priv->reservation_sem, false); 1372 spin_lock(&dev_priv->svga_lock); 1373 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1374 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1375 spin_unlock(&dev_priv->svga_lock); 1376 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1377 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1378 vmw_write(dev_priv, SVGA_REG_ENABLE, 1379 SVGA_REG_ENABLE_HIDE | 1380 SVGA_REG_ENABLE_ENABLE); 1381 } else 1382 spin_unlock(&dev_priv->svga_lock); 1383 ttm_write_unlock(&dev_priv->reservation_sem); 1384 } 1385 1386 static void vmw_remove(struct pci_dev *pdev) 1387 { 1388 struct drm_device *dev = pci_get_drvdata(pdev); 1389 1390 pci_disable_device(pdev); 1391 drm_put_dev(dev); 1392 } 1393 1394 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1395 void *ptr) 1396 { 1397 struct vmw_private *dev_priv = 1398 container_of(nb, struct vmw_private, pm_nb); 1399 1400 switch (val) { 1401 case PM_HIBERNATION_PREPARE: 1402 /* 1403 * Take the reservation sem in write mode, which will make sure 1404 * there are no other processes holding a buffer object 1405 * reservation, meaning we should be able to evict all buffer 1406 * objects if needed. 1407 * Once user-space processes have been frozen, we can release 1408 * the lock again. 1409 */ 1410 ttm_suspend_lock(&dev_priv->reservation_sem); 1411 dev_priv->suspend_locked = true; 1412 break; 1413 case PM_POST_HIBERNATION: 1414 case PM_POST_RESTORE: 1415 if (READ_ONCE(dev_priv->suspend_locked)) { 1416 dev_priv->suspend_locked = false; 1417 ttm_suspend_unlock(&dev_priv->reservation_sem); 1418 } 1419 break; 1420 default: 1421 break; 1422 } 1423 return 0; 1424 } 1425 1426 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1427 { 1428 struct drm_device *dev = pci_get_drvdata(pdev); 1429 struct vmw_private *dev_priv = vmw_priv(dev); 1430 1431 if (dev_priv->refuse_hibernation) 1432 return -EBUSY; 1433 1434 pci_save_state(pdev); 1435 pci_disable_device(pdev); 1436 pci_set_power_state(pdev, PCI_D3hot); 1437 return 0; 1438 } 1439 1440 static int vmw_pci_resume(struct pci_dev *pdev) 1441 { 1442 pci_set_power_state(pdev, PCI_D0); 1443 pci_restore_state(pdev); 1444 return pci_enable_device(pdev); 1445 } 1446 1447 static int vmw_pm_suspend(struct device *kdev) 1448 { 1449 struct pci_dev *pdev = to_pci_dev(kdev); 1450 struct pm_message dummy; 1451 1452 dummy.event = 0; 1453 1454 return vmw_pci_suspend(pdev, dummy); 1455 } 1456 1457 static int vmw_pm_resume(struct device *kdev) 1458 { 1459 struct pci_dev *pdev = to_pci_dev(kdev); 1460 1461 return vmw_pci_resume(pdev); 1462 } 1463 1464 static int vmw_pm_freeze(struct device *kdev) 1465 { 1466 struct pci_dev *pdev = to_pci_dev(kdev); 1467 struct drm_device *dev = pci_get_drvdata(pdev); 1468 struct vmw_private *dev_priv = vmw_priv(dev); 1469 int ret; 1470 1471 /* 1472 * Unlock for vmw_kms_suspend. 1473 * No user-space processes should be running now. 1474 */ 1475 ttm_suspend_unlock(&dev_priv->reservation_sem); 1476 ret = vmw_kms_suspend(dev_priv->dev); 1477 if (ret) { 1478 ttm_suspend_lock(&dev_priv->reservation_sem); 1479 DRM_ERROR("Failed to freeze modesetting.\n"); 1480 return ret; 1481 } 1482 if (dev_priv->enable_fb) 1483 vmw_fb_off(dev_priv); 1484 1485 ttm_suspend_lock(&dev_priv->reservation_sem); 1486 vmw_execbuf_release_pinned_bo(dev_priv); 1487 vmw_resource_evict_all(dev_priv); 1488 vmw_release_device_early(dev_priv); 1489 ttm_bo_swapout_all(&dev_priv->bdev); 1490 if (dev_priv->enable_fb) 1491 vmw_fifo_resource_dec(dev_priv); 1492 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1493 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1494 if (dev_priv->enable_fb) 1495 vmw_fifo_resource_inc(dev_priv); 1496 WARN_ON(vmw_request_device_late(dev_priv)); 1497 dev_priv->suspend_locked = false; 1498 ttm_suspend_unlock(&dev_priv->reservation_sem); 1499 if (dev_priv->suspend_state) 1500 vmw_kms_resume(dev); 1501 if (dev_priv->enable_fb) 1502 vmw_fb_on(dev_priv); 1503 return -EBUSY; 1504 } 1505 1506 vmw_fence_fifo_down(dev_priv->fman); 1507 __vmw_svga_disable(dev_priv); 1508 1509 vmw_release_device_late(dev_priv); 1510 return 0; 1511 } 1512 1513 static int vmw_pm_restore(struct device *kdev) 1514 { 1515 struct pci_dev *pdev = to_pci_dev(kdev); 1516 struct drm_device *dev = pci_get_drvdata(pdev); 1517 struct vmw_private *dev_priv = vmw_priv(dev); 1518 int ret; 1519 1520 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1521 (void) vmw_read(dev_priv, SVGA_REG_ID); 1522 1523 if (dev_priv->enable_fb) 1524 vmw_fifo_resource_inc(dev_priv); 1525 1526 ret = vmw_request_device(dev_priv); 1527 if (ret) 1528 return ret; 1529 1530 if (dev_priv->enable_fb) 1531 __vmw_svga_enable(dev_priv); 1532 1533 vmw_fence_fifo_up(dev_priv->fman); 1534 dev_priv->suspend_locked = false; 1535 ttm_suspend_unlock(&dev_priv->reservation_sem); 1536 if (dev_priv->suspend_state) 1537 vmw_kms_resume(dev_priv->dev); 1538 1539 if (dev_priv->enable_fb) 1540 vmw_fb_on(dev_priv); 1541 1542 return 0; 1543 } 1544 1545 static const struct dev_pm_ops vmw_pm_ops = { 1546 .freeze = vmw_pm_freeze, 1547 .thaw = vmw_pm_restore, 1548 .restore = vmw_pm_restore, 1549 .suspend = vmw_pm_suspend, 1550 .resume = vmw_pm_resume, 1551 }; 1552 1553 static const struct file_operations vmwgfx_driver_fops = { 1554 .owner = THIS_MODULE, 1555 .open = drm_open, 1556 .release = drm_release, 1557 .unlocked_ioctl = vmw_unlocked_ioctl, 1558 .mmap = vmw_mmap, 1559 .poll = vmw_fops_poll, 1560 .read = vmw_fops_read, 1561 #if defined(CONFIG_COMPAT) 1562 .compat_ioctl = vmw_compat_ioctl, 1563 #endif 1564 .llseek = noop_llseek, 1565 }; 1566 1567 static struct drm_driver driver = { 1568 .driver_features = 1569 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC, 1570 .load = vmw_driver_load, 1571 .unload = vmw_driver_unload, 1572 .lastclose = vmw_lastclose, 1573 .get_vblank_counter = vmw_get_vblank_counter, 1574 .enable_vblank = vmw_enable_vblank, 1575 .disable_vblank = vmw_disable_vblank, 1576 .ioctls = vmw_ioctls, 1577 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1578 .master_create = vmw_master_create, 1579 .master_destroy = vmw_master_destroy, 1580 .master_set = vmw_master_set, 1581 .master_drop = vmw_master_drop, 1582 .open = vmw_driver_open, 1583 .postclose = vmw_postclose, 1584 1585 .dumb_create = vmw_dumb_create, 1586 .dumb_map_offset = vmw_dumb_map_offset, 1587 .dumb_destroy = vmw_dumb_destroy, 1588 1589 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1590 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1591 1592 .fops = &vmwgfx_driver_fops, 1593 .name = VMWGFX_DRIVER_NAME, 1594 .desc = VMWGFX_DRIVER_DESC, 1595 .date = VMWGFX_DRIVER_DATE, 1596 .major = VMWGFX_DRIVER_MAJOR, 1597 .minor = VMWGFX_DRIVER_MINOR, 1598 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1599 }; 1600 1601 static struct pci_driver vmw_pci_driver = { 1602 .name = VMWGFX_DRIVER_NAME, 1603 .id_table = vmw_pci_id_list, 1604 .probe = vmw_probe, 1605 .remove = vmw_remove, 1606 .driver = { 1607 .pm = &vmw_pm_ops 1608 } 1609 }; 1610 1611 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1612 { 1613 return drm_get_pci_dev(pdev, ent, &driver); 1614 } 1615 1616 static int __init vmwgfx_init(void) 1617 { 1618 int ret; 1619 1620 if (vgacon_text_force()) 1621 return -EINVAL; 1622 1623 ret = pci_register_driver(&vmw_pci_driver); 1624 if (ret) 1625 DRM_ERROR("Failed initializing DRM.\n"); 1626 return ret; 1627 } 1628 1629 static void __exit vmwgfx_exit(void) 1630 { 1631 pci_unregister_driver(&vmw_pci_driver); 1632 } 1633 1634 module_init(vmwgfx_init); 1635 module_exit(vmwgfx_exit); 1636 1637 MODULE_AUTHOR("VMware Inc. and others"); 1638 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1639 MODULE_LICENSE("GPL and additional rights"); 1640 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1641 __stringify(VMWGFX_DRIVER_MINOR) "." 1642 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1643 "0"); 1644