1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 #include <linux/module.h> 28 #include <linux/console.h> 29 30 #include <drm/drmP.h> 31 #include "vmwgfx_drv.h" 32 #include "vmwgfx_binding.h" 33 #include "ttm_object.h" 34 #include <drm/ttm/ttm_placement.h> 35 #include <drm/ttm/ttm_bo_driver.h> 36 #include <drm/ttm/ttm_module.h> 37 #include <linux/dma_remapping.h> 38 39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 40 #define VMWGFX_CHIP_SVGAII 0 41 #define VMW_FB_RESERVATION 0 42 43 #define VMW_MIN_INITIAL_WIDTH 800 44 #define VMW_MIN_INITIAL_HEIGHT 600 45 46 #ifndef VMWGFX_GIT_VERSION 47 #define VMWGFX_GIT_VERSION "Unknown" 48 #endif 49 50 #define VMWGFX_REPO "In Tree" 51 52 53 /** 54 * Fully encoded drm commands. Might move to vmw_drm.h 55 */ 56 57 #define DRM_IOCTL_VMW_GET_PARAM \ 58 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 59 struct drm_vmw_getparam_arg) 60 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 61 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 62 union drm_vmw_alloc_dmabuf_arg) 63 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 65 struct drm_vmw_unref_dmabuf_arg) 66 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 67 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 68 struct drm_vmw_cursor_bypass_arg) 69 70 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 72 struct drm_vmw_control_stream_arg) 73 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 75 struct drm_vmw_stream_arg) 76 #define DRM_IOCTL_VMW_UNREF_STREAM \ 77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 78 struct drm_vmw_stream_arg) 79 80 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 81 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 82 struct drm_vmw_context_arg) 83 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 85 struct drm_vmw_context_arg) 86 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 87 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 88 union drm_vmw_surface_create_arg) 89 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 90 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 91 struct drm_vmw_surface_arg) 92 #define DRM_IOCTL_VMW_REF_SURFACE \ 93 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 94 union drm_vmw_surface_reference_arg) 95 #define DRM_IOCTL_VMW_EXECBUF \ 96 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 97 struct drm_vmw_execbuf_arg) 98 #define DRM_IOCTL_VMW_GET_3D_CAP \ 99 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 100 struct drm_vmw_get_3d_cap_arg) 101 #define DRM_IOCTL_VMW_FENCE_WAIT \ 102 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 103 struct drm_vmw_fence_wait_arg) 104 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 105 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 106 struct drm_vmw_fence_signaled_arg) 107 #define DRM_IOCTL_VMW_FENCE_UNREF \ 108 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 109 struct drm_vmw_fence_arg) 110 #define DRM_IOCTL_VMW_FENCE_EVENT \ 111 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 112 struct drm_vmw_fence_event_arg) 113 #define DRM_IOCTL_VMW_PRESENT \ 114 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 115 struct drm_vmw_present_arg) 116 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 117 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 118 struct drm_vmw_present_readback_arg) 119 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 121 struct drm_vmw_update_layout_arg) 122 #define DRM_IOCTL_VMW_CREATE_SHADER \ 123 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 124 struct drm_vmw_shader_create_arg) 125 #define DRM_IOCTL_VMW_UNREF_SHADER \ 126 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 127 struct drm_vmw_shader_arg) 128 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 129 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 130 union drm_vmw_gb_surface_create_arg) 131 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 132 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 133 union drm_vmw_gb_surface_reference_arg) 134 #define DRM_IOCTL_VMW_SYNCCPU \ 135 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 136 struct drm_vmw_synccpu_arg) 137 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 138 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 139 struct drm_vmw_context_arg) 140 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 141 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 142 union drm_vmw_gb_surface_create_ext_arg) 143 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 144 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 145 union drm_vmw_gb_surface_reference_ext_arg) 146 147 /** 148 * The core DRM version of this macro doesn't account for 149 * DRM_COMMAND_BASE. 150 */ 151 152 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 153 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 154 155 /** 156 * Ioctl definitions. 157 */ 158 159 static const struct drm_ioctl_desc vmw_ioctls[] = { 160 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 161 DRM_AUTH | DRM_RENDER_ALLOW), 162 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 163 DRM_AUTH | DRM_RENDER_ALLOW), 164 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 165 DRM_RENDER_ALLOW), 166 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 167 vmw_kms_cursor_bypass_ioctl, 168 DRM_MASTER), 169 170 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 171 DRM_MASTER), 172 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 173 DRM_MASTER), 174 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 175 DRM_MASTER), 176 177 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 178 DRM_AUTH | DRM_RENDER_ALLOW), 179 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 180 DRM_RENDER_ALLOW), 181 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 182 DRM_AUTH | DRM_RENDER_ALLOW), 183 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 184 DRM_RENDER_ALLOW), 185 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 186 DRM_AUTH | DRM_RENDER_ALLOW), 187 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | 188 DRM_RENDER_ALLOW), 189 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 190 DRM_RENDER_ALLOW), 191 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 192 vmw_fence_obj_signaled_ioctl, 193 DRM_RENDER_ALLOW), 194 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 197 DRM_AUTH | DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 199 DRM_AUTH | DRM_RENDER_ALLOW), 200 201 /* these allow direct access to the framebuffers mark as master only */ 202 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 203 DRM_MASTER | DRM_AUTH), 204 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 205 vmw_present_readback_ioctl, 206 DRM_MASTER | DRM_AUTH), 207 /* 208 * The permissions of the below ioctl are overridden in 209 * vmw_generic_ioctl(). We require either 210 * DRM_MASTER or capable(CAP_SYS_ADMIN). 211 */ 212 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 213 vmw_kms_update_layout_ioctl, 214 DRM_RENDER_ALLOW), 215 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 216 vmw_shader_define_ioctl, 217 DRM_AUTH | DRM_RENDER_ALLOW), 218 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 219 vmw_shader_destroy_ioctl, 220 DRM_RENDER_ALLOW), 221 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 222 vmw_gb_surface_define_ioctl, 223 DRM_AUTH | DRM_RENDER_ALLOW), 224 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 225 vmw_gb_surface_reference_ioctl, 226 DRM_AUTH | DRM_RENDER_ALLOW), 227 VMW_IOCTL_DEF(VMW_SYNCCPU, 228 vmw_user_bo_synccpu_ioctl, 229 DRM_RENDER_ALLOW), 230 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 231 vmw_extended_context_define_ioctl, 232 DRM_AUTH | DRM_RENDER_ALLOW), 233 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 234 vmw_gb_surface_define_ext_ioctl, 235 DRM_AUTH | DRM_RENDER_ALLOW), 236 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 237 vmw_gb_surface_reference_ext_ioctl, 238 DRM_AUTH | DRM_RENDER_ALLOW), 239 }; 240 241 static const struct pci_device_id vmw_pci_id_list[] = { 242 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 243 {0, 0, 0} 244 }; 245 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 246 247 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 248 static int vmw_force_iommu; 249 static int vmw_restrict_iommu; 250 static int vmw_force_coherent; 251 static int vmw_restrict_dma_mask; 252 static int vmw_assume_16bpp; 253 254 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 255 static void vmw_master_init(struct vmw_master *); 256 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 257 void *ptr); 258 259 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 260 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 261 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 262 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 263 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 264 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 265 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 266 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 267 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 268 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 269 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 270 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 271 272 273 static void vmw_print_capabilities2(uint32_t capabilities2) 274 { 275 DRM_INFO("Capabilities2:\n"); 276 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 277 DRM_INFO(" Grow oTable.\n"); 278 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 279 DRM_INFO(" IntraSurface copy.\n"); 280 } 281 282 static void vmw_print_capabilities(uint32_t capabilities) 283 { 284 DRM_INFO("Capabilities:\n"); 285 if (capabilities & SVGA_CAP_RECT_COPY) 286 DRM_INFO(" Rect copy.\n"); 287 if (capabilities & SVGA_CAP_CURSOR) 288 DRM_INFO(" Cursor.\n"); 289 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 290 DRM_INFO(" Cursor bypass.\n"); 291 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 292 DRM_INFO(" Cursor bypass 2.\n"); 293 if (capabilities & SVGA_CAP_8BIT_EMULATION) 294 DRM_INFO(" 8bit emulation.\n"); 295 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 296 DRM_INFO(" Alpha cursor.\n"); 297 if (capabilities & SVGA_CAP_3D) 298 DRM_INFO(" 3D.\n"); 299 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 300 DRM_INFO(" Extended Fifo.\n"); 301 if (capabilities & SVGA_CAP_MULTIMON) 302 DRM_INFO(" Multimon.\n"); 303 if (capabilities & SVGA_CAP_PITCHLOCK) 304 DRM_INFO(" Pitchlock.\n"); 305 if (capabilities & SVGA_CAP_IRQMASK) 306 DRM_INFO(" Irq mask.\n"); 307 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 308 DRM_INFO(" Display Topology.\n"); 309 if (capabilities & SVGA_CAP_GMR) 310 DRM_INFO(" GMR.\n"); 311 if (capabilities & SVGA_CAP_TRACES) 312 DRM_INFO(" Traces.\n"); 313 if (capabilities & SVGA_CAP_GMR2) 314 DRM_INFO(" GMR2.\n"); 315 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 316 DRM_INFO(" Screen Object 2.\n"); 317 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 318 DRM_INFO(" Command Buffers.\n"); 319 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 320 DRM_INFO(" Command Buffers 2.\n"); 321 if (capabilities & SVGA_CAP_GBOBJECTS) 322 DRM_INFO(" Guest Backed Resources.\n"); 323 if (capabilities & SVGA_CAP_DX) 324 DRM_INFO(" DX Features.\n"); 325 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 326 DRM_INFO(" HP Command Queue.\n"); 327 } 328 329 /** 330 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 331 * 332 * @dev_priv: A device private structure. 333 * 334 * This function creates a small buffer object that holds the query 335 * result for dummy queries emitted as query barriers. 336 * The function will then map the first page and initialize a pending 337 * occlusion query result structure, Finally it will unmap the buffer. 338 * No interruptible waits are done within this function. 339 * 340 * Returns an error if bo creation or initialization fails. 341 */ 342 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 343 { 344 int ret; 345 struct vmw_buffer_object *vbo; 346 struct ttm_bo_kmap_obj map; 347 volatile SVGA3dQueryResult *result; 348 bool dummy; 349 350 /* 351 * Create the vbo as pinned, so that a tryreserve will 352 * immediately succeed. This is because we're the only 353 * user of the bo currently. 354 */ 355 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 356 if (!vbo) 357 return -ENOMEM; 358 359 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 360 &vmw_sys_ne_placement, false, 361 &vmw_bo_bo_free); 362 if (unlikely(ret != 0)) 363 return ret; 364 365 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 366 BUG_ON(ret != 0); 367 vmw_bo_pin_reserved(vbo, true); 368 369 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 370 if (likely(ret == 0)) { 371 result = ttm_kmap_obj_virtual(&map, &dummy); 372 result->totalSize = sizeof(*result); 373 result->state = SVGA3D_QUERYSTATE_PENDING; 374 result->result32 = 0xff; 375 ttm_bo_kunmap(&map); 376 } 377 vmw_bo_pin_reserved(vbo, false); 378 ttm_bo_unreserve(&vbo->base); 379 380 if (unlikely(ret != 0)) { 381 DRM_ERROR("Dummy query buffer map failed.\n"); 382 vmw_bo_unreference(&vbo); 383 } else 384 dev_priv->dummy_query_bo = vbo; 385 386 return ret; 387 } 388 389 /** 390 * vmw_request_device_late - Perform late device setup 391 * 392 * @dev_priv: Pointer to device private. 393 * 394 * This function performs setup of otables and enables large command 395 * buffer submission. These tasks are split out to a separate function 396 * because it reverts vmw_release_device_early and is intended to be used 397 * by an error path in the hibernation code. 398 */ 399 static int vmw_request_device_late(struct vmw_private *dev_priv) 400 { 401 int ret; 402 403 if (dev_priv->has_mob) { 404 ret = vmw_otables_setup(dev_priv); 405 if (unlikely(ret != 0)) { 406 DRM_ERROR("Unable to initialize " 407 "guest Memory OBjects.\n"); 408 return ret; 409 } 410 } 411 412 if (dev_priv->cman) { 413 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 414 256*4096, 2*4096); 415 if (ret) { 416 struct vmw_cmdbuf_man *man = dev_priv->cman; 417 418 dev_priv->cman = NULL; 419 vmw_cmdbuf_man_destroy(man); 420 } 421 } 422 423 return 0; 424 } 425 426 static int vmw_request_device(struct vmw_private *dev_priv) 427 { 428 int ret; 429 430 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 431 if (unlikely(ret != 0)) { 432 DRM_ERROR("Unable to initialize FIFO.\n"); 433 return ret; 434 } 435 vmw_fence_fifo_up(dev_priv->fman); 436 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 437 if (IS_ERR(dev_priv->cman)) { 438 dev_priv->cman = NULL; 439 dev_priv->has_dx = false; 440 } 441 442 ret = vmw_request_device_late(dev_priv); 443 if (ret) 444 goto out_no_mob; 445 446 ret = vmw_dummy_query_bo_create(dev_priv); 447 if (unlikely(ret != 0)) 448 goto out_no_query_bo; 449 450 return 0; 451 452 out_no_query_bo: 453 if (dev_priv->cman) 454 vmw_cmdbuf_remove_pool(dev_priv->cman); 455 if (dev_priv->has_mob) { 456 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 457 vmw_otables_takedown(dev_priv); 458 } 459 if (dev_priv->cman) 460 vmw_cmdbuf_man_destroy(dev_priv->cman); 461 out_no_mob: 462 vmw_fence_fifo_down(dev_priv->fman); 463 vmw_fifo_release(dev_priv, &dev_priv->fifo); 464 return ret; 465 } 466 467 /** 468 * vmw_release_device_early - Early part of fifo takedown. 469 * 470 * @dev_priv: Pointer to device private struct. 471 * 472 * This is the first part of command submission takedown, to be called before 473 * buffer management is taken down. 474 */ 475 static void vmw_release_device_early(struct vmw_private *dev_priv) 476 { 477 /* 478 * Previous destructions should've released 479 * the pinned bo. 480 */ 481 482 BUG_ON(dev_priv->pinned_bo != NULL); 483 484 vmw_bo_unreference(&dev_priv->dummy_query_bo); 485 if (dev_priv->cman) 486 vmw_cmdbuf_remove_pool(dev_priv->cman); 487 488 if (dev_priv->has_mob) { 489 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 490 vmw_otables_takedown(dev_priv); 491 } 492 } 493 494 /** 495 * vmw_release_device_late - Late part of fifo takedown. 496 * 497 * @dev_priv: Pointer to device private struct. 498 * 499 * This is the last part of the command submission takedown, to be called when 500 * command submission is no longer needed. It may wait on pending fences. 501 */ 502 static void vmw_release_device_late(struct vmw_private *dev_priv) 503 { 504 vmw_fence_fifo_down(dev_priv->fman); 505 if (dev_priv->cman) 506 vmw_cmdbuf_man_destroy(dev_priv->cman); 507 508 vmw_fifo_release(dev_priv, &dev_priv->fifo); 509 } 510 511 /** 512 * Sets the initial_[width|height] fields on the given vmw_private. 513 * 514 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 515 * clamping the value to fb_max_[width|height] fields and the 516 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 517 * If the values appear to be invalid, set them to 518 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 519 */ 520 static void vmw_get_initial_size(struct vmw_private *dev_priv) 521 { 522 uint32_t width; 523 uint32_t height; 524 525 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 526 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 527 528 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 529 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 530 531 if (width > dev_priv->fb_max_width || 532 height > dev_priv->fb_max_height) { 533 534 /* 535 * This is a host error and shouldn't occur. 536 */ 537 538 width = VMW_MIN_INITIAL_WIDTH; 539 height = VMW_MIN_INITIAL_HEIGHT; 540 } 541 542 dev_priv->initial_width = width; 543 dev_priv->initial_height = height; 544 } 545 546 /** 547 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 548 * system. 549 * 550 * @dev_priv: Pointer to a struct vmw_private 551 * 552 * This functions tries to determine the IOMMU setup and what actions 553 * need to be taken by the driver to make system pages visible to the 554 * device. 555 * If this function decides that DMA is not possible, it returns -EINVAL. 556 * The driver may then try to disable features of the device that require 557 * DMA. 558 */ 559 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 560 { 561 static const char *names[vmw_dma_map_max] = { 562 [vmw_dma_phys] = "Using physical TTM page addresses.", 563 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 564 [vmw_dma_map_populate] = "Keeping DMA mappings.", 565 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 566 #ifdef CONFIG_X86 567 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); 568 569 #ifdef CONFIG_INTEL_IOMMU 570 if (intel_iommu_enabled) { 571 dev_priv->map_mode = vmw_dma_map_populate; 572 goto out_fixup; 573 } 574 #endif 575 576 if (!(vmw_force_iommu || vmw_force_coherent)) { 577 dev_priv->map_mode = vmw_dma_phys; 578 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 579 return 0; 580 } 581 582 dev_priv->map_mode = vmw_dma_map_populate; 583 584 if (dma_ops->sync_single_for_cpu) 585 dev_priv->map_mode = vmw_dma_alloc_coherent; 586 #ifdef CONFIG_SWIOTLB 587 if (swiotlb_nr_tbl() == 0) 588 dev_priv->map_mode = vmw_dma_map_populate; 589 #endif 590 591 #ifdef CONFIG_INTEL_IOMMU 592 out_fixup: 593 #endif 594 if (dev_priv->map_mode == vmw_dma_map_populate && 595 vmw_restrict_iommu) 596 dev_priv->map_mode = vmw_dma_map_bind; 597 598 if (vmw_force_coherent) 599 dev_priv->map_mode = vmw_dma_alloc_coherent; 600 601 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) 602 /* 603 * No coherent page pool 604 */ 605 if (dev_priv->map_mode == vmw_dma_alloc_coherent) 606 return -EINVAL; 607 #endif 608 609 #else /* CONFIG_X86 */ 610 dev_priv->map_mode = vmw_dma_map_populate; 611 #endif /* CONFIG_X86 */ 612 613 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 614 615 return 0; 616 } 617 618 /** 619 * vmw_dma_masks - set required page- and dma masks 620 * 621 * @dev: Pointer to struct drm-device 622 * 623 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 624 * restriction also for 64-bit systems. 625 */ 626 #ifdef CONFIG_INTEL_IOMMU 627 static int vmw_dma_masks(struct vmw_private *dev_priv) 628 { 629 struct drm_device *dev = dev_priv->dev; 630 631 if (intel_iommu_enabled && 632 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 633 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 634 return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); 635 } 636 return 0; 637 } 638 #else 639 static int vmw_dma_masks(struct vmw_private *dev_priv) 640 { 641 return 0; 642 } 643 #endif 644 645 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 646 { 647 struct vmw_private *dev_priv; 648 int ret; 649 uint32_t svga_id; 650 enum vmw_res_type i; 651 bool refuse_dma = false; 652 char host_log[100] = {0}; 653 654 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 655 if (unlikely(!dev_priv)) { 656 DRM_ERROR("Failed allocating a device private struct.\n"); 657 return -ENOMEM; 658 } 659 660 pci_set_master(dev->pdev); 661 662 dev_priv->dev = dev; 663 dev_priv->vmw_chipset = chipset; 664 dev_priv->last_read_seqno = (uint32_t) -100; 665 mutex_init(&dev_priv->cmdbuf_mutex); 666 mutex_init(&dev_priv->release_mutex); 667 mutex_init(&dev_priv->binding_mutex); 668 mutex_init(&dev_priv->requested_layout_mutex); 669 mutex_init(&dev_priv->global_kms_state_mutex); 670 ttm_lock_init(&dev_priv->reservation_sem); 671 spin_lock_init(&dev_priv->resource_lock); 672 spin_lock_init(&dev_priv->hw_lock); 673 spin_lock_init(&dev_priv->waiter_lock); 674 spin_lock_init(&dev_priv->cap_lock); 675 spin_lock_init(&dev_priv->svga_lock); 676 spin_lock_init(&dev_priv->cursor_lock); 677 678 for (i = vmw_res_context; i < vmw_res_max; ++i) { 679 idr_init(&dev_priv->res_idr[i]); 680 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 681 } 682 683 mutex_init(&dev_priv->init_mutex); 684 init_waitqueue_head(&dev_priv->fence_queue); 685 init_waitqueue_head(&dev_priv->fifo_queue); 686 dev_priv->fence_queue_waiters = 0; 687 dev_priv->fifo_queue_waiters = 0; 688 689 dev_priv->used_memory_size = 0; 690 691 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 692 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 693 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 694 695 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 696 697 dev_priv->enable_fb = enable_fbdev; 698 699 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 700 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 701 if (svga_id != SVGA_ID_2) { 702 ret = -ENOSYS; 703 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 704 goto out_err0; 705 } 706 707 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 708 709 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 710 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 711 } 712 713 714 ret = vmw_dma_select_mode(dev_priv); 715 if (unlikely(ret != 0)) { 716 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 717 refuse_dma = true; 718 } 719 720 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 721 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 722 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 723 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 724 725 vmw_get_initial_size(dev_priv); 726 727 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 728 dev_priv->max_gmr_ids = 729 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 730 dev_priv->max_gmr_pages = 731 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 732 dev_priv->memory_size = 733 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 734 dev_priv->memory_size -= dev_priv->vram_size; 735 } else { 736 /* 737 * An arbitrary limit of 512MiB on surface 738 * memory. But all HWV8 hardware supports GMR2. 739 */ 740 dev_priv->memory_size = 512*1024*1024; 741 } 742 dev_priv->max_mob_pages = 0; 743 dev_priv->max_mob_size = 0; 744 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 745 uint64_t mem_size = 746 vmw_read(dev_priv, 747 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 748 749 /* 750 * Workaround for low memory 2D VMs to compensate for the 751 * allocation taken by fbdev 752 */ 753 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 754 mem_size *= 3; 755 756 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 757 dev_priv->prim_bb_mem = 758 vmw_read(dev_priv, 759 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 760 dev_priv->max_mob_size = 761 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 762 dev_priv->stdu_max_width = 763 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 764 dev_priv->stdu_max_height = 765 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 766 767 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 768 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 769 dev_priv->texture_max_width = vmw_read(dev_priv, 770 SVGA_REG_DEV_CAP); 771 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 772 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 773 dev_priv->texture_max_height = vmw_read(dev_priv, 774 SVGA_REG_DEV_CAP); 775 } else { 776 dev_priv->texture_max_width = 8192; 777 dev_priv->texture_max_height = 8192; 778 dev_priv->prim_bb_mem = dev_priv->vram_size; 779 } 780 781 vmw_print_capabilities(dev_priv->capabilities); 782 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 783 vmw_print_capabilities2(dev_priv->capabilities2); 784 785 ret = vmw_dma_masks(dev_priv); 786 if (unlikely(ret != 0)) 787 goto out_err0; 788 789 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 790 DRM_INFO("Max GMR ids is %u\n", 791 (unsigned)dev_priv->max_gmr_ids); 792 DRM_INFO("Max number of GMR pages is %u\n", 793 (unsigned)dev_priv->max_gmr_pages); 794 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 795 (unsigned)dev_priv->memory_size / 1024); 796 } 797 DRM_INFO("Maximum display memory size is %u kiB\n", 798 dev_priv->prim_bb_mem / 1024); 799 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 800 dev_priv->vram_start, dev_priv->vram_size / 1024); 801 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 802 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 803 804 ret = vmw_ttm_global_init(dev_priv); 805 if (unlikely(ret != 0)) 806 goto out_err0; 807 808 809 vmw_master_init(&dev_priv->fbdev_master); 810 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 811 dev_priv->active_master = &dev_priv->fbdev_master; 812 813 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 814 dev_priv->mmio_size, MEMREMAP_WB); 815 816 if (unlikely(dev_priv->mmio_virt == NULL)) { 817 ret = -ENOMEM; 818 DRM_ERROR("Failed mapping MMIO.\n"); 819 goto out_err3; 820 } 821 822 /* Need mmio memory to check for fifo pitchlock cap. */ 823 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 824 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 825 !vmw_fifo_have_pitchlock(dev_priv)) { 826 ret = -ENOSYS; 827 DRM_ERROR("Hardware has no pitchlock\n"); 828 goto out_err4; 829 } 830 831 dev_priv->tdev = ttm_object_device_init 832 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); 833 834 if (unlikely(dev_priv->tdev == NULL)) { 835 DRM_ERROR("Unable to initialize TTM object management.\n"); 836 ret = -ENOMEM; 837 goto out_err4; 838 } 839 840 dev->dev_private = dev_priv; 841 842 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 843 dev_priv->stealth = (ret != 0); 844 if (dev_priv->stealth) { 845 /** 846 * Request at least the mmio PCI resource. 847 */ 848 849 DRM_INFO("It appears like vesafb is loaded. " 850 "Ignore above error if any.\n"); 851 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 852 if (unlikely(ret != 0)) { 853 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 854 goto out_no_device; 855 } 856 } 857 858 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 859 ret = vmw_irq_install(dev, dev->pdev->irq); 860 if (ret != 0) { 861 DRM_ERROR("Failed installing irq: %d\n", ret); 862 goto out_no_irq; 863 } 864 } 865 866 dev_priv->fman = vmw_fence_manager_init(dev_priv); 867 if (unlikely(dev_priv->fman == NULL)) { 868 ret = -ENOMEM; 869 goto out_no_fman; 870 } 871 872 ret = ttm_bo_device_init(&dev_priv->bdev, 873 dev_priv->bo_global_ref.ref.object, 874 &vmw_bo_driver, 875 dev->anon_inode->i_mapping, 876 VMWGFX_FILE_PAGE_OFFSET, 877 false); 878 if (unlikely(ret != 0)) { 879 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 880 goto out_no_bdev; 881 } 882 883 /* 884 * Enable VRAM, but initially don't use it until SVGA is enabled and 885 * unhidden. 886 */ 887 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 888 (dev_priv->vram_size >> PAGE_SHIFT)); 889 if (unlikely(ret != 0)) { 890 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 891 goto out_no_vram; 892 } 893 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 894 895 dev_priv->has_gmr = true; 896 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 897 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 898 VMW_PL_GMR) != 0) { 899 DRM_INFO("No GMR memory available. " 900 "Graphics memory resources are very limited.\n"); 901 dev_priv->has_gmr = false; 902 } 903 904 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 905 dev_priv->has_mob = true; 906 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 907 VMW_PL_MOB) != 0) { 908 DRM_INFO("No MOB memory available. " 909 "3D will be disabled.\n"); 910 dev_priv->has_mob = false; 911 } 912 } 913 914 if (dev_priv->has_mob) { 915 spin_lock(&dev_priv->cap_lock); 916 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 917 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 918 spin_unlock(&dev_priv->cap_lock); 919 } 920 921 922 ret = vmw_kms_init(dev_priv); 923 if (unlikely(ret != 0)) 924 goto out_no_kms; 925 vmw_overlay_init(dev_priv); 926 927 ret = vmw_request_device(dev_priv); 928 if (ret) 929 goto out_no_fifo; 930 931 if (dev_priv->has_dx) { 932 /* 933 * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 934 * support 935 */ 936 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) { 937 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 938 SVGA3D_DEVCAP_SM41); 939 dev_priv->has_sm4_1 = vmw_read(dev_priv, 940 SVGA_REG_DEV_CAP); 941 } 942 } 943 944 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 945 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 946 ? "yes." : "no."); 947 DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no."); 948 949 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 950 VMWGFX_REPO, VMWGFX_GIT_VERSION); 951 vmw_host_log(host_log); 952 953 memset(host_log, 0, sizeof(host_log)); 954 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 955 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 956 VMWGFX_DRIVER_PATCHLEVEL); 957 vmw_host_log(host_log); 958 959 if (dev_priv->enable_fb) { 960 vmw_fifo_resource_inc(dev_priv); 961 vmw_svga_enable(dev_priv); 962 vmw_fb_init(dev_priv); 963 } 964 965 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 966 register_pm_notifier(&dev_priv->pm_nb); 967 968 return 0; 969 970 out_no_fifo: 971 vmw_overlay_close(dev_priv); 972 vmw_kms_close(dev_priv); 973 out_no_kms: 974 if (dev_priv->has_mob) 975 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 976 if (dev_priv->has_gmr) 977 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 978 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 979 out_no_vram: 980 (void)ttm_bo_device_release(&dev_priv->bdev); 981 out_no_bdev: 982 vmw_fence_manager_takedown(dev_priv->fman); 983 out_no_fman: 984 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 985 vmw_irq_uninstall(dev_priv->dev); 986 out_no_irq: 987 if (dev_priv->stealth) 988 pci_release_region(dev->pdev, 2); 989 else 990 pci_release_regions(dev->pdev); 991 out_no_device: 992 ttm_object_device_release(&dev_priv->tdev); 993 out_err4: 994 memunmap(dev_priv->mmio_virt); 995 out_err3: 996 vmw_ttm_global_release(dev_priv); 997 out_err0: 998 for (i = vmw_res_context; i < vmw_res_max; ++i) 999 idr_destroy(&dev_priv->res_idr[i]); 1000 1001 if (dev_priv->ctx.staged_bindings) 1002 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1003 kfree(dev_priv); 1004 return ret; 1005 } 1006 1007 static void vmw_driver_unload(struct drm_device *dev) 1008 { 1009 struct vmw_private *dev_priv = vmw_priv(dev); 1010 enum vmw_res_type i; 1011 1012 unregister_pm_notifier(&dev_priv->pm_nb); 1013 1014 if (dev_priv->ctx.res_ht_initialized) 1015 drm_ht_remove(&dev_priv->ctx.res_ht); 1016 vfree(dev_priv->ctx.cmd_bounce); 1017 if (dev_priv->enable_fb) { 1018 vmw_fb_off(dev_priv); 1019 vmw_fb_close(dev_priv); 1020 vmw_fifo_resource_dec(dev_priv); 1021 vmw_svga_disable(dev_priv); 1022 } 1023 1024 vmw_kms_close(dev_priv); 1025 vmw_overlay_close(dev_priv); 1026 1027 if (dev_priv->has_gmr) 1028 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 1029 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 1030 1031 vmw_release_device_early(dev_priv); 1032 if (dev_priv->has_mob) 1033 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 1034 (void) ttm_bo_device_release(&dev_priv->bdev); 1035 vmw_release_device_late(dev_priv); 1036 vmw_fence_manager_takedown(dev_priv->fman); 1037 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1038 vmw_irq_uninstall(dev_priv->dev); 1039 if (dev_priv->stealth) 1040 pci_release_region(dev->pdev, 2); 1041 else 1042 pci_release_regions(dev->pdev); 1043 1044 ttm_object_device_release(&dev_priv->tdev); 1045 memunmap(dev_priv->mmio_virt); 1046 if (dev_priv->ctx.staged_bindings) 1047 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1048 vmw_ttm_global_release(dev_priv); 1049 1050 for (i = vmw_res_context; i < vmw_res_max; ++i) 1051 idr_destroy(&dev_priv->res_idr[i]); 1052 1053 kfree(dev_priv); 1054 } 1055 1056 static void vmw_postclose(struct drm_device *dev, 1057 struct drm_file *file_priv) 1058 { 1059 struct vmw_fpriv *vmw_fp; 1060 1061 vmw_fp = vmw_fpriv(file_priv); 1062 1063 if (vmw_fp->locked_master) { 1064 struct vmw_master *vmaster = 1065 vmw_master(vmw_fp->locked_master); 1066 1067 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1068 ttm_vt_unlock(&vmaster->lock); 1069 drm_master_put(&vmw_fp->locked_master); 1070 } 1071 1072 ttm_object_file_release(&vmw_fp->tfile); 1073 kfree(vmw_fp); 1074 } 1075 1076 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1077 { 1078 struct vmw_private *dev_priv = vmw_priv(dev); 1079 struct vmw_fpriv *vmw_fp; 1080 int ret = -ENOMEM; 1081 1082 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1083 if (unlikely(!vmw_fp)) 1084 return ret; 1085 1086 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1087 if (unlikely(vmw_fp->tfile == NULL)) 1088 goto out_no_tfile; 1089 1090 file_priv->driver_priv = vmw_fp; 1091 1092 return 0; 1093 1094 out_no_tfile: 1095 kfree(vmw_fp); 1096 return ret; 1097 } 1098 1099 static struct vmw_master *vmw_master_check(struct drm_device *dev, 1100 struct drm_file *file_priv, 1101 unsigned int flags) 1102 { 1103 int ret; 1104 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1105 struct vmw_master *vmaster; 1106 1107 if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH)) 1108 return NULL; 1109 1110 ret = mutex_lock_interruptible(&dev->master_mutex); 1111 if (unlikely(ret != 0)) 1112 return ERR_PTR(-ERESTARTSYS); 1113 1114 if (drm_is_current_master(file_priv)) { 1115 mutex_unlock(&dev->master_mutex); 1116 return NULL; 1117 } 1118 1119 /* 1120 * Check if we were previously master, but now dropped. In that 1121 * case, allow at least render node functionality. 1122 */ 1123 if (vmw_fp->locked_master) { 1124 mutex_unlock(&dev->master_mutex); 1125 1126 if (flags & DRM_RENDER_ALLOW) 1127 return NULL; 1128 1129 DRM_ERROR("Dropped master trying to access ioctl that " 1130 "requires authentication.\n"); 1131 return ERR_PTR(-EACCES); 1132 } 1133 mutex_unlock(&dev->master_mutex); 1134 1135 /* 1136 * Take the TTM lock. Possibly sleep waiting for the authenticating 1137 * master to become master again, or for a SIGTERM if the 1138 * authenticating master exits. 1139 */ 1140 vmaster = vmw_master(file_priv->master); 1141 ret = ttm_read_lock(&vmaster->lock, true); 1142 if (unlikely(ret != 0)) 1143 vmaster = ERR_PTR(ret); 1144 1145 return vmaster; 1146 } 1147 1148 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1149 unsigned long arg, 1150 long (*ioctl_func)(struct file *, unsigned int, 1151 unsigned long)) 1152 { 1153 struct drm_file *file_priv = filp->private_data; 1154 struct drm_device *dev = file_priv->minor->dev; 1155 unsigned int nr = DRM_IOCTL_NR(cmd); 1156 struct vmw_master *vmaster; 1157 unsigned int flags; 1158 long ret; 1159 1160 /* 1161 * Do extra checking on driver private ioctls. 1162 */ 1163 1164 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1165 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1166 const struct drm_ioctl_desc *ioctl = 1167 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1168 1169 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1170 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); 1171 if (unlikely(ret != 0)) 1172 return ret; 1173 1174 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) 1175 goto out_io_encoding; 1176 1177 return (long) vmw_execbuf_ioctl(dev, arg, file_priv, 1178 _IOC_SIZE(cmd)); 1179 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1180 if (!drm_is_current_master(file_priv) && 1181 !capable(CAP_SYS_ADMIN)) 1182 return -EACCES; 1183 } 1184 1185 if (unlikely(ioctl->cmd != cmd)) 1186 goto out_io_encoding; 1187 1188 flags = ioctl->flags; 1189 } else if (!drm_ioctl_flags(nr, &flags)) 1190 return -EINVAL; 1191 1192 vmaster = vmw_master_check(dev, file_priv, flags); 1193 if (IS_ERR(vmaster)) { 1194 ret = PTR_ERR(vmaster); 1195 1196 if (ret != -ERESTARTSYS) 1197 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", 1198 nr, ret); 1199 return ret; 1200 } 1201 1202 ret = ioctl_func(filp, cmd, arg); 1203 if (vmaster) 1204 ttm_read_unlock(&vmaster->lock); 1205 1206 return ret; 1207 1208 out_io_encoding: 1209 DRM_ERROR("Invalid command format, ioctl %d\n", 1210 nr - DRM_COMMAND_BASE); 1211 1212 return -EINVAL; 1213 } 1214 1215 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1216 unsigned long arg) 1217 { 1218 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1219 } 1220 1221 #ifdef CONFIG_COMPAT 1222 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1223 unsigned long arg) 1224 { 1225 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1226 } 1227 #endif 1228 1229 static void vmw_lastclose(struct drm_device *dev) 1230 { 1231 } 1232 1233 static void vmw_master_init(struct vmw_master *vmaster) 1234 { 1235 ttm_lock_init(&vmaster->lock); 1236 } 1237 1238 static int vmw_master_create(struct drm_device *dev, 1239 struct drm_master *master) 1240 { 1241 struct vmw_master *vmaster; 1242 1243 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); 1244 if (unlikely(!vmaster)) 1245 return -ENOMEM; 1246 1247 vmw_master_init(vmaster); 1248 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1249 master->driver_priv = vmaster; 1250 1251 return 0; 1252 } 1253 1254 static void vmw_master_destroy(struct drm_device *dev, 1255 struct drm_master *master) 1256 { 1257 struct vmw_master *vmaster = vmw_master(master); 1258 1259 master->driver_priv = NULL; 1260 kfree(vmaster); 1261 } 1262 1263 static int vmw_master_set(struct drm_device *dev, 1264 struct drm_file *file_priv, 1265 bool from_open) 1266 { 1267 struct vmw_private *dev_priv = vmw_priv(dev); 1268 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1269 struct vmw_master *active = dev_priv->active_master; 1270 struct vmw_master *vmaster = vmw_master(file_priv->master); 1271 int ret = 0; 1272 1273 if (active) { 1274 BUG_ON(active != &dev_priv->fbdev_master); 1275 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 1276 if (unlikely(ret != 0)) 1277 return ret; 1278 1279 ttm_lock_set_kill(&active->lock, true, SIGTERM); 1280 dev_priv->active_master = NULL; 1281 } 1282 1283 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1284 if (!from_open) { 1285 ttm_vt_unlock(&vmaster->lock); 1286 BUG_ON(vmw_fp->locked_master != file_priv->master); 1287 drm_master_put(&vmw_fp->locked_master); 1288 } 1289 1290 dev_priv->active_master = vmaster; 1291 drm_sysfs_hotplug_event(dev); 1292 1293 return 0; 1294 } 1295 1296 static void vmw_master_drop(struct drm_device *dev, 1297 struct drm_file *file_priv) 1298 { 1299 struct vmw_private *dev_priv = vmw_priv(dev); 1300 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1301 struct vmw_master *vmaster = vmw_master(file_priv->master); 1302 int ret; 1303 1304 /** 1305 * Make sure the master doesn't disappear while we have 1306 * it locked. 1307 */ 1308 1309 vmw_fp->locked_master = drm_master_get(file_priv->master); 1310 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 1311 vmw_kms_legacy_hotspot_clear(dev_priv); 1312 if (unlikely((ret != 0))) { 1313 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 1314 drm_master_put(&vmw_fp->locked_master); 1315 } 1316 1317 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1318 1319 if (!dev_priv->enable_fb) 1320 vmw_svga_disable(dev_priv); 1321 1322 dev_priv->active_master = &dev_priv->fbdev_master; 1323 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 1324 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 1325 } 1326 1327 /** 1328 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1329 * 1330 * @dev_priv: Pointer to device private struct. 1331 * Needs the reservation sem to be held in non-exclusive mode. 1332 */ 1333 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1334 { 1335 spin_lock(&dev_priv->svga_lock); 1336 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1337 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1338 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1339 } 1340 spin_unlock(&dev_priv->svga_lock); 1341 } 1342 1343 /** 1344 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1345 * 1346 * @dev_priv: Pointer to device private struct. 1347 */ 1348 void vmw_svga_enable(struct vmw_private *dev_priv) 1349 { 1350 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1351 __vmw_svga_enable(dev_priv); 1352 ttm_read_unlock(&dev_priv->reservation_sem); 1353 } 1354 1355 /** 1356 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1357 * 1358 * @dev_priv: Pointer to device private struct. 1359 * Needs the reservation sem to be held in exclusive mode. 1360 * Will not empty VRAM. VRAM must be emptied by caller. 1361 */ 1362 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1363 { 1364 spin_lock(&dev_priv->svga_lock); 1365 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1366 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1367 vmw_write(dev_priv, SVGA_REG_ENABLE, 1368 SVGA_REG_ENABLE_HIDE | 1369 SVGA_REG_ENABLE_ENABLE); 1370 } 1371 spin_unlock(&dev_priv->svga_lock); 1372 } 1373 1374 /** 1375 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1376 * running. 1377 * 1378 * @dev_priv: Pointer to device private struct. 1379 * Will empty VRAM. 1380 */ 1381 void vmw_svga_disable(struct vmw_private *dev_priv) 1382 { 1383 /* 1384 * Disabling SVGA will turn off device modesetting capabilities, so 1385 * notify KMS about that so that it doesn't cache atomic state that 1386 * isn't valid anymore, for example crtcs turned on. 1387 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1388 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1389 * end up with lock order reversal. Thus, a master may actually perform 1390 * a new modeset just after we call vmw_kms_lost_device() and race with 1391 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1392 * to be inconsistent with the device, causing modesetting problems. 1393 * 1394 */ 1395 vmw_kms_lost_device(dev_priv->dev); 1396 ttm_write_lock(&dev_priv->reservation_sem, false); 1397 spin_lock(&dev_priv->svga_lock); 1398 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1399 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1400 spin_unlock(&dev_priv->svga_lock); 1401 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1402 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1403 vmw_write(dev_priv, SVGA_REG_ENABLE, 1404 SVGA_REG_ENABLE_HIDE | 1405 SVGA_REG_ENABLE_ENABLE); 1406 } else 1407 spin_unlock(&dev_priv->svga_lock); 1408 ttm_write_unlock(&dev_priv->reservation_sem); 1409 } 1410 1411 static void vmw_remove(struct pci_dev *pdev) 1412 { 1413 struct drm_device *dev = pci_get_drvdata(pdev); 1414 1415 pci_disable_device(pdev); 1416 drm_put_dev(dev); 1417 } 1418 1419 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1420 void *ptr) 1421 { 1422 struct vmw_private *dev_priv = 1423 container_of(nb, struct vmw_private, pm_nb); 1424 1425 switch (val) { 1426 case PM_HIBERNATION_PREPARE: 1427 /* 1428 * Take the reservation sem in write mode, which will make sure 1429 * there are no other processes holding a buffer object 1430 * reservation, meaning we should be able to evict all buffer 1431 * objects if needed. 1432 * Once user-space processes have been frozen, we can release 1433 * the lock again. 1434 */ 1435 ttm_suspend_lock(&dev_priv->reservation_sem); 1436 dev_priv->suspend_locked = true; 1437 break; 1438 case PM_POST_HIBERNATION: 1439 case PM_POST_RESTORE: 1440 if (READ_ONCE(dev_priv->suspend_locked)) { 1441 dev_priv->suspend_locked = false; 1442 ttm_suspend_unlock(&dev_priv->reservation_sem); 1443 } 1444 break; 1445 default: 1446 break; 1447 } 1448 return 0; 1449 } 1450 1451 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1452 { 1453 struct drm_device *dev = pci_get_drvdata(pdev); 1454 struct vmw_private *dev_priv = vmw_priv(dev); 1455 1456 if (dev_priv->refuse_hibernation) 1457 return -EBUSY; 1458 1459 pci_save_state(pdev); 1460 pci_disable_device(pdev); 1461 pci_set_power_state(pdev, PCI_D3hot); 1462 return 0; 1463 } 1464 1465 static int vmw_pci_resume(struct pci_dev *pdev) 1466 { 1467 pci_set_power_state(pdev, PCI_D0); 1468 pci_restore_state(pdev); 1469 return pci_enable_device(pdev); 1470 } 1471 1472 static int vmw_pm_suspend(struct device *kdev) 1473 { 1474 struct pci_dev *pdev = to_pci_dev(kdev); 1475 struct pm_message dummy; 1476 1477 dummy.event = 0; 1478 1479 return vmw_pci_suspend(pdev, dummy); 1480 } 1481 1482 static int vmw_pm_resume(struct device *kdev) 1483 { 1484 struct pci_dev *pdev = to_pci_dev(kdev); 1485 1486 return vmw_pci_resume(pdev); 1487 } 1488 1489 static int vmw_pm_freeze(struct device *kdev) 1490 { 1491 struct pci_dev *pdev = to_pci_dev(kdev); 1492 struct drm_device *dev = pci_get_drvdata(pdev); 1493 struct vmw_private *dev_priv = vmw_priv(dev); 1494 int ret; 1495 1496 /* 1497 * Unlock for vmw_kms_suspend. 1498 * No user-space processes should be running now. 1499 */ 1500 ttm_suspend_unlock(&dev_priv->reservation_sem); 1501 ret = vmw_kms_suspend(dev_priv->dev); 1502 if (ret) { 1503 ttm_suspend_lock(&dev_priv->reservation_sem); 1504 DRM_ERROR("Failed to freeze modesetting.\n"); 1505 return ret; 1506 } 1507 if (dev_priv->enable_fb) 1508 vmw_fb_off(dev_priv); 1509 1510 ttm_suspend_lock(&dev_priv->reservation_sem); 1511 vmw_execbuf_release_pinned_bo(dev_priv); 1512 vmw_resource_evict_all(dev_priv); 1513 vmw_release_device_early(dev_priv); 1514 ttm_bo_swapout_all(&dev_priv->bdev); 1515 if (dev_priv->enable_fb) 1516 vmw_fifo_resource_dec(dev_priv); 1517 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1518 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1519 if (dev_priv->enable_fb) 1520 vmw_fifo_resource_inc(dev_priv); 1521 WARN_ON(vmw_request_device_late(dev_priv)); 1522 dev_priv->suspend_locked = false; 1523 ttm_suspend_unlock(&dev_priv->reservation_sem); 1524 if (dev_priv->suspend_state) 1525 vmw_kms_resume(dev); 1526 if (dev_priv->enable_fb) 1527 vmw_fb_on(dev_priv); 1528 return -EBUSY; 1529 } 1530 1531 vmw_fence_fifo_down(dev_priv->fman); 1532 __vmw_svga_disable(dev_priv); 1533 1534 vmw_release_device_late(dev_priv); 1535 return 0; 1536 } 1537 1538 static int vmw_pm_restore(struct device *kdev) 1539 { 1540 struct pci_dev *pdev = to_pci_dev(kdev); 1541 struct drm_device *dev = pci_get_drvdata(pdev); 1542 struct vmw_private *dev_priv = vmw_priv(dev); 1543 int ret; 1544 1545 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1546 (void) vmw_read(dev_priv, SVGA_REG_ID); 1547 1548 if (dev_priv->enable_fb) 1549 vmw_fifo_resource_inc(dev_priv); 1550 1551 ret = vmw_request_device(dev_priv); 1552 if (ret) 1553 return ret; 1554 1555 if (dev_priv->enable_fb) 1556 __vmw_svga_enable(dev_priv); 1557 1558 vmw_fence_fifo_up(dev_priv->fman); 1559 dev_priv->suspend_locked = false; 1560 ttm_suspend_unlock(&dev_priv->reservation_sem); 1561 if (dev_priv->suspend_state) 1562 vmw_kms_resume(dev_priv->dev); 1563 1564 if (dev_priv->enable_fb) 1565 vmw_fb_on(dev_priv); 1566 1567 return 0; 1568 } 1569 1570 static const struct dev_pm_ops vmw_pm_ops = { 1571 .freeze = vmw_pm_freeze, 1572 .thaw = vmw_pm_restore, 1573 .restore = vmw_pm_restore, 1574 .suspend = vmw_pm_suspend, 1575 .resume = vmw_pm_resume, 1576 }; 1577 1578 static const struct file_operations vmwgfx_driver_fops = { 1579 .owner = THIS_MODULE, 1580 .open = drm_open, 1581 .release = drm_release, 1582 .unlocked_ioctl = vmw_unlocked_ioctl, 1583 .mmap = vmw_mmap, 1584 .poll = vmw_fops_poll, 1585 .read = vmw_fops_read, 1586 #if defined(CONFIG_COMPAT) 1587 .compat_ioctl = vmw_compat_ioctl, 1588 #endif 1589 .llseek = noop_llseek, 1590 }; 1591 1592 static struct drm_driver driver = { 1593 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | 1594 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC, 1595 .load = vmw_driver_load, 1596 .unload = vmw_driver_unload, 1597 .lastclose = vmw_lastclose, 1598 .get_vblank_counter = vmw_get_vblank_counter, 1599 .enable_vblank = vmw_enable_vblank, 1600 .disable_vblank = vmw_disable_vblank, 1601 .ioctls = vmw_ioctls, 1602 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1603 .master_create = vmw_master_create, 1604 .master_destroy = vmw_master_destroy, 1605 .master_set = vmw_master_set, 1606 .master_drop = vmw_master_drop, 1607 .open = vmw_driver_open, 1608 .postclose = vmw_postclose, 1609 1610 .dumb_create = vmw_dumb_create, 1611 .dumb_map_offset = vmw_dumb_map_offset, 1612 .dumb_destroy = vmw_dumb_destroy, 1613 1614 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1615 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1616 1617 .fops = &vmwgfx_driver_fops, 1618 .name = VMWGFX_DRIVER_NAME, 1619 .desc = VMWGFX_DRIVER_DESC, 1620 .date = VMWGFX_DRIVER_DATE, 1621 .major = VMWGFX_DRIVER_MAJOR, 1622 .minor = VMWGFX_DRIVER_MINOR, 1623 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1624 }; 1625 1626 static struct pci_driver vmw_pci_driver = { 1627 .name = VMWGFX_DRIVER_NAME, 1628 .id_table = vmw_pci_id_list, 1629 .probe = vmw_probe, 1630 .remove = vmw_remove, 1631 .driver = { 1632 .pm = &vmw_pm_ops 1633 } 1634 }; 1635 1636 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1637 { 1638 return drm_get_pci_dev(pdev, ent, &driver); 1639 } 1640 1641 static int __init vmwgfx_init(void) 1642 { 1643 int ret; 1644 1645 if (vgacon_text_force()) 1646 return -EINVAL; 1647 1648 ret = pci_register_driver(&vmw_pci_driver); 1649 if (ret) 1650 DRM_ERROR("Failed initializing DRM.\n"); 1651 return ret; 1652 } 1653 1654 static void __exit vmwgfx_exit(void) 1655 { 1656 pci_unregister_driver(&vmw_pci_driver); 1657 } 1658 1659 module_init(vmwgfx_init); 1660 module_exit(vmwgfx_exit); 1661 1662 MODULE_AUTHOR("VMware Inc. and others"); 1663 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1664 MODULE_LICENSE("GPL and additional rights"); 1665 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1666 __stringify(VMWGFX_DRIVER_MINOR) "." 1667 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1668 "0"); 1669