1 /************************************************************************** 2 * 3 * Copyright © 2009-2015 VMware, Inc., Palo Alto, CA., USA 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 #include <linux/module.h> 28 29 #include <drm/drmP.h> 30 #include "vmwgfx_drv.h" 31 #include "vmwgfx_binding.h" 32 #include <drm/ttm/ttm_placement.h> 33 #include <drm/ttm/ttm_bo_driver.h> 34 #include <drm/ttm/ttm_object.h> 35 #include <drm/ttm/ttm_module.h> 36 #include <linux/dma_remapping.h> 37 38 #define VMWGFX_DRIVER_NAME "vmwgfx" 39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 40 #define VMWGFX_CHIP_SVGAII 0 41 #define VMW_FB_RESERVATION 0 42 43 #define VMW_MIN_INITIAL_WIDTH 800 44 #define VMW_MIN_INITIAL_HEIGHT 600 45 46 47 /** 48 * Fully encoded drm commands. Might move to vmw_drm.h 49 */ 50 51 #define DRM_IOCTL_VMW_GET_PARAM \ 52 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 53 struct drm_vmw_getparam_arg) 54 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 55 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 56 union drm_vmw_alloc_dmabuf_arg) 57 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 58 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 59 struct drm_vmw_unref_dmabuf_arg) 60 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 61 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 62 struct drm_vmw_cursor_bypass_arg) 63 64 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 65 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 66 struct drm_vmw_control_stream_arg) 67 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 68 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 69 struct drm_vmw_stream_arg) 70 #define DRM_IOCTL_VMW_UNREF_STREAM \ 71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 72 struct drm_vmw_stream_arg) 73 74 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 75 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 76 struct drm_vmw_context_arg) 77 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 79 struct drm_vmw_context_arg) 80 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 81 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 82 union drm_vmw_surface_create_arg) 83 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 85 struct drm_vmw_surface_arg) 86 #define DRM_IOCTL_VMW_REF_SURFACE \ 87 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 88 union drm_vmw_surface_reference_arg) 89 #define DRM_IOCTL_VMW_EXECBUF \ 90 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 91 struct drm_vmw_execbuf_arg) 92 #define DRM_IOCTL_VMW_GET_3D_CAP \ 93 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 94 struct drm_vmw_get_3d_cap_arg) 95 #define DRM_IOCTL_VMW_FENCE_WAIT \ 96 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 97 struct drm_vmw_fence_wait_arg) 98 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 99 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 100 struct drm_vmw_fence_signaled_arg) 101 #define DRM_IOCTL_VMW_FENCE_UNREF \ 102 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 103 struct drm_vmw_fence_arg) 104 #define DRM_IOCTL_VMW_FENCE_EVENT \ 105 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 106 struct drm_vmw_fence_event_arg) 107 #define DRM_IOCTL_VMW_PRESENT \ 108 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 109 struct drm_vmw_present_arg) 110 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 111 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 112 struct drm_vmw_present_readback_arg) 113 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 114 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 115 struct drm_vmw_update_layout_arg) 116 #define DRM_IOCTL_VMW_CREATE_SHADER \ 117 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 118 struct drm_vmw_shader_create_arg) 119 #define DRM_IOCTL_VMW_UNREF_SHADER \ 120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 121 struct drm_vmw_shader_arg) 122 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 123 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 124 union drm_vmw_gb_surface_create_arg) 125 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 126 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 127 union drm_vmw_gb_surface_reference_arg) 128 #define DRM_IOCTL_VMW_SYNCCPU \ 129 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 130 struct drm_vmw_synccpu_arg) 131 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 132 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 133 struct drm_vmw_context_arg) 134 135 /** 136 * The core DRM version of this macro doesn't account for 137 * DRM_COMMAND_BASE. 138 */ 139 140 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 141 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 142 143 /** 144 * Ioctl definitions. 145 */ 146 147 static const struct drm_ioctl_desc vmw_ioctls[] = { 148 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 149 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 150 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, 151 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 152 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, 153 DRM_UNLOCKED | DRM_RENDER_ALLOW), 154 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 155 vmw_kms_cursor_bypass_ioctl, 156 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 157 158 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 159 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 160 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 161 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 162 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 163 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 164 165 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 166 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 167 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 168 DRM_UNLOCKED | DRM_RENDER_ALLOW), 169 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 170 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 171 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 172 DRM_UNLOCKED | DRM_RENDER_ALLOW), 173 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 174 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 175 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | DRM_UNLOCKED | 176 DRM_RENDER_ALLOW), 177 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 178 DRM_UNLOCKED | DRM_RENDER_ALLOW), 179 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 180 vmw_fence_obj_signaled_ioctl, 181 DRM_UNLOCKED | DRM_RENDER_ALLOW), 182 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 183 DRM_UNLOCKED | DRM_RENDER_ALLOW), 184 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 185 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 186 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 187 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 188 189 /* these allow direct access to the framebuffers mark as master only */ 190 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 191 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), 192 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 193 vmw_present_readback_ioctl, 194 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), 195 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 196 vmw_kms_update_layout_ioctl, 197 DRM_MASTER | DRM_UNLOCKED), 198 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 199 vmw_shader_define_ioctl, 200 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 201 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 202 vmw_shader_destroy_ioctl, 203 DRM_UNLOCKED | DRM_RENDER_ALLOW), 204 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 205 vmw_gb_surface_define_ioctl, 206 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 207 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 208 vmw_gb_surface_reference_ioctl, 209 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 210 VMW_IOCTL_DEF(VMW_SYNCCPU, 211 vmw_user_dmabuf_synccpu_ioctl, 212 DRM_UNLOCKED | DRM_RENDER_ALLOW), 213 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 214 vmw_extended_context_define_ioctl, 215 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 216 }; 217 218 static struct pci_device_id vmw_pci_id_list[] = { 219 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 220 {0, 0, 0} 221 }; 222 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 223 224 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 225 static int vmw_force_iommu; 226 static int vmw_restrict_iommu; 227 static int vmw_force_coherent; 228 static int vmw_restrict_dma_mask; 229 230 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 231 static void vmw_master_init(struct vmw_master *); 232 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 233 void *ptr); 234 235 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 236 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 237 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 238 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 239 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 240 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 241 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 242 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 243 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 244 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 245 246 247 static void vmw_print_capabilities(uint32_t capabilities) 248 { 249 DRM_INFO("Capabilities:\n"); 250 if (capabilities & SVGA_CAP_RECT_COPY) 251 DRM_INFO(" Rect copy.\n"); 252 if (capabilities & SVGA_CAP_CURSOR) 253 DRM_INFO(" Cursor.\n"); 254 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 255 DRM_INFO(" Cursor bypass.\n"); 256 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 257 DRM_INFO(" Cursor bypass 2.\n"); 258 if (capabilities & SVGA_CAP_8BIT_EMULATION) 259 DRM_INFO(" 8bit emulation.\n"); 260 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 261 DRM_INFO(" Alpha cursor.\n"); 262 if (capabilities & SVGA_CAP_3D) 263 DRM_INFO(" 3D.\n"); 264 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 265 DRM_INFO(" Extended Fifo.\n"); 266 if (capabilities & SVGA_CAP_MULTIMON) 267 DRM_INFO(" Multimon.\n"); 268 if (capabilities & SVGA_CAP_PITCHLOCK) 269 DRM_INFO(" Pitchlock.\n"); 270 if (capabilities & SVGA_CAP_IRQMASK) 271 DRM_INFO(" Irq mask.\n"); 272 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 273 DRM_INFO(" Display Topology.\n"); 274 if (capabilities & SVGA_CAP_GMR) 275 DRM_INFO(" GMR.\n"); 276 if (capabilities & SVGA_CAP_TRACES) 277 DRM_INFO(" Traces.\n"); 278 if (capabilities & SVGA_CAP_GMR2) 279 DRM_INFO(" GMR2.\n"); 280 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 281 DRM_INFO(" Screen Object 2.\n"); 282 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 283 DRM_INFO(" Command Buffers.\n"); 284 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 285 DRM_INFO(" Command Buffers 2.\n"); 286 if (capabilities & SVGA_CAP_GBOBJECTS) 287 DRM_INFO(" Guest Backed Resources.\n"); 288 if (capabilities & SVGA_CAP_DX) 289 DRM_INFO(" DX Features.\n"); 290 } 291 292 /** 293 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 294 * 295 * @dev_priv: A device private structure. 296 * 297 * This function creates a small buffer object that holds the query 298 * result for dummy queries emitted as query barriers. 299 * The function will then map the first page and initialize a pending 300 * occlusion query result structure, Finally it will unmap the buffer. 301 * No interruptible waits are done within this function. 302 * 303 * Returns an error if bo creation or initialization fails. 304 */ 305 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 306 { 307 int ret; 308 struct vmw_dma_buffer *vbo; 309 struct ttm_bo_kmap_obj map; 310 volatile SVGA3dQueryResult *result; 311 bool dummy; 312 313 /* 314 * Create the vbo as pinned, so that a tryreserve will 315 * immediately succeed. This is because we're the only 316 * user of the bo currently. 317 */ 318 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 319 if (!vbo) 320 return -ENOMEM; 321 322 ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE, 323 &vmw_sys_ne_placement, false, 324 &vmw_dmabuf_bo_free); 325 if (unlikely(ret != 0)) 326 return ret; 327 328 ret = ttm_bo_reserve(&vbo->base, false, true, false, NULL); 329 BUG_ON(ret != 0); 330 vmw_bo_pin_reserved(vbo, true); 331 332 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 333 if (likely(ret == 0)) { 334 result = ttm_kmap_obj_virtual(&map, &dummy); 335 result->totalSize = sizeof(*result); 336 result->state = SVGA3D_QUERYSTATE_PENDING; 337 result->result32 = 0xff; 338 ttm_bo_kunmap(&map); 339 } 340 vmw_bo_pin_reserved(vbo, false); 341 ttm_bo_unreserve(&vbo->base); 342 343 if (unlikely(ret != 0)) { 344 DRM_ERROR("Dummy query buffer map failed.\n"); 345 vmw_dmabuf_unreference(&vbo); 346 } else 347 dev_priv->dummy_query_bo = vbo; 348 349 return ret; 350 } 351 352 /** 353 * vmw_request_device_late - Perform late device setup 354 * 355 * @dev_priv: Pointer to device private. 356 * 357 * This function performs setup of otables and enables large command 358 * buffer submission. These tasks are split out to a separate function 359 * because it reverts vmw_release_device_early and is intended to be used 360 * by an error path in the hibernation code. 361 */ 362 static int vmw_request_device_late(struct vmw_private *dev_priv) 363 { 364 int ret; 365 366 if (dev_priv->has_mob) { 367 ret = vmw_otables_setup(dev_priv); 368 if (unlikely(ret != 0)) { 369 DRM_ERROR("Unable to initialize " 370 "guest Memory OBjects.\n"); 371 return ret; 372 } 373 } 374 375 if (dev_priv->cman) { 376 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 377 256*4096, 2*4096); 378 if (ret) { 379 struct vmw_cmdbuf_man *man = dev_priv->cman; 380 381 dev_priv->cman = NULL; 382 vmw_cmdbuf_man_destroy(man); 383 } 384 } 385 386 return 0; 387 } 388 389 static int vmw_request_device(struct vmw_private *dev_priv) 390 { 391 int ret; 392 393 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 394 if (unlikely(ret != 0)) { 395 DRM_ERROR("Unable to initialize FIFO.\n"); 396 return ret; 397 } 398 vmw_fence_fifo_up(dev_priv->fman); 399 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 400 if (IS_ERR(dev_priv->cman)) { 401 dev_priv->cman = NULL; 402 dev_priv->has_dx = false; 403 } 404 405 ret = vmw_request_device_late(dev_priv); 406 if (ret) 407 goto out_no_mob; 408 409 ret = vmw_dummy_query_bo_create(dev_priv); 410 if (unlikely(ret != 0)) 411 goto out_no_query_bo; 412 413 return 0; 414 415 out_no_query_bo: 416 if (dev_priv->cman) 417 vmw_cmdbuf_remove_pool(dev_priv->cman); 418 if (dev_priv->has_mob) { 419 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 420 vmw_otables_takedown(dev_priv); 421 } 422 if (dev_priv->cman) 423 vmw_cmdbuf_man_destroy(dev_priv->cman); 424 out_no_mob: 425 vmw_fence_fifo_down(dev_priv->fman); 426 vmw_fifo_release(dev_priv, &dev_priv->fifo); 427 return ret; 428 } 429 430 /** 431 * vmw_release_device_early - Early part of fifo takedown. 432 * 433 * @dev_priv: Pointer to device private struct. 434 * 435 * This is the first part of command submission takedown, to be called before 436 * buffer management is taken down. 437 */ 438 static void vmw_release_device_early(struct vmw_private *dev_priv) 439 { 440 /* 441 * Previous destructions should've released 442 * the pinned bo. 443 */ 444 445 BUG_ON(dev_priv->pinned_bo != NULL); 446 447 vmw_dmabuf_unreference(&dev_priv->dummy_query_bo); 448 if (dev_priv->cman) 449 vmw_cmdbuf_remove_pool(dev_priv->cman); 450 451 if (dev_priv->has_mob) { 452 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 453 vmw_otables_takedown(dev_priv); 454 } 455 } 456 457 /** 458 * vmw_release_device_late - Late part of fifo takedown. 459 * 460 * @dev_priv: Pointer to device private struct. 461 * 462 * This is the last part of the command submission takedown, to be called when 463 * command submission is no longer needed. It may wait on pending fences. 464 */ 465 static void vmw_release_device_late(struct vmw_private *dev_priv) 466 { 467 vmw_fence_fifo_down(dev_priv->fman); 468 if (dev_priv->cman) 469 vmw_cmdbuf_man_destroy(dev_priv->cman); 470 471 vmw_fifo_release(dev_priv, &dev_priv->fifo); 472 } 473 474 /** 475 * Sets the initial_[width|height] fields on the given vmw_private. 476 * 477 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 478 * clamping the value to fb_max_[width|height] fields and the 479 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 480 * If the values appear to be invalid, set them to 481 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 482 */ 483 static void vmw_get_initial_size(struct vmw_private *dev_priv) 484 { 485 uint32_t width; 486 uint32_t height; 487 488 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 489 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 490 491 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 492 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 493 494 if (width > dev_priv->fb_max_width || 495 height > dev_priv->fb_max_height) { 496 497 /* 498 * This is a host error and shouldn't occur. 499 */ 500 501 width = VMW_MIN_INITIAL_WIDTH; 502 height = VMW_MIN_INITIAL_HEIGHT; 503 } 504 505 dev_priv->initial_width = width; 506 dev_priv->initial_height = height; 507 } 508 509 /** 510 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 511 * system. 512 * 513 * @dev_priv: Pointer to a struct vmw_private 514 * 515 * This functions tries to determine the IOMMU setup and what actions 516 * need to be taken by the driver to make system pages visible to the 517 * device. 518 * If this function decides that DMA is not possible, it returns -EINVAL. 519 * The driver may then try to disable features of the device that require 520 * DMA. 521 */ 522 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 523 { 524 static const char *names[vmw_dma_map_max] = { 525 [vmw_dma_phys] = "Using physical TTM page addresses.", 526 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 527 [vmw_dma_map_populate] = "Keeping DMA mappings.", 528 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 529 #ifdef CONFIG_X86 530 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); 531 532 #ifdef CONFIG_INTEL_IOMMU 533 if (intel_iommu_enabled) { 534 dev_priv->map_mode = vmw_dma_map_populate; 535 goto out_fixup; 536 } 537 #endif 538 539 if (!(vmw_force_iommu || vmw_force_coherent)) { 540 dev_priv->map_mode = vmw_dma_phys; 541 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 542 return 0; 543 } 544 545 dev_priv->map_mode = vmw_dma_map_populate; 546 547 if (dma_ops->sync_single_for_cpu) 548 dev_priv->map_mode = vmw_dma_alloc_coherent; 549 #ifdef CONFIG_SWIOTLB 550 if (swiotlb_nr_tbl() == 0) 551 dev_priv->map_mode = vmw_dma_map_populate; 552 #endif 553 554 #ifdef CONFIG_INTEL_IOMMU 555 out_fixup: 556 #endif 557 if (dev_priv->map_mode == vmw_dma_map_populate && 558 vmw_restrict_iommu) 559 dev_priv->map_mode = vmw_dma_map_bind; 560 561 if (vmw_force_coherent) 562 dev_priv->map_mode = vmw_dma_alloc_coherent; 563 564 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) 565 /* 566 * No coherent page pool 567 */ 568 if (dev_priv->map_mode == vmw_dma_alloc_coherent) 569 return -EINVAL; 570 #endif 571 572 #else /* CONFIG_X86 */ 573 dev_priv->map_mode = vmw_dma_map_populate; 574 #endif /* CONFIG_X86 */ 575 576 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 577 578 return 0; 579 } 580 581 /** 582 * vmw_dma_masks - set required page- and dma masks 583 * 584 * @dev: Pointer to struct drm-device 585 * 586 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 587 * restriction also for 64-bit systems. 588 */ 589 #ifdef CONFIG_INTEL_IOMMU 590 static int vmw_dma_masks(struct vmw_private *dev_priv) 591 { 592 struct drm_device *dev = dev_priv->dev; 593 594 if (intel_iommu_enabled && 595 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 596 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 597 return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); 598 } 599 return 0; 600 } 601 #else 602 static int vmw_dma_masks(struct vmw_private *dev_priv) 603 { 604 return 0; 605 } 606 #endif 607 608 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 609 { 610 struct vmw_private *dev_priv; 611 int ret; 612 uint32_t svga_id; 613 enum vmw_res_type i; 614 bool refuse_dma = false; 615 616 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 617 if (unlikely(dev_priv == NULL)) { 618 DRM_ERROR("Failed allocating a device private struct.\n"); 619 return -ENOMEM; 620 } 621 622 pci_set_master(dev->pdev); 623 624 dev_priv->dev = dev; 625 dev_priv->vmw_chipset = chipset; 626 dev_priv->last_read_seqno = (uint32_t) -100; 627 mutex_init(&dev_priv->cmdbuf_mutex); 628 mutex_init(&dev_priv->release_mutex); 629 mutex_init(&dev_priv->binding_mutex); 630 rwlock_init(&dev_priv->resource_lock); 631 ttm_lock_init(&dev_priv->reservation_sem); 632 spin_lock_init(&dev_priv->hw_lock); 633 spin_lock_init(&dev_priv->waiter_lock); 634 spin_lock_init(&dev_priv->cap_lock); 635 spin_lock_init(&dev_priv->svga_lock); 636 637 for (i = vmw_res_context; i < vmw_res_max; ++i) { 638 idr_init(&dev_priv->res_idr[i]); 639 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 640 } 641 642 mutex_init(&dev_priv->init_mutex); 643 init_waitqueue_head(&dev_priv->fence_queue); 644 init_waitqueue_head(&dev_priv->fifo_queue); 645 dev_priv->fence_queue_waiters = 0; 646 atomic_set(&dev_priv->fifo_queue_waiters, 0); 647 648 dev_priv->used_memory_size = 0; 649 650 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 651 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 652 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 653 654 dev_priv->enable_fb = enable_fbdev; 655 656 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 657 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 658 if (svga_id != SVGA_ID_2) { 659 ret = -ENOSYS; 660 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 661 goto out_err0; 662 } 663 664 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 665 ret = vmw_dma_select_mode(dev_priv); 666 if (unlikely(ret != 0)) { 667 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 668 refuse_dma = true; 669 } 670 671 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 672 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 673 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 674 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 675 676 vmw_get_initial_size(dev_priv); 677 678 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 679 dev_priv->max_gmr_ids = 680 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 681 dev_priv->max_gmr_pages = 682 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 683 dev_priv->memory_size = 684 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 685 dev_priv->memory_size -= dev_priv->vram_size; 686 } else { 687 /* 688 * An arbitrary limit of 512MiB on surface 689 * memory. But all HWV8 hardware supports GMR2. 690 */ 691 dev_priv->memory_size = 512*1024*1024; 692 } 693 dev_priv->max_mob_pages = 0; 694 dev_priv->max_mob_size = 0; 695 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 696 uint64_t mem_size = 697 vmw_read(dev_priv, 698 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 699 700 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 701 dev_priv->prim_bb_mem = 702 vmw_read(dev_priv, 703 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 704 dev_priv->max_mob_size = 705 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 706 dev_priv->stdu_max_width = 707 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 708 dev_priv->stdu_max_height = 709 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 710 711 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 712 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 713 dev_priv->texture_max_width = vmw_read(dev_priv, 714 SVGA_REG_DEV_CAP); 715 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 716 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 717 dev_priv->texture_max_height = vmw_read(dev_priv, 718 SVGA_REG_DEV_CAP); 719 } else { 720 dev_priv->texture_max_width = 8192; 721 dev_priv->texture_max_height = 8192; 722 dev_priv->prim_bb_mem = dev_priv->vram_size; 723 } 724 725 vmw_print_capabilities(dev_priv->capabilities); 726 727 ret = vmw_dma_masks(dev_priv); 728 if (unlikely(ret != 0)) 729 goto out_err0; 730 731 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 732 DRM_INFO("Max GMR ids is %u\n", 733 (unsigned)dev_priv->max_gmr_ids); 734 DRM_INFO("Max number of GMR pages is %u\n", 735 (unsigned)dev_priv->max_gmr_pages); 736 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 737 (unsigned)dev_priv->memory_size / 1024); 738 } 739 DRM_INFO("Maximum display memory size is %u kiB\n", 740 dev_priv->prim_bb_mem / 1024); 741 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 742 dev_priv->vram_start, dev_priv->vram_size / 1024); 743 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 744 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 745 746 ret = vmw_ttm_global_init(dev_priv); 747 if (unlikely(ret != 0)) 748 goto out_err0; 749 750 751 vmw_master_init(&dev_priv->fbdev_master); 752 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 753 dev_priv->active_master = &dev_priv->fbdev_master; 754 755 756 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start, 757 dev_priv->mmio_size); 758 759 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, 760 dev_priv->mmio_size); 761 762 if (unlikely(dev_priv->mmio_virt == NULL)) { 763 ret = -ENOMEM; 764 DRM_ERROR("Failed mapping MMIO.\n"); 765 goto out_err3; 766 } 767 768 /* Need mmio memory to check for fifo pitchlock cap. */ 769 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 770 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 771 !vmw_fifo_have_pitchlock(dev_priv)) { 772 ret = -ENOSYS; 773 DRM_ERROR("Hardware has no pitchlock\n"); 774 goto out_err4; 775 } 776 777 dev_priv->tdev = ttm_object_device_init 778 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); 779 780 if (unlikely(dev_priv->tdev == NULL)) { 781 DRM_ERROR("Unable to initialize TTM object management.\n"); 782 ret = -ENOMEM; 783 goto out_err4; 784 } 785 786 dev->dev_private = dev_priv; 787 788 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 789 dev_priv->stealth = (ret != 0); 790 if (dev_priv->stealth) { 791 /** 792 * Request at least the mmio PCI resource. 793 */ 794 795 DRM_INFO("It appears like vesafb is loaded. " 796 "Ignore above error if any.\n"); 797 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 798 if (unlikely(ret != 0)) { 799 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 800 goto out_no_device; 801 } 802 } 803 804 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 805 ret = drm_irq_install(dev, dev->pdev->irq); 806 if (ret != 0) { 807 DRM_ERROR("Failed installing irq: %d\n", ret); 808 goto out_no_irq; 809 } 810 } 811 812 dev_priv->fman = vmw_fence_manager_init(dev_priv); 813 if (unlikely(dev_priv->fman == NULL)) { 814 ret = -ENOMEM; 815 goto out_no_fman; 816 } 817 818 ret = ttm_bo_device_init(&dev_priv->bdev, 819 dev_priv->bo_global_ref.ref.object, 820 &vmw_bo_driver, 821 dev->anon_inode->i_mapping, 822 VMWGFX_FILE_PAGE_OFFSET, 823 false); 824 if (unlikely(ret != 0)) { 825 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 826 goto out_no_bdev; 827 } 828 829 /* 830 * Enable VRAM, but initially don't use it until SVGA is enabled and 831 * unhidden. 832 */ 833 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 834 (dev_priv->vram_size >> PAGE_SHIFT)); 835 if (unlikely(ret != 0)) { 836 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 837 goto out_no_vram; 838 } 839 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 840 841 dev_priv->has_gmr = true; 842 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 843 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 844 VMW_PL_GMR) != 0) { 845 DRM_INFO("No GMR memory available. " 846 "Graphics memory resources are very limited.\n"); 847 dev_priv->has_gmr = false; 848 } 849 850 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 851 dev_priv->has_mob = true; 852 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 853 VMW_PL_MOB) != 0) { 854 DRM_INFO("No MOB memory available. " 855 "3D will be disabled.\n"); 856 dev_priv->has_mob = false; 857 } 858 } 859 860 if (dev_priv->has_mob) { 861 spin_lock(&dev_priv->cap_lock); 862 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX); 863 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 864 spin_unlock(&dev_priv->cap_lock); 865 } 866 867 868 ret = vmw_kms_init(dev_priv); 869 if (unlikely(ret != 0)) 870 goto out_no_kms; 871 vmw_overlay_init(dev_priv); 872 873 ret = vmw_request_device(dev_priv); 874 if (ret) 875 goto out_no_fifo; 876 877 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 878 879 if (dev_priv->enable_fb) { 880 vmw_fifo_resource_inc(dev_priv); 881 vmw_svga_enable(dev_priv); 882 vmw_fb_init(dev_priv); 883 } 884 885 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 886 register_pm_notifier(&dev_priv->pm_nb); 887 888 return 0; 889 890 out_no_fifo: 891 vmw_overlay_close(dev_priv); 892 vmw_kms_close(dev_priv); 893 out_no_kms: 894 if (dev_priv->has_mob) 895 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 896 if (dev_priv->has_gmr) 897 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 898 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 899 out_no_vram: 900 (void)ttm_bo_device_release(&dev_priv->bdev); 901 out_no_bdev: 902 vmw_fence_manager_takedown(dev_priv->fman); 903 out_no_fman: 904 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 905 drm_irq_uninstall(dev_priv->dev); 906 out_no_irq: 907 if (dev_priv->stealth) 908 pci_release_region(dev->pdev, 2); 909 else 910 pci_release_regions(dev->pdev); 911 out_no_device: 912 ttm_object_device_release(&dev_priv->tdev); 913 out_err4: 914 iounmap(dev_priv->mmio_virt); 915 out_err3: 916 arch_phys_wc_del(dev_priv->mmio_mtrr); 917 vmw_ttm_global_release(dev_priv); 918 out_err0: 919 for (i = vmw_res_context; i < vmw_res_max; ++i) 920 idr_destroy(&dev_priv->res_idr[i]); 921 922 if (dev_priv->ctx.staged_bindings) 923 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 924 kfree(dev_priv); 925 return ret; 926 } 927 928 static int vmw_driver_unload(struct drm_device *dev) 929 { 930 struct vmw_private *dev_priv = vmw_priv(dev); 931 enum vmw_res_type i; 932 933 unregister_pm_notifier(&dev_priv->pm_nb); 934 935 if (dev_priv->ctx.res_ht_initialized) 936 drm_ht_remove(&dev_priv->ctx.res_ht); 937 vfree(dev_priv->ctx.cmd_bounce); 938 if (dev_priv->enable_fb) { 939 vmw_fb_off(dev_priv); 940 vmw_fb_close(dev_priv); 941 vmw_fifo_resource_dec(dev_priv); 942 vmw_svga_disable(dev_priv); 943 } 944 945 vmw_kms_close(dev_priv); 946 vmw_overlay_close(dev_priv); 947 948 if (dev_priv->has_gmr) 949 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 950 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 951 952 vmw_release_device_early(dev_priv); 953 if (dev_priv->has_mob) 954 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 955 (void) ttm_bo_device_release(&dev_priv->bdev); 956 vmw_release_device_late(dev_priv); 957 vmw_fence_manager_takedown(dev_priv->fman); 958 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 959 drm_irq_uninstall(dev_priv->dev); 960 if (dev_priv->stealth) 961 pci_release_region(dev->pdev, 2); 962 else 963 pci_release_regions(dev->pdev); 964 965 ttm_object_device_release(&dev_priv->tdev); 966 iounmap(dev_priv->mmio_virt); 967 arch_phys_wc_del(dev_priv->mmio_mtrr); 968 if (dev_priv->ctx.staged_bindings) 969 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 970 vmw_ttm_global_release(dev_priv); 971 972 for (i = vmw_res_context; i < vmw_res_max; ++i) 973 idr_destroy(&dev_priv->res_idr[i]); 974 975 kfree(dev_priv); 976 977 return 0; 978 } 979 980 static void vmw_preclose(struct drm_device *dev, 981 struct drm_file *file_priv) 982 { 983 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 984 struct vmw_private *dev_priv = vmw_priv(dev); 985 986 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events); 987 } 988 989 static void vmw_postclose(struct drm_device *dev, 990 struct drm_file *file_priv) 991 { 992 struct vmw_fpriv *vmw_fp; 993 994 vmw_fp = vmw_fpriv(file_priv); 995 996 if (vmw_fp->locked_master) { 997 struct vmw_master *vmaster = 998 vmw_master(vmw_fp->locked_master); 999 1000 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1001 ttm_vt_unlock(&vmaster->lock); 1002 drm_master_put(&vmw_fp->locked_master); 1003 } 1004 1005 ttm_object_file_release(&vmw_fp->tfile); 1006 kfree(vmw_fp); 1007 } 1008 1009 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1010 { 1011 struct vmw_private *dev_priv = vmw_priv(dev); 1012 struct vmw_fpriv *vmw_fp; 1013 int ret = -ENOMEM; 1014 1015 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1016 if (unlikely(vmw_fp == NULL)) 1017 return ret; 1018 1019 INIT_LIST_HEAD(&vmw_fp->fence_events); 1020 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1021 if (unlikely(vmw_fp->tfile == NULL)) 1022 goto out_no_tfile; 1023 1024 file_priv->driver_priv = vmw_fp; 1025 1026 return 0; 1027 1028 out_no_tfile: 1029 kfree(vmw_fp); 1030 return ret; 1031 } 1032 1033 static struct vmw_master *vmw_master_check(struct drm_device *dev, 1034 struct drm_file *file_priv, 1035 unsigned int flags) 1036 { 1037 int ret; 1038 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1039 struct vmw_master *vmaster; 1040 1041 if (file_priv->minor->type != DRM_MINOR_LEGACY || 1042 !(flags & DRM_AUTH)) 1043 return NULL; 1044 1045 ret = mutex_lock_interruptible(&dev->master_mutex); 1046 if (unlikely(ret != 0)) 1047 return ERR_PTR(-ERESTARTSYS); 1048 1049 if (file_priv->is_master) { 1050 mutex_unlock(&dev->master_mutex); 1051 return NULL; 1052 } 1053 1054 /* 1055 * Check if we were previously master, but now dropped. 1056 */ 1057 if (vmw_fp->locked_master) { 1058 mutex_unlock(&dev->master_mutex); 1059 DRM_ERROR("Dropped master trying to access ioctl that " 1060 "requires authentication.\n"); 1061 return ERR_PTR(-EACCES); 1062 } 1063 mutex_unlock(&dev->master_mutex); 1064 1065 /* 1066 * Taking the drm_global_mutex after the TTM lock might deadlock 1067 */ 1068 if (!(flags & DRM_UNLOCKED)) { 1069 DRM_ERROR("Refusing locked ioctl access.\n"); 1070 return ERR_PTR(-EDEADLK); 1071 } 1072 1073 /* 1074 * Take the TTM lock. Possibly sleep waiting for the authenticating 1075 * master to become master again, or for a SIGTERM if the 1076 * authenticating master exits. 1077 */ 1078 vmaster = vmw_master(file_priv->master); 1079 ret = ttm_read_lock(&vmaster->lock, true); 1080 if (unlikely(ret != 0)) 1081 vmaster = ERR_PTR(ret); 1082 1083 return vmaster; 1084 } 1085 1086 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1087 unsigned long arg, 1088 long (*ioctl_func)(struct file *, unsigned int, 1089 unsigned long)) 1090 { 1091 struct drm_file *file_priv = filp->private_data; 1092 struct drm_device *dev = file_priv->minor->dev; 1093 unsigned int nr = DRM_IOCTL_NR(cmd); 1094 struct vmw_master *vmaster; 1095 unsigned int flags; 1096 long ret; 1097 1098 /* 1099 * Do extra checking on driver private ioctls. 1100 */ 1101 1102 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1103 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1104 const struct drm_ioctl_desc *ioctl = 1105 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1106 1107 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1108 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); 1109 if (unlikely(ret != 0)) 1110 return ret; 1111 1112 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) 1113 goto out_io_encoding; 1114 1115 return (long) vmw_execbuf_ioctl(dev, arg, file_priv, 1116 _IOC_SIZE(cmd)); 1117 } 1118 1119 if (unlikely(ioctl->cmd != cmd)) 1120 goto out_io_encoding; 1121 1122 flags = ioctl->flags; 1123 } else if (!drm_ioctl_flags(nr, &flags)) 1124 return -EINVAL; 1125 1126 vmaster = vmw_master_check(dev, file_priv, flags); 1127 if (IS_ERR(vmaster)) { 1128 ret = PTR_ERR(vmaster); 1129 1130 if (ret != -ERESTARTSYS) 1131 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", 1132 nr, ret); 1133 return ret; 1134 } 1135 1136 ret = ioctl_func(filp, cmd, arg); 1137 if (vmaster) 1138 ttm_read_unlock(&vmaster->lock); 1139 1140 return ret; 1141 1142 out_io_encoding: 1143 DRM_ERROR("Invalid command format, ioctl %d\n", 1144 nr - DRM_COMMAND_BASE); 1145 1146 return -EINVAL; 1147 } 1148 1149 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1150 unsigned long arg) 1151 { 1152 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1153 } 1154 1155 #ifdef CONFIG_COMPAT 1156 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1157 unsigned long arg) 1158 { 1159 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1160 } 1161 #endif 1162 1163 static void vmw_lastclose(struct drm_device *dev) 1164 { 1165 } 1166 1167 static void vmw_master_init(struct vmw_master *vmaster) 1168 { 1169 ttm_lock_init(&vmaster->lock); 1170 } 1171 1172 static int vmw_master_create(struct drm_device *dev, 1173 struct drm_master *master) 1174 { 1175 struct vmw_master *vmaster; 1176 1177 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); 1178 if (unlikely(vmaster == NULL)) 1179 return -ENOMEM; 1180 1181 vmw_master_init(vmaster); 1182 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1183 master->driver_priv = vmaster; 1184 1185 return 0; 1186 } 1187 1188 static void vmw_master_destroy(struct drm_device *dev, 1189 struct drm_master *master) 1190 { 1191 struct vmw_master *vmaster = vmw_master(master); 1192 1193 master->driver_priv = NULL; 1194 kfree(vmaster); 1195 } 1196 1197 static int vmw_master_set(struct drm_device *dev, 1198 struct drm_file *file_priv, 1199 bool from_open) 1200 { 1201 struct vmw_private *dev_priv = vmw_priv(dev); 1202 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1203 struct vmw_master *active = dev_priv->active_master; 1204 struct vmw_master *vmaster = vmw_master(file_priv->master); 1205 int ret = 0; 1206 1207 if (active) { 1208 BUG_ON(active != &dev_priv->fbdev_master); 1209 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 1210 if (unlikely(ret != 0)) 1211 return ret; 1212 1213 ttm_lock_set_kill(&active->lock, true, SIGTERM); 1214 dev_priv->active_master = NULL; 1215 } 1216 1217 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1218 if (!from_open) { 1219 ttm_vt_unlock(&vmaster->lock); 1220 BUG_ON(vmw_fp->locked_master != file_priv->master); 1221 drm_master_put(&vmw_fp->locked_master); 1222 } 1223 1224 dev_priv->active_master = vmaster; 1225 1226 return 0; 1227 } 1228 1229 static void vmw_master_drop(struct drm_device *dev, 1230 struct drm_file *file_priv, 1231 bool from_release) 1232 { 1233 struct vmw_private *dev_priv = vmw_priv(dev); 1234 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1235 struct vmw_master *vmaster = vmw_master(file_priv->master); 1236 int ret; 1237 1238 /** 1239 * Make sure the master doesn't disappear while we have 1240 * it locked. 1241 */ 1242 1243 vmw_fp->locked_master = drm_master_get(file_priv->master); 1244 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 1245 if (unlikely((ret != 0))) { 1246 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 1247 drm_master_put(&vmw_fp->locked_master); 1248 } 1249 1250 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1251 1252 if (!dev_priv->enable_fb) 1253 vmw_svga_disable(dev_priv); 1254 1255 dev_priv->active_master = &dev_priv->fbdev_master; 1256 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 1257 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 1258 1259 if (dev_priv->enable_fb) 1260 vmw_fb_on(dev_priv); 1261 } 1262 1263 /** 1264 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1265 * 1266 * @dev_priv: Pointer to device private struct. 1267 * Needs the reservation sem to be held in non-exclusive mode. 1268 */ 1269 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1270 { 1271 spin_lock(&dev_priv->svga_lock); 1272 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1273 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1274 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1275 } 1276 spin_unlock(&dev_priv->svga_lock); 1277 } 1278 1279 /** 1280 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1281 * 1282 * @dev_priv: Pointer to device private struct. 1283 */ 1284 void vmw_svga_enable(struct vmw_private *dev_priv) 1285 { 1286 ttm_read_lock(&dev_priv->reservation_sem, false); 1287 __vmw_svga_enable(dev_priv); 1288 ttm_read_unlock(&dev_priv->reservation_sem); 1289 } 1290 1291 /** 1292 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1293 * 1294 * @dev_priv: Pointer to device private struct. 1295 * Needs the reservation sem to be held in exclusive mode. 1296 * Will not empty VRAM. VRAM must be emptied by caller. 1297 */ 1298 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1299 { 1300 spin_lock(&dev_priv->svga_lock); 1301 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1302 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1303 vmw_write(dev_priv, SVGA_REG_ENABLE, 1304 SVGA_REG_ENABLE_HIDE | 1305 SVGA_REG_ENABLE_ENABLE); 1306 } 1307 spin_unlock(&dev_priv->svga_lock); 1308 } 1309 1310 /** 1311 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1312 * running. 1313 * 1314 * @dev_priv: Pointer to device private struct. 1315 * Will empty VRAM. 1316 */ 1317 void vmw_svga_disable(struct vmw_private *dev_priv) 1318 { 1319 ttm_write_lock(&dev_priv->reservation_sem, false); 1320 spin_lock(&dev_priv->svga_lock); 1321 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1322 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1323 spin_unlock(&dev_priv->svga_lock); 1324 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1325 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1326 vmw_write(dev_priv, SVGA_REG_ENABLE, 1327 SVGA_REG_ENABLE_HIDE | 1328 SVGA_REG_ENABLE_ENABLE); 1329 } else 1330 spin_unlock(&dev_priv->svga_lock); 1331 ttm_write_unlock(&dev_priv->reservation_sem); 1332 } 1333 1334 static void vmw_remove(struct pci_dev *pdev) 1335 { 1336 struct drm_device *dev = pci_get_drvdata(pdev); 1337 1338 pci_disable_device(pdev); 1339 drm_put_dev(dev); 1340 } 1341 1342 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1343 void *ptr) 1344 { 1345 struct vmw_private *dev_priv = 1346 container_of(nb, struct vmw_private, pm_nb); 1347 1348 switch (val) { 1349 case PM_HIBERNATION_PREPARE: 1350 if (dev_priv->enable_fb) 1351 vmw_fb_off(dev_priv); 1352 ttm_suspend_lock(&dev_priv->reservation_sem); 1353 1354 /* 1355 * This empties VRAM and unbinds all GMR bindings. 1356 * Buffer contents is moved to swappable memory. 1357 */ 1358 vmw_execbuf_release_pinned_bo(dev_priv); 1359 vmw_resource_evict_all(dev_priv); 1360 vmw_release_device_early(dev_priv); 1361 ttm_bo_swapout_all(&dev_priv->bdev); 1362 vmw_fence_fifo_down(dev_priv->fman); 1363 break; 1364 case PM_POST_HIBERNATION: 1365 case PM_POST_RESTORE: 1366 vmw_fence_fifo_up(dev_priv->fman); 1367 ttm_suspend_unlock(&dev_priv->reservation_sem); 1368 if (dev_priv->enable_fb) 1369 vmw_fb_on(dev_priv); 1370 break; 1371 case PM_RESTORE_PREPARE: 1372 break; 1373 default: 1374 break; 1375 } 1376 return 0; 1377 } 1378 1379 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1380 { 1381 struct drm_device *dev = pci_get_drvdata(pdev); 1382 struct vmw_private *dev_priv = vmw_priv(dev); 1383 1384 if (dev_priv->refuse_hibernation) 1385 return -EBUSY; 1386 1387 pci_save_state(pdev); 1388 pci_disable_device(pdev); 1389 pci_set_power_state(pdev, PCI_D3hot); 1390 return 0; 1391 } 1392 1393 static int vmw_pci_resume(struct pci_dev *pdev) 1394 { 1395 pci_set_power_state(pdev, PCI_D0); 1396 pci_restore_state(pdev); 1397 return pci_enable_device(pdev); 1398 } 1399 1400 static int vmw_pm_suspend(struct device *kdev) 1401 { 1402 struct pci_dev *pdev = to_pci_dev(kdev); 1403 struct pm_message dummy; 1404 1405 dummy.event = 0; 1406 1407 return vmw_pci_suspend(pdev, dummy); 1408 } 1409 1410 static int vmw_pm_resume(struct device *kdev) 1411 { 1412 struct pci_dev *pdev = to_pci_dev(kdev); 1413 1414 return vmw_pci_resume(pdev); 1415 } 1416 1417 static int vmw_pm_freeze(struct device *kdev) 1418 { 1419 struct pci_dev *pdev = to_pci_dev(kdev); 1420 struct drm_device *dev = pci_get_drvdata(pdev); 1421 struct vmw_private *dev_priv = vmw_priv(dev); 1422 1423 dev_priv->suspended = true; 1424 if (dev_priv->enable_fb) 1425 vmw_fifo_resource_dec(dev_priv); 1426 1427 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1428 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1429 if (dev_priv->enable_fb) 1430 vmw_fifo_resource_inc(dev_priv); 1431 WARN_ON(vmw_request_device_late(dev_priv)); 1432 dev_priv->suspended = false; 1433 return -EBUSY; 1434 } 1435 1436 if (dev_priv->enable_fb) 1437 __vmw_svga_disable(dev_priv); 1438 1439 vmw_release_device_late(dev_priv); 1440 1441 return 0; 1442 } 1443 1444 static int vmw_pm_restore(struct device *kdev) 1445 { 1446 struct pci_dev *pdev = to_pci_dev(kdev); 1447 struct drm_device *dev = pci_get_drvdata(pdev); 1448 struct vmw_private *dev_priv = vmw_priv(dev); 1449 int ret; 1450 1451 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1452 (void) vmw_read(dev_priv, SVGA_REG_ID); 1453 1454 if (dev_priv->enable_fb) 1455 vmw_fifo_resource_inc(dev_priv); 1456 1457 ret = vmw_request_device(dev_priv); 1458 if (ret) 1459 return ret; 1460 1461 if (dev_priv->enable_fb) 1462 __vmw_svga_enable(dev_priv); 1463 1464 dev_priv->suspended = false; 1465 1466 return 0; 1467 } 1468 1469 static const struct dev_pm_ops vmw_pm_ops = { 1470 .freeze = vmw_pm_freeze, 1471 .thaw = vmw_pm_restore, 1472 .restore = vmw_pm_restore, 1473 .suspend = vmw_pm_suspend, 1474 .resume = vmw_pm_resume, 1475 }; 1476 1477 static const struct file_operations vmwgfx_driver_fops = { 1478 .owner = THIS_MODULE, 1479 .open = drm_open, 1480 .release = drm_release, 1481 .unlocked_ioctl = vmw_unlocked_ioctl, 1482 .mmap = vmw_mmap, 1483 .poll = vmw_fops_poll, 1484 .read = vmw_fops_read, 1485 #if defined(CONFIG_COMPAT) 1486 .compat_ioctl = vmw_compat_ioctl, 1487 #endif 1488 .llseek = noop_llseek, 1489 }; 1490 1491 static struct drm_driver driver = { 1492 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | 1493 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER, 1494 .load = vmw_driver_load, 1495 .unload = vmw_driver_unload, 1496 .lastclose = vmw_lastclose, 1497 .irq_preinstall = vmw_irq_preinstall, 1498 .irq_postinstall = vmw_irq_postinstall, 1499 .irq_uninstall = vmw_irq_uninstall, 1500 .irq_handler = vmw_irq_handler, 1501 .get_vblank_counter = vmw_get_vblank_counter, 1502 .enable_vblank = vmw_enable_vblank, 1503 .disable_vblank = vmw_disable_vblank, 1504 .ioctls = vmw_ioctls, 1505 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1506 .master_create = vmw_master_create, 1507 .master_destroy = vmw_master_destroy, 1508 .master_set = vmw_master_set, 1509 .master_drop = vmw_master_drop, 1510 .open = vmw_driver_open, 1511 .preclose = vmw_preclose, 1512 .postclose = vmw_postclose, 1513 .set_busid = drm_pci_set_busid, 1514 1515 .dumb_create = vmw_dumb_create, 1516 .dumb_map_offset = vmw_dumb_map_offset, 1517 .dumb_destroy = vmw_dumb_destroy, 1518 1519 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1520 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1521 1522 .fops = &vmwgfx_driver_fops, 1523 .name = VMWGFX_DRIVER_NAME, 1524 .desc = VMWGFX_DRIVER_DESC, 1525 .date = VMWGFX_DRIVER_DATE, 1526 .major = VMWGFX_DRIVER_MAJOR, 1527 .minor = VMWGFX_DRIVER_MINOR, 1528 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1529 }; 1530 1531 static struct pci_driver vmw_pci_driver = { 1532 .name = VMWGFX_DRIVER_NAME, 1533 .id_table = vmw_pci_id_list, 1534 .probe = vmw_probe, 1535 .remove = vmw_remove, 1536 .driver = { 1537 .pm = &vmw_pm_ops 1538 } 1539 }; 1540 1541 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1542 { 1543 return drm_get_pci_dev(pdev, ent, &driver); 1544 } 1545 1546 static int __init vmwgfx_init(void) 1547 { 1548 int ret; 1549 ret = drm_pci_init(&driver, &vmw_pci_driver); 1550 if (ret) 1551 DRM_ERROR("Failed initializing DRM.\n"); 1552 return ret; 1553 } 1554 1555 static void __exit vmwgfx_exit(void) 1556 { 1557 drm_pci_exit(&driver, &vmw_pci_driver); 1558 } 1559 1560 module_init(vmwgfx_init); 1561 module_exit(vmwgfx_exit); 1562 1563 MODULE_AUTHOR("VMware Inc. and others"); 1564 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1565 MODULE_LICENSE("GPL and additional rights"); 1566 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1567 __stringify(VMWGFX_DRIVER_MINOR) "." 1568 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1569 "0"); 1570