1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include <linux/console.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/mem_encrypt.h> 33 34 #include <drm/drm_drv.h> 35 #include <drm/drm_ioctl.h> 36 #include <drm/drm_sysfs.h> 37 #include <drm/ttm/ttm_bo_driver.h> 38 #include <drm/ttm/ttm_placement.h> 39 40 #include "ttm_object.h" 41 #include "vmwgfx_binding.h" 42 #include "vmwgfx_drv.h" 43 44 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 45 #define VMWGFX_CHIP_SVGAII 0 46 #define VMW_FB_RESERVATION 0 47 48 #define VMW_MIN_INITIAL_WIDTH 800 49 #define VMW_MIN_INITIAL_HEIGHT 600 50 51 #ifndef VMWGFX_GIT_VERSION 52 #define VMWGFX_GIT_VERSION "Unknown" 53 #endif 54 55 #define VMWGFX_REPO "In Tree" 56 57 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 58 59 60 /** 61 * Fully encoded drm commands. Might move to vmw_drm.h 62 */ 63 64 #define DRM_IOCTL_VMW_GET_PARAM \ 65 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 66 struct drm_vmw_getparam_arg) 67 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 68 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 69 union drm_vmw_alloc_dmabuf_arg) 70 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 72 struct drm_vmw_unref_dmabuf_arg) 73 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 74 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 75 struct drm_vmw_cursor_bypass_arg) 76 77 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 79 struct drm_vmw_control_stream_arg) 80 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 81 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 82 struct drm_vmw_stream_arg) 83 #define DRM_IOCTL_VMW_UNREF_STREAM \ 84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 85 struct drm_vmw_stream_arg) 86 87 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 88 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 89 struct drm_vmw_context_arg) 90 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 92 struct drm_vmw_context_arg) 93 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 94 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 95 union drm_vmw_surface_create_arg) 96 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 97 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 98 struct drm_vmw_surface_arg) 99 #define DRM_IOCTL_VMW_REF_SURFACE \ 100 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 101 union drm_vmw_surface_reference_arg) 102 #define DRM_IOCTL_VMW_EXECBUF \ 103 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 104 struct drm_vmw_execbuf_arg) 105 #define DRM_IOCTL_VMW_GET_3D_CAP \ 106 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 107 struct drm_vmw_get_3d_cap_arg) 108 #define DRM_IOCTL_VMW_FENCE_WAIT \ 109 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 110 struct drm_vmw_fence_wait_arg) 111 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 112 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 113 struct drm_vmw_fence_signaled_arg) 114 #define DRM_IOCTL_VMW_FENCE_UNREF \ 115 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 116 struct drm_vmw_fence_arg) 117 #define DRM_IOCTL_VMW_FENCE_EVENT \ 118 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 119 struct drm_vmw_fence_event_arg) 120 #define DRM_IOCTL_VMW_PRESENT \ 121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 122 struct drm_vmw_present_arg) 123 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 124 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 125 struct drm_vmw_present_readback_arg) 126 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 127 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 128 struct drm_vmw_update_layout_arg) 129 #define DRM_IOCTL_VMW_CREATE_SHADER \ 130 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 131 struct drm_vmw_shader_create_arg) 132 #define DRM_IOCTL_VMW_UNREF_SHADER \ 133 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 134 struct drm_vmw_shader_arg) 135 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 136 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 137 union drm_vmw_gb_surface_create_arg) 138 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 139 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 140 union drm_vmw_gb_surface_reference_arg) 141 #define DRM_IOCTL_VMW_SYNCCPU \ 142 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 143 struct drm_vmw_synccpu_arg) 144 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 145 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 146 struct drm_vmw_context_arg) 147 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 148 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 149 union drm_vmw_gb_surface_create_ext_arg) 150 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 151 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 152 union drm_vmw_gb_surface_reference_ext_arg) 153 #define DRM_IOCTL_VMW_MSG \ 154 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 155 struct drm_vmw_msg_arg) 156 157 /** 158 * The core DRM version of this macro doesn't account for 159 * DRM_COMMAND_BASE. 160 */ 161 162 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 163 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 164 165 /** 166 * Ioctl definitions. 167 */ 168 169 static const struct drm_ioctl_desc vmw_ioctls[] = { 170 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 171 DRM_RENDER_ALLOW), 172 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 173 DRM_RENDER_ALLOW), 174 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 175 DRM_RENDER_ALLOW), 176 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 177 vmw_kms_cursor_bypass_ioctl, 178 DRM_MASTER), 179 180 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 181 DRM_MASTER), 182 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 183 DRM_MASTER), 184 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 185 DRM_MASTER), 186 187 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 188 DRM_RENDER_ALLOW), 189 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 190 DRM_RENDER_ALLOW), 191 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 192 DRM_RENDER_ALLOW), 193 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 194 DRM_RENDER_ALLOW), 195 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 196 DRM_RENDER_ALLOW), 197 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, 198 DRM_RENDER_ALLOW), 199 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 200 DRM_RENDER_ALLOW), 201 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 202 vmw_fence_obj_signaled_ioctl, 203 DRM_RENDER_ALLOW), 204 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 205 DRM_RENDER_ALLOW), 206 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 207 DRM_RENDER_ALLOW), 208 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 209 DRM_RENDER_ALLOW), 210 211 /* these allow direct access to the framebuffers mark as master only */ 212 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 213 DRM_MASTER | DRM_AUTH), 214 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 215 vmw_present_readback_ioctl, 216 DRM_MASTER | DRM_AUTH), 217 /* 218 * The permissions of the below ioctl are overridden in 219 * vmw_generic_ioctl(). We require either 220 * DRM_MASTER or capable(CAP_SYS_ADMIN). 221 */ 222 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 223 vmw_kms_update_layout_ioctl, 224 DRM_RENDER_ALLOW), 225 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 226 vmw_shader_define_ioctl, 227 DRM_RENDER_ALLOW), 228 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 229 vmw_shader_destroy_ioctl, 230 DRM_RENDER_ALLOW), 231 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 232 vmw_gb_surface_define_ioctl, 233 DRM_RENDER_ALLOW), 234 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 235 vmw_gb_surface_reference_ioctl, 236 DRM_RENDER_ALLOW), 237 VMW_IOCTL_DEF(VMW_SYNCCPU, 238 vmw_user_bo_synccpu_ioctl, 239 DRM_RENDER_ALLOW), 240 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 241 vmw_extended_context_define_ioctl, 242 DRM_RENDER_ALLOW), 243 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 244 vmw_gb_surface_define_ext_ioctl, 245 DRM_RENDER_ALLOW), 246 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 247 vmw_gb_surface_reference_ext_ioctl, 248 DRM_RENDER_ALLOW), 249 VMW_IOCTL_DEF(VMW_MSG, 250 vmw_msg_ioctl, 251 DRM_RENDER_ALLOW), 252 }; 253 254 static const struct pci_device_id vmw_pci_id_list[] = { 255 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 256 {0, 0, 0} 257 }; 258 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 259 260 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 261 static int vmw_force_iommu; 262 static int vmw_restrict_iommu; 263 static int vmw_force_coherent; 264 static int vmw_restrict_dma_mask; 265 static int vmw_assume_16bpp; 266 267 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 268 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 269 void *ptr); 270 271 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 272 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 273 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 274 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 275 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 276 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 277 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 278 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 279 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 280 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 281 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 282 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 283 284 285 static void vmw_print_capabilities2(uint32_t capabilities2) 286 { 287 DRM_INFO("Capabilities2:\n"); 288 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 289 DRM_INFO(" Grow oTable.\n"); 290 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 291 DRM_INFO(" IntraSurface copy.\n"); 292 if (capabilities2 & SVGA_CAP2_DX3) 293 DRM_INFO(" DX3.\n"); 294 } 295 296 static void vmw_print_capabilities(uint32_t capabilities) 297 { 298 DRM_INFO("Capabilities:\n"); 299 if (capabilities & SVGA_CAP_RECT_COPY) 300 DRM_INFO(" Rect copy.\n"); 301 if (capabilities & SVGA_CAP_CURSOR) 302 DRM_INFO(" Cursor.\n"); 303 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 304 DRM_INFO(" Cursor bypass.\n"); 305 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 306 DRM_INFO(" Cursor bypass 2.\n"); 307 if (capabilities & SVGA_CAP_8BIT_EMULATION) 308 DRM_INFO(" 8bit emulation.\n"); 309 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 310 DRM_INFO(" Alpha cursor.\n"); 311 if (capabilities & SVGA_CAP_3D) 312 DRM_INFO(" 3D.\n"); 313 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 314 DRM_INFO(" Extended Fifo.\n"); 315 if (capabilities & SVGA_CAP_MULTIMON) 316 DRM_INFO(" Multimon.\n"); 317 if (capabilities & SVGA_CAP_PITCHLOCK) 318 DRM_INFO(" Pitchlock.\n"); 319 if (capabilities & SVGA_CAP_IRQMASK) 320 DRM_INFO(" Irq mask.\n"); 321 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 322 DRM_INFO(" Display Topology.\n"); 323 if (capabilities & SVGA_CAP_GMR) 324 DRM_INFO(" GMR.\n"); 325 if (capabilities & SVGA_CAP_TRACES) 326 DRM_INFO(" Traces.\n"); 327 if (capabilities & SVGA_CAP_GMR2) 328 DRM_INFO(" GMR2.\n"); 329 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 330 DRM_INFO(" Screen Object 2.\n"); 331 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 332 DRM_INFO(" Command Buffers.\n"); 333 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 334 DRM_INFO(" Command Buffers 2.\n"); 335 if (capabilities & SVGA_CAP_GBOBJECTS) 336 DRM_INFO(" Guest Backed Resources.\n"); 337 if (capabilities & SVGA_CAP_DX) 338 DRM_INFO(" DX Features.\n"); 339 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 340 DRM_INFO(" HP Command Queue.\n"); 341 } 342 343 /** 344 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 345 * 346 * @dev_priv: A device private structure. 347 * 348 * This function creates a small buffer object that holds the query 349 * result for dummy queries emitted as query barriers. 350 * The function will then map the first page and initialize a pending 351 * occlusion query result structure, Finally it will unmap the buffer. 352 * No interruptible waits are done within this function. 353 * 354 * Returns an error if bo creation or initialization fails. 355 */ 356 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 357 { 358 int ret; 359 struct vmw_buffer_object *vbo; 360 struct ttm_bo_kmap_obj map; 361 volatile SVGA3dQueryResult *result; 362 bool dummy; 363 364 /* 365 * Create the vbo as pinned, so that a tryreserve will 366 * immediately succeed. This is because we're the only 367 * user of the bo currently. 368 */ 369 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 370 if (!vbo) 371 return -ENOMEM; 372 373 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 374 &vmw_sys_placement, false, true, 375 &vmw_bo_bo_free); 376 if (unlikely(ret != 0)) 377 return ret; 378 379 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 380 BUG_ON(ret != 0); 381 vmw_bo_pin_reserved(vbo, true); 382 383 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 384 if (likely(ret == 0)) { 385 result = ttm_kmap_obj_virtual(&map, &dummy); 386 result->totalSize = sizeof(*result); 387 result->state = SVGA3D_QUERYSTATE_PENDING; 388 result->result32 = 0xff; 389 ttm_bo_kunmap(&map); 390 } 391 vmw_bo_pin_reserved(vbo, false); 392 ttm_bo_unreserve(&vbo->base); 393 394 if (unlikely(ret != 0)) { 395 DRM_ERROR("Dummy query buffer map failed.\n"); 396 vmw_bo_unreference(&vbo); 397 } else 398 dev_priv->dummy_query_bo = vbo; 399 400 return ret; 401 } 402 403 /** 404 * vmw_request_device_late - Perform late device setup 405 * 406 * @dev_priv: Pointer to device private. 407 * 408 * This function performs setup of otables and enables large command 409 * buffer submission. These tasks are split out to a separate function 410 * because it reverts vmw_release_device_early and is intended to be used 411 * by an error path in the hibernation code. 412 */ 413 static int vmw_request_device_late(struct vmw_private *dev_priv) 414 { 415 int ret; 416 417 if (dev_priv->has_mob) { 418 ret = vmw_otables_setup(dev_priv); 419 if (unlikely(ret != 0)) { 420 DRM_ERROR("Unable to initialize " 421 "guest Memory OBjects.\n"); 422 return ret; 423 } 424 } 425 426 if (dev_priv->cman) { 427 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 428 256*4096, 2*4096); 429 if (ret) { 430 struct vmw_cmdbuf_man *man = dev_priv->cman; 431 432 dev_priv->cman = NULL; 433 vmw_cmdbuf_man_destroy(man); 434 } 435 } 436 437 return 0; 438 } 439 440 static int vmw_request_device(struct vmw_private *dev_priv) 441 { 442 int ret; 443 444 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 445 if (unlikely(ret != 0)) { 446 DRM_ERROR("Unable to initialize FIFO.\n"); 447 return ret; 448 } 449 vmw_fence_fifo_up(dev_priv->fman); 450 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 451 if (IS_ERR(dev_priv->cman)) { 452 dev_priv->cman = NULL; 453 dev_priv->sm_type = VMW_SM_LEGACY; 454 } 455 456 ret = vmw_request_device_late(dev_priv); 457 if (ret) 458 goto out_no_mob; 459 460 ret = vmw_dummy_query_bo_create(dev_priv); 461 if (unlikely(ret != 0)) 462 goto out_no_query_bo; 463 464 return 0; 465 466 out_no_query_bo: 467 if (dev_priv->cman) 468 vmw_cmdbuf_remove_pool(dev_priv->cman); 469 if (dev_priv->has_mob) { 470 struct ttm_resource_manager *man; 471 472 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 473 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 474 vmw_otables_takedown(dev_priv); 475 } 476 if (dev_priv->cman) 477 vmw_cmdbuf_man_destroy(dev_priv->cman); 478 out_no_mob: 479 vmw_fence_fifo_down(dev_priv->fman); 480 vmw_fifo_release(dev_priv, &dev_priv->fifo); 481 return ret; 482 } 483 484 /** 485 * vmw_release_device_early - Early part of fifo takedown. 486 * 487 * @dev_priv: Pointer to device private struct. 488 * 489 * This is the first part of command submission takedown, to be called before 490 * buffer management is taken down. 491 */ 492 static void vmw_release_device_early(struct vmw_private *dev_priv) 493 { 494 /* 495 * Previous destructions should've released 496 * the pinned bo. 497 */ 498 499 BUG_ON(dev_priv->pinned_bo != NULL); 500 501 vmw_bo_unreference(&dev_priv->dummy_query_bo); 502 if (dev_priv->cman) 503 vmw_cmdbuf_remove_pool(dev_priv->cman); 504 505 if (dev_priv->has_mob) { 506 struct ttm_resource_manager *man; 507 508 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 509 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 510 vmw_otables_takedown(dev_priv); 511 } 512 } 513 514 /** 515 * vmw_release_device_late - Late part of fifo takedown. 516 * 517 * @dev_priv: Pointer to device private struct. 518 * 519 * This is the last part of the command submission takedown, to be called when 520 * command submission is no longer needed. It may wait on pending fences. 521 */ 522 static void vmw_release_device_late(struct vmw_private *dev_priv) 523 { 524 vmw_fence_fifo_down(dev_priv->fman); 525 if (dev_priv->cman) 526 vmw_cmdbuf_man_destroy(dev_priv->cman); 527 528 vmw_fifo_release(dev_priv, &dev_priv->fifo); 529 } 530 531 /** 532 * Sets the initial_[width|height] fields on the given vmw_private. 533 * 534 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 535 * clamping the value to fb_max_[width|height] fields and the 536 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 537 * If the values appear to be invalid, set them to 538 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 539 */ 540 static void vmw_get_initial_size(struct vmw_private *dev_priv) 541 { 542 uint32_t width; 543 uint32_t height; 544 545 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 546 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 547 548 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 549 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 550 551 if (width > dev_priv->fb_max_width || 552 height > dev_priv->fb_max_height) { 553 554 /* 555 * This is a host error and shouldn't occur. 556 */ 557 558 width = VMW_MIN_INITIAL_WIDTH; 559 height = VMW_MIN_INITIAL_HEIGHT; 560 } 561 562 dev_priv->initial_width = width; 563 dev_priv->initial_height = height; 564 } 565 566 /** 567 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 568 * system. 569 * 570 * @dev_priv: Pointer to a struct vmw_private 571 * 572 * This functions tries to determine what actions need to be taken by the 573 * driver to make system pages visible to the device. 574 * If this function decides that DMA is not possible, it returns -EINVAL. 575 * The driver may then try to disable features of the device that require 576 * DMA. 577 */ 578 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 579 { 580 static const char *names[vmw_dma_map_max] = { 581 [vmw_dma_phys] = "Using physical TTM page addresses.", 582 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 583 [vmw_dma_map_populate] = "Caching DMA mappings.", 584 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 585 586 /* TTM currently doesn't fully support SEV encryption. */ 587 if (mem_encrypt_active()) 588 return -EINVAL; 589 590 if (vmw_force_coherent) 591 dev_priv->map_mode = vmw_dma_alloc_coherent; 592 else if (vmw_restrict_iommu) 593 dev_priv->map_mode = vmw_dma_map_bind; 594 else 595 dev_priv->map_mode = vmw_dma_map_populate; 596 597 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 598 return 0; 599 } 600 601 /** 602 * vmw_dma_masks - set required page- and dma masks 603 * 604 * @dev: Pointer to struct drm-device 605 * 606 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 607 * restriction also for 64-bit systems. 608 */ 609 static int vmw_dma_masks(struct vmw_private *dev_priv) 610 { 611 struct drm_device *dev = dev_priv->dev; 612 int ret = 0; 613 614 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 615 if (dev_priv->map_mode != vmw_dma_phys && 616 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 617 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 618 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 619 } 620 621 return ret; 622 } 623 624 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 625 { 626 int ret; 627 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 628 ret = vmw_thp_init(dev_priv); 629 #else 630 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 631 dev_priv->vram_size >> PAGE_SHIFT); 632 #endif 633 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 634 return ret; 635 } 636 637 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 638 { 639 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 640 vmw_thp_fini(dev_priv); 641 #else 642 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 643 #endif 644 } 645 646 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 647 { 648 struct vmw_private *dev_priv; 649 int ret; 650 uint32_t svga_id; 651 enum vmw_res_type i; 652 bool refuse_dma = false; 653 char host_log[100] = {0}; 654 struct pci_dev *pdev = to_pci_dev(dev->dev); 655 656 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 657 if (unlikely(!dev_priv)) { 658 DRM_ERROR("Failed allocating a device private struct.\n"); 659 return -ENOMEM; 660 } 661 662 pci_set_master(pdev); 663 664 dev_priv->dev = dev; 665 dev_priv->vmw_chipset = chipset; 666 dev_priv->last_read_seqno = (uint32_t) -100; 667 mutex_init(&dev_priv->cmdbuf_mutex); 668 mutex_init(&dev_priv->release_mutex); 669 mutex_init(&dev_priv->binding_mutex); 670 mutex_init(&dev_priv->global_kms_state_mutex); 671 ttm_lock_init(&dev_priv->reservation_sem); 672 spin_lock_init(&dev_priv->resource_lock); 673 spin_lock_init(&dev_priv->hw_lock); 674 spin_lock_init(&dev_priv->waiter_lock); 675 spin_lock_init(&dev_priv->cap_lock); 676 spin_lock_init(&dev_priv->svga_lock); 677 spin_lock_init(&dev_priv->cursor_lock); 678 679 for (i = vmw_res_context; i < vmw_res_max; ++i) { 680 idr_init(&dev_priv->res_idr[i]); 681 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 682 } 683 684 init_waitqueue_head(&dev_priv->fence_queue); 685 init_waitqueue_head(&dev_priv->fifo_queue); 686 dev_priv->fence_queue_waiters = 0; 687 dev_priv->fifo_queue_waiters = 0; 688 689 dev_priv->used_memory_size = 0; 690 691 dev_priv->io_start = pci_resource_start(pdev, 0); 692 dev_priv->vram_start = pci_resource_start(pdev, 1); 693 dev_priv->mmio_start = pci_resource_start(pdev, 2); 694 695 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 696 697 dev_priv->enable_fb = enable_fbdev; 698 699 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 700 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 701 if (svga_id != SVGA_ID_2) { 702 ret = -ENOSYS; 703 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 704 goto out_err0; 705 } 706 707 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 708 709 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 710 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 711 } 712 713 714 ret = vmw_dma_select_mode(dev_priv); 715 if (unlikely(ret != 0)) { 716 DRM_INFO("Restricting capabilities since DMA not available.\n"); 717 refuse_dma = true; 718 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 719 DRM_INFO("Disabling 3D acceleration.\n"); 720 } 721 722 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 723 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 724 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 725 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 726 727 vmw_get_initial_size(dev_priv); 728 729 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 730 dev_priv->max_gmr_ids = 731 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 732 dev_priv->max_gmr_pages = 733 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 734 dev_priv->memory_size = 735 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 736 dev_priv->memory_size -= dev_priv->vram_size; 737 } else { 738 /* 739 * An arbitrary limit of 512MiB on surface 740 * memory. But all HWV8 hardware supports GMR2. 741 */ 742 dev_priv->memory_size = 512*1024*1024; 743 } 744 dev_priv->max_mob_pages = 0; 745 dev_priv->max_mob_size = 0; 746 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 747 uint64_t mem_size; 748 749 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 750 mem_size = vmw_read(dev_priv, 751 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 752 else 753 mem_size = 754 vmw_read(dev_priv, 755 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 756 757 /* 758 * Workaround for low memory 2D VMs to compensate for the 759 * allocation taken by fbdev 760 */ 761 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 762 mem_size *= 3; 763 764 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 765 dev_priv->prim_bb_mem = 766 vmw_read(dev_priv, 767 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 768 dev_priv->max_mob_size = 769 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 770 dev_priv->stdu_max_width = 771 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 772 dev_priv->stdu_max_height = 773 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 774 775 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 776 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 777 dev_priv->texture_max_width = vmw_read(dev_priv, 778 SVGA_REG_DEV_CAP); 779 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 780 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 781 dev_priv->texture_max_height = vmw_read(dev_priv, 782 SVGA_REG_DEV_CAP); 783 } else { 784 dev_priv->texture_max_width = 8192; 785 dev_priv->texture_max_height = 8192; 786 dev_priv->prim_bb_mem = dev_priv->vram_size; 787 } 788 789 vmw_print_capabilities(dev_priv->capabilities); 790 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 791 vmw_print_capabilities2(dev_priv->capabilities2); 792 793 ret = vmw_dma_masks(dev_priv); 794 if (unlikely(ret != 0)) 795 goto out_err0; 796 797 dma_set_max_seg_size(dev->dev, U32_MAX); 798 799 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 800 DRM_INFO("Max GMR ids is %u\n", 801 (unsigned)dev_priv->max_gmr_ids); 802 DRM_INFO("Max number of GMR pages is %u\n", 803 (unsigned)dev_priv->max_gmr_pages); 804 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 805 (unsigned)dev_priv->memory_size / 1024); 806 } 807 DRM_INFO("Maximum display memory size is %u kiB\n", 808 dev_priv->prim_bb_mem / 1024); 809 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 810 dev_priv->vram_start, dev_priv->vram_size / 1024); 811 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 812 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 813 814 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 815 dev_priv->mmio_size, MEMREMAP_WB); 816 817 if (unlikely(dev_priv->mmio_virt == NULL)) { 818 ret = -ENOMEM; 819 DRM_ERROR("Failed mapping MMIO.\n"); 820 goto out_err0; 821 } 822 823 /* Need mmio memory to check for fifo pitchlock cap. */ 824 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 825 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 826 !vmw_fifo_have_pitchlock(dev_priv)) { 827 ret = -ENOSYS; 828 DRM_ERROR("Hardware has no pitchlock\n"); 829 goto out_err4; 830 } 831 832 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 833 &vmw_prime_dmabuf_ops); 834 835 if (unlikely(dev_priv->tdev == NULL)) { 836 DRM_ERROR("Unable to initialize TTM object management.\n"); 837 ret = -ENOMEM; 838 goto out_err4; 839 } 840 841 dev->dev_private = dev_priv; 842 843 ret = pci_request_regions(pdev, "vmwgfx probe"); 844 dev_priv->stealth = (ret != 0); 845 if (dev_priv->stealth) { 846 /** 847 * Request at least the mmio PCI resource. 848 */ 849 850 DRM_INFO("It appears like vesafb is loaded. " 851 "Ignore above error if any.\n"); 852 ret = pci_request_region(pdev, 2, "vmwgfx stealth probe"); 853 if (unlikely(ret != 0)) { 854 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 855 goto out_no_device; 856 } 857 } 858 859 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 860 ret = vmw_irq_install(dev, pdev->irq); 861 if (ret != 0) { 862 DRM_ERROR("Failed installing irq: %d\n", ret); 863 goto out_no_irq; 864 } 865 } 866 867 dev_priv->fman = vmw_fence_manager_init(dev_priv); 868 if (unlikely(dev_priv->fman == NULL)) { 869 ret = -ENOMEM; 870 goto out_no_fman; 871 } 872 873 drm_vma_offset_manager_init(&dev_priv->vma_manager, 874 DRM_FILE_PAGE_OFFSET_START, 875 DRM_FILE_PAGE_OFFSET_SIZE); 876 ret = ttm_bo_device_init(&dev_priv->bdev, &vmw_bo_driver, 877 dev_priv->dev->dev, 878 dev->anon_inode->i_mapping, 879 &dev_priv->vma_manager, 880 dev_priv->map_mode == vmw_dma_alloc_coherent, 881 false); 882 if (unlikely(ret != 0)) { 883 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 884 goto out_no_bdev; 885 } 886 887 /* 888 * Enable VRAM, but initially don't use it until SVGA is enabled and 889 * unhidden. 890 */ 891 892 ret = vmw_vram_manager_init(dev_priv); 893 if (unlikely(ret != 0)) { 894 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 895 goto out_no_vram; 896 } 897 898 /* 899 * "Guest Memory Regions" is an aperture like feature with 900 * one slot per bo. There is an upper limit of the number of 901 * slots as well as the bo size. 902 */ 903 dev_priv->has_gmr = true; 904 /* TODO: This is most likely not correct */ 905 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 906 refuse_dma || 907 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 908 DRM_INFO("No GMR memory available. " 909 "Graphics memory resources are very limited.\n"); 910 dev_priv->has_gmr = false; 911 } 912 913 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 914 dev_priv->has_mob = true; 915 916 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 917 DRM_INFO("No MOB memory available. " 918 "3D will be disabled.\n"); 919 dev_priv->has_mob = false; 920 } 921 } 922 923 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 924 spin_lock(&dev_priv->cap_lock); 925 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 926 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 927 dev_priv->sm_type = VMW_SM_4; 928 spin_unlock(&dev_priv->cap_lock); 929 } 930 931 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 932 933 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 934 if (has_sm4_context(dev_priv) && 935 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 936 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM41); 937 938 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 939 dev_priv->sm_type = VMW_SM_4_1; 940 941 if (has_sm4_1_context(dev_priv) && 942 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 943 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM5); 944 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 945 dev_priv->sm_type = VMW_SM_5; 946 } 947 } 948 949 ret = vmw_kms_init(dev_priv); 950 if (unlikely(ret != 0)) 951 goto out_no_kms; 952 vmw_overlay_init(dev_priv); 953 954 ret = vmw_request_device(dev_priv); 955 if (ret) 956 goto out_no_fifo; 957 958 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 959 ? "yes." : "no."); 960 if (dev_priv->sm_type == VMW_SM_5) 961 DRM_INFO("SM5 support available.\n"); 962 if (dev_priv->sm_type == VMW_SM_4_1) 963 DRM_INFO("SM4_1 support available.\n"); 964 if (dev_priv->sm_type == VMW_SM_4) 965 DRM_INFO("SM4 support available.\n"); 966 967 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 968 VMWGFX_REPO, VMWGFX_GIT_VERSION); 969 vmw_host_log(host_log); 970 971 memset(host_log, 0, sizeof(host_log)); 972 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 973 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 974 VMWGFX_DRIVER_PATCHLEVEL); 975 vmw_host_log(host_log); 976 977 if (dev_priv->enable_fb) { 978 vmw_fifo_resource_inc(dev_priv); 979 vmw_svga_enable(dev_priv); 980 vmw_fb_init(dev_priv); 981 } 982 983 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 984 register_pm_notifier(&dev_priv->pm_nb); 985 986 return 0; 987 988 out_no_fifo: 989 vmw_overlay_close(dev_priv); 990 vmw_kms_close(dev_priv); 991 out_no_kms: 992 if (dev_priv->has_mob) 993 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 994 if (dev_priv->has_gmr) 995 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 996 vmw_vram_manager_fini(dev_priv); 997 out_no_vram: 998 (void)ttm_bo_device_release(&dev_priv->bdev); 999 out_no_bdev: 1000 vmw_fence_manager_takedown(dev_priv->fman); 1001 out_no_fman: 1002 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1003 vmw_irq_uninstall(dev_priv->dev); 1004 out_no_irq: 1005 if (dev_priv->stealth) 1006 pci_release_region(pdev, 2); 1007 else 1008 pci_release_regions(pdev); 1009 out_no_device: 1010 ttm_object_device_release(&dev_priv->tdev); 1011 out_err4: 1012 memunmap(dev_priv->mmio_virt); 1013 out_err0: 1014 for (i = vmw_res_context; i < vmw_res_max; ++i) 1015 idr_destroy(&dev_priv->res_idr[i]); 1016 1017 if (dev_priv->ctx.staged_bindings) 1018 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1019 kfree(dev_priv); 1020 return ret; 1021 } 1022 1023 static void vmw_driver_unload(struct drm_device *dev) 1024 { 1025 struct vmw_private *dev_priv = vmw_priv(dev); 1026 struct pci_dev *pdev = to_pci_dev(dev->dev); 1027 enum vmw_res_type i; 1028 1029 unregister_pm_notifier(&dev_priv->pm_nb); 1030 1031 if (dev_priv->ctx.res_ht_initialized) 1032 drm_ht_remove(&dev_priv->ctx.res_ht); 1033 vfree(dev_priv->ctx.cmd_bounce); 1034 if (dev_priv->enable_fb) { 1035 vmw_fb_off(dev_priv); 1036 vmw_fb_close(dev_priv); 1037 vmw_fifo_resource_dec(dev_priv); 1038 vmw_svga_disable(dev_priv); 1039 } 1040 1041 vmw_kms_close(dev_priv); 1042 vmw_overlay_close(dev_priv); 1043 1044 if (dev_priv->has_gmr) 1045 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1046 1047 vmw_release_device_early(dev_priv); 1048 if (dev_priv->has_mob) 1049 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1050 vmw_vram_manager_fini(dev_priv); 1051 (void) ttm_bo_device_release(&dev_priv->bdev); 1052 drm_vma_offset_manager_destroy(&dev_priv->vma_manager); 1053 vmw_release_device_late(dev_priv); 1054 vmw_fence_manager_takedown(dev_priv->fman); 1055 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1056 vmw_irq_uninstall(dev_priv->dev); 1057 if (dev_priv->stealth) 1058 pci_release_region(pdev, 2); 1059 else 1060 pci_release_regions(pdev); 1061 1062 ttm_object_device_release(&dev_priv->tdev); 1063 memunmap(dev_priv->mmio_virt); 1064 if (dev_priv->ctx.staged_bindings) 1065 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1066 1067 for (i = vmw_res_context; i < vmw_res_max; ++i) 1068 idr_destroy(&dev_priv->res_idr[i]); 1069 1070 kfree(dev_priv); 1071 } 1072 1073 static void vmw_postclose(struct drm_device *dev, 1074 struct drm_file *file_priv) 1075 { 1076 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1077 1078 ttm_object_file_release(&vmw_fp->tfile); 1079 kfree(vmw_fp); 1080 } 1081 1082 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1083 { 1084 struct vmw_private *dev_priv = vmw_priv(dev); 1085 struct vmw_fpriv *vmw_fp; 1086 int ret = -ENOMEM; 1087 1088 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1089 if (unlikely(!vmw_fp)) 1090 return ret; 1091 1092 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1093 if (unlikely(vmw_fp->tfile == NULL)) 1094 goto out_no_tfile; 1095 1096 file_priv->driver_priv = vmw_fp; 1097 1098 return 0; 1099 1100 out_no_tfile: 1101 kfree(vmw_fp); 1102 return ret; 1103 } 1104 1105 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1106 unsigned long arg, 1107 long (*ioctl_func)(struct file *, unsigned int, 1108 unsigned long)) 1109 { 1110 struct drm_file *file_priv = filp->private_data; 1111 struct drm_device *dev = file_priv->minor->dev; 1112 unsigned int nr = DRM_IOCTL_NR(cmd); 1113 unsigned int flags; 1114 1115 /* 1116 * Do extra checking on driver private ioctls. 1117 */ 1118 1119 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1120 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1121 const struct drm_ioctl_desc *ioctl = 1122 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1123 1124 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1125 return ioctl_func(filp, cmd, arg); 1126 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1127 if (!drm_is_current_master(file_priv) && 1128 !capable(CAP_SYS_ADMIN)) 1129 return -EACCES; 1130 } 1131 1132 if (unlikely(ioctl->cmd != cmd)) 1133 goto out_io_encoding; 1134 1135 flags = ioctl->flags; 1136 } else if (!drm_ioctl_flags(nr, &flags)) 1137 return -EINVAL; 1138 1139 return ioctl_func(filp, cmd, arg); 1140 1141 out_io_encoding: 1142 DRM_ERROR("Invalid command format, ioctl %d\n", 1143 nr - DRM_COMMAND_BASE); 1144 1145 return -EINVAL; 1146 } 1147 1148 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1149 unsigned long arg) 1150 { 1151 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1152 } 1153 1154 #ifdef CONFIG_COMPAT 1155 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1156 unsigned long arg) 1157 { 1158 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1159 } 1160 #endif 1161 1162 static void vmw_master_set(struct drm_device *dev, 1163 struct drm_file *file_priv, 1164 bool from_open) 1165 { 1166 /* 1167 * Inform a new master that the layout may have changed while 1168 * it was gone. 1169 */ 1170 if (!from_open) 1171 drm_sysfs_hotplug_event(dev); 1172 } 1173 1174 static void vmw_master_drop(struct drm_device *dev, 1175 struct drm_file *file_priv) 1176 { 1177 struct vmw_private *dev_priv = vmw_priv(dev); 1178 1179 vmw_kms_legacy_hotspot_clear(dev_priv); 1180 if (!dev_priv->enable_fb) 1181 vmw_svga_disable(dev_priv); 1182 } 1183 1184 /** 1185 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1186 * 1187 * @dev_priv: Pointer to device private struct. 1188 * Needs the reservation sem to be held in non-exclusive mode. 1189 */ 1190 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1191 { 1192 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1193 1194 spin_lock(&dev_priv->svga_lock); 1195 if (!ttm_resource_manager_used(man)) { 1196 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1197 ttm_resource_manager_set_used(man, true); 1198 } 1199 spin_unlock(&dev_priv->svga_lock); 1200 } 1201 1202 /** 1203 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1204 * 1205 * @dev_priv: Pointer to device private struct. 1206 */ 1207 void vmw_svga_enable(struct vmw_private *dev_priv) 1208 { 1209 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1210 __vmw_svga_enable(dev_priv); 1211 ttm_read_unlock(&dev_priv->reservation_sem); 1212 } 1213 1214 /** 1215 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1216 * 1217 * @dev_priv: Pointer to device private struct. 1218 * Needs the reservation sem to be held in exclusive mode. 1219 * Will not empty VRAM. VRAM must be emptied by caller. 1220 */ 1221 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1222 { 1223 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1224 1225 spin_lock(&dev_priv->svga_lock); 1226 if (ttm_resource_manager_used(man)) { 1227 ttm_resource_manager_set_used(man, false); 1228 vmw_write(dev_priv, SVGA_REG_ENABLE, 1229 SVGA_REG_ENABLE_HIDE | 1230 SVGA_REG_ENABLE_ENABLE); 1231 } 1232 spin_unlock(&dev_priv->svga_lock); 1233 } 1234 1235 /** 1236 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1237 * running. 1238 * 1239 * @dev_priv: Pointer to device private struct. 1240 * Will empty VRAM. 1241 */ 1242 void vmw_svga_disable(struct vmw_private *dev_priv) 1243 { 1244 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1245 /* 1246 * Disabling SVGA will turn off device modesetting capabilities, so 1247 * notify KMS about that so that it doesn't cache atomic state that 1248 * isn't valid anymore, for example crtcs turned on. 1249 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1250 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1251 * end up with lock order reversal. Thus, a master may actually perform 1252 * a new modeset just after we call vmw_kms_lost_device() and race with 1253 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1254 * to be inconsistent with the device, causing modesetting problems. 1255 * 1256 */ 1257 vmw_kms_lost_device(dev_priv->dev); 1258 ttm_write_lock(&dev_priv->reservation_sem, false); 1259 spin_lock(&dev_priv->svga_lock); 1260 if (ttm_resource_manager_used(man)) { 1261 ttm_resource_manager_set_used(man, false); 1262 spin_unlock(&dev_priv->svga_lock); 1263 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1264 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1265 vmw_write(dev_priv, SVGA_REG_ENABLE, 1266 SVGA_REG_ENABLE_HIDE | 1267 SVGA_REG_ENABLE_ENABLE); 1268 } else 1269 spin_unlock(&dev_priv->svga_lock); 1270 ttm_write_unlock(&dev_priv->reservation_sem); 1271 } 1272 1273 static void vmw_remove(struct pci_dev *pdev) 1274 { 1275 struct drm_device *dev = pci_get_drvdata(pdev); 1276 1277 drm_dev_unregister(dev); 1278 vmw_driver_unload(dev); 1279 drm_dev_put(dev); 1280 pci_disable_device(pdev); 1281 } 1282 1283 static unsigned long 1284 vmw_get_unmapped_area(struct file *file, unsigned long uaddr, 1285 unsigned long len, unsigned long pgoff, 1286 unsigned long flags) 1287 { 1288 struct drm_file *file_priv = file->private_data; 1289 struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev); 1290 1291 return drm_get_unmapped_area(file, uaddr, len, pgoff, flags, 1292 &dev_priv->vma_manager); 1293 } 1294 1295 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1296 void *ptr) 1297 { 1298 struct vmw_private *dev_priv = 1299 container_of(nb, struct vmw_private, pm_nb); 1300 1301 switch (val) { 1302 case PM_HIBERNATION_PREPARE: 1303 /* 1304 * Take the reservation sem in write mode, which will make sure 1305 * there are no other processes holding a buffer object 1306 * reservation, meaning we should be able to evict all buffer 1307 * objects if needed. 1308 * Once user-space processes have been frozen, we can release 1309 * the lock again. 1310 */ 1311 ttm_suspend_lock(&dev_priv->reservation_sem); 1312 dev_priv->suspend_locked = true; 1313 break; 1314 case PM_POST_HIBERNATION: 1315 case PM_POST_RESTORE: 1316 if (READ_ONCE(dev_priv->suspend_locked)) { 1317 dev_priv->suspend_locked = false; 1318 ttm_suspend_unlock(&dev_priv->reservation_sem); 1319 } 1320 break; 1321 default: 1322 break; 1323 } 1324 return 0; 1325 } 1326 1327 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1328 { 1329 struct drm_device *dev = pci_get_drvdata(pdev); 1330 struct vmw_private *dev_priv = vmw_priv(dev); 1331 1332 if (dev_priv->refuse_hibernation) 1333 return -EBUSY; 1334 1335 pci_save_state(pdev); 1336 pci_disable_device(pdev); 1337 pci_set_power_state(pdev, PCI_D3hot); 1338 return 0; 1339 } 1340 1341 static int vmw_pci_resume(struct pci_dev *pdev) 1342 { 1343 pci_set_power_state(pdev, PCI_D0); 1344 pci_restore_state(pdev); 1345 return pci_enable_device(pdev); 1346 } 1347 1348 static int vmw_pm_suspend(struct device *kdev) 1349 { 1350 struct pci_dev *pdev = to_pci_dev(kdev); 1351 struct pm_message dummy; 1352 1353 dummy.event = 0; 1354 1355 return vmw_pci_suspend(pdev, dummy); 1356 } 1357 1358 static int vmw_pm_resume(struct device *kdev) 1359 { 1360 struct pci_dev *pdev = to_pci_dev(kdev); 1361 1362 return vmw_pci_resume(pdev); 1363 } 1364 1365 static int vmw_pm_freeze(struct device *kdev) 1366 { 1367 struct pci_dev *pdev = to_pci_dev(kdev); 1368 struct drm_device *dev = pci_get_drvdata(pdev); 1369 struct vmw_private *dev_priv = vmw_priv(dev); 1370 struct ttm_operation_ctx ctx = { 1371 .interruptible = false, 1372 .no_wait_gpu = false 1373 }; 1374 int ret; 1375 1376 /* 1377 * Unlock for vmw_kms_suspend. 1378 * No user-space processes should be running now. 1379 */ 1380 ttm_suspend_unlock(&dev_priv->reservation_sem); 1381 ret = vmw_kms_suspend(dev_priv->dev); 1382 if (ret) { 1383 ttm_suspend_lock(&dev_priv->reservation_sem); 1384 DRM_ERROR("Failed to freeze modesetting.\n"); 1385 return ret; 1386 } 1387 if (dev_priv->enable_fb) 1388 vmw_fb_off(dev_priv); 1389 1390 ttm_suspend_lock(&dev_priv->reservation_sem); 1391 vmw_execbuf_release_pinned_bo(dev_priv); 1392 vmw_resource_evict_all(dev_priv); 1393 vmw_release_device_early(dev_priv); 1394 while (ttm_bo_swapout(&ctx) == 0); 1395 if (dev_priv->enable_fb) 1396 vmw_fifo_resource_dec(dev_priv); 1397 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1398 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1399 if (dev_priv->enable_fb) 1400 vmw_fifo_resource_inc(dev_priv); 1401 WARN_ON(vmw_request_device_late(dev_priv)); 1402 dev_priv->suspend_locked = false; 1403 ttm_suspend_unlock(&dev_priv->reservation_sem); 1404 if (dev_priv->suspend_state) 1405 vmw_kms_resume(dev); 1406 if (dev_priv->enable_fb) 1407 vmw_fb_on(dev_priv); 1408 return -EBUSY; 1409 } 1410 1411 vmw_fence_fifo_down(dev_priv->fman); 1412 __vmw_svga_disable(dev_priv); 1413 1414 vmw_release_device_late(dev_priv); 1415 return 0; 1416 } 1417 1418 static int vmw_pm_restore(struct device *kdev) 1419 { 1420 struct pci_dev *pdev = to_pci_dev(kdev); 1421 struct drm_device *dev = pci_get_drvdata(pdev); 1422 struct vmw_private *dev_priv = vmw_priv(dev); 1423 int ret; 1424 1425 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1426 (void) vmw_read(dev_priv, SVGA_REG_ID); 1427 1428 if (dev_priv->enable_fb) 1429 vmw_fifo_resource_inc(dev_priv); 1430 1431 ret = vmw_request_device(dev_priv); 1432 if (ret) 1433 return ret; 1434 1435 if (dev_priv->enable_fb) 1436 __vmw_svga_enable(dev_priv); 1437 1438 vmw_fence_fifo_up(dev_priv->fman); 1439 dev_priv->suspend_locked = false; 1440 ttm_suspend_unlock(&dev_priv->reservation_sem); 1441 if (dev_priv->suspend_state) 1442 vmw_kms_resume(dev_priv->dev); 1443 1444 if (dev_priv->enable_fb) 1445 vmw_fb_on(dev_priv); 1446 1447 return 0; 1448 } 1449 1450 static const struct dev_pm_ops vmw_pm_ops = { 1451 .freeze = vmw_pm_freeze, 1452 .thaw = vmw_pm_restore, 1453 .restore = vmw_pm_restore, 1454 .suspend = vmw_pm_suspend, 1455 .resume = vmw_pm_resume, 1456 }; 1457 1458 static const struct file_operations vmwgfx_driver_fops = { 1459 .owner = THIS_MODULE, 1460 .open = drm_open, 1461 .release = drm_release, 1462 .unlocked_ioctl = vmw_unlocked_ioctl, 1463 .mmap = vmw_mmap, 1464 .poll = vmw_fops_poll, 1465 .read = vmw_fops_read, 1466 #if defined(CONFIG_COMPAT) 1467 .compat_ioctl = vmw_compat_ioctl, 1468 #endif 1469 .llseek = noop_llseek, 1470 .get_unmapped_area = vmw_get_unmapped_area, 1471 }; 1472 1473 static const struct drm_driver driver = { 1474 .driver_features = 1475 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC, 1476 .ioctls = vmw_ioctls, 1477 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1478 .master_set = vmw_master_set, 1479 .master_drop = vmw_master_drop, 1480 .open = vmw_driver_open, 1481 .postclose = vmw_postclose, 1482 1483 .dumb_create = vmw_dumb_create, 1484 .dumb_map_offset = vmw_dumb_map_offset, 1485 .dumb_destroy = vmw_dumb_destroy, 1486 1487 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1488 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1489 1490 .fops = &vmwgfx_driver_fops, 1491 .name = VMWGFX_DRIVER_NAME, 1492 .desc = VMWGFX_DRIVER_DESC, 1493 .date = VMWGFX_DRIVER_DATE, 1494 .major = VMWGFX_DRIVER_MAJOR, 1495 .minor = VMWGFX_DRIVER_MINOR, 1496 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1497 }; 1498 1499 static struct pci_driver vmw_pci_driver = { 1500 .name = VMWGFX_DRIVER_NAME, 1501 .id_table = vmw_pci_id_list, 1502 .probe = vmw_probe, 1503 .remove = vmw_remove, 1504 .driver = { 1505 .pm = &vmw_pm_ops 1506 } 1507 }; 1508 1509 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1510 { 1511 struct drm_device *dev; 1512 int ret; 1513 1514 ret = pci_enable_device(pdev); 1515 if (ret) 1516 return ret; 1517 1518 dev = drm_dev_alloc(&driver, &pdev->dev); 1519 if (IS_ERR(dev)) { 1520 ret = PTR_ERR(dev); 1521 goto err_pci_disable_device; 1522 } 1523 1524 pci_set_drvdata(pdev, dev); 1525 1526 ret = vmw_driver_load(dev, ent->driver_data); 1527 if (ret) 1528 goto err_drm_dev_put; 1529 1530 ret = drm_dev_register(dev, ent->driver_data); 1531 if (ret) 1532 goto err_vmw_driver_unload; 1533 1534 return 0; 1535 1536 err_vmw_driver_unload: 1537 vmw_driver_unload(dev); 1538 err_drm_dev_put: 1539 drm_dev_put(dev); 1540 err_pci_disable_device: 1541 pci_disable_device(pdev); 1542 return ret; 1543 } 1544 1545 static int __init vmwgfx_init(void) 1546 { 1547 int ret; 1548 1549 if (vgacon_text_force()) 1550 return -EINVAL; 1551 1552 ret = pci_register_driver(&vmw_pci_driver); 1553 if (ret) 1554 DRM_ERROR("Failed initializing DRM.\n"); 1555 return ret; 1556 } 1557 1558 static void __exit vmwgfx_exit(void) 1559 { 1560 pci_unregister_driver(&vmw_pci_driver); 1561 } 1562 1563 module_init(vmwgfx_init); 1564 module_exit(vmwgfx_exit); 1565 1566 MODULE_AUTHOR("VMware Inc. and others"); 1567 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1568 MODULE_LICENSE("GPL and additional rights"); 1569 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1570 __stringify(VMWGFX_DRIVER_MINOR) "." 1571 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1572 "0"); 1573