1 /************************************************************************** 2 * 3 * Copyright © 2009-2016 VMware, Inc., Palo Alto, CA., USA 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 #include <linux/module.h> 28 #include <linux/console.h> 29 30 #include <drm/drmP.h> 31 #include "vmwgfx_drv.h" 32 #include "vmwgfx_binding.h" 33 #include <drm/ttm/ttm_placement.h> 34 #include <drm/ttm/ttm_bo_driver.h> 35 #include <drm/ttm/ttm_object.h> 36 #include <drm/ttm/ttm_module.h> 37 #include <linux/dma_remapping.h> 38 39 #define VMWGFX_DRIVER_NAME "vmwgfx" 40 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 41 #define VMWGFX_CHIP_SVGAII 0 42 #define VMW_FB_RESERVATION 0 43 44 #define VMW_MIN_INITIAL_WIDTH 800 45 #define VMW_MIN_INITIAL_HEIGHT 600 46 47 #ifndef VMWGFX_GIT_VERSION 48 #define VMWGFX_GIT_VERSION "Unknown" 49 #endif 50 51 #define VMWGFX_REPO "In Tree" 52 53 54 /** 55 * Fully encoded drm commands. Might move to vmw_drm.h 56 */ 57 58 #define DRM_IOCTL_VMW_GET_PARAM \ 59 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 60 struct drm_vmw_getparam_arg) 61 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 62 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 63 union drm_vmw_alloc_dmabuf_arg) 64 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 65 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 66 struct drm_vmw_unref_dmabuf_arg) 67 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 68 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 69 struct drm_vmw_cursor_bypass_arg) 70 71 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 72 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 73 struct drm_vmw_control_stream_arg) 74 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 75 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 76 struct drm_vmw_stream_arg) 77 #define DRM_IOCTL_VMW_UNREF_STREAM \ 78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 79 struct drm_vmw_stream_arg) 80 81 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 82 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 83 struct drm_vmw_context_arg) 84 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 86 struct drm_vmw_context_arg) 87 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 88 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 89 union drm_vmw_surface_create_arg) 90 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 92 struct drm_vmw_surface_arg) 93 #define DRM_IOCTL_VMW_REF_SURFACE \ 94 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 95 union drm_vmw_surface_reference_arg) 96 #define DRM_IOCTL_VMW_EXECBUF \ 97 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 98 struct drm_vmw_execbuf_arg) 99 #define DRM_IOCTL_VMW_GET_3D_CAP \ 100 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 101 struct drm_vmw_get_3d_cap_arg) 102 #define DRM_IOCTL_VMW_FENCE_WAIT \ 103 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 104 struct drm_vmw_fence_wait_arg) 105 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 106 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 107 struct drm_vmw_fence_signaled_arg) 108 #define DRM_IOCTL_VMW_FENCE_UNREF \ 109 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 110 struct drm_vmw_fence_arg) 111 #define DRM_IOCTL_VMW_FENCE_EVENT \ 112 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 113 struct drm_vmw_fence_event_arg) 114 #define DRM_IOCTL_VMW_PRESENT \ 115 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 116 struct drm_vmw_present_arg) 117 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 118 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 119 struct drm_vmw_present_readback_arg) 120 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 122 struct drm_vmw_update_layout_arg) 123 #define DRM_IOCTL_VMW_CREATE_SHADER \ 124 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 125 struct drm_vmw_shader_create_arg) 126 #define DRM_IOCTL_VMW_UNREF_SHADER \ 127 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 128 struct drm_vmw_shader_arg) 129 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 130 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 131 union drm_vmw_gb_surface_create_arg) 132 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 133 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 134 union drm_vmw_gb_surface_reference_arg) 135 #define DRM_IOCTL_VMW_SYNCCPU \ 136 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 137 struct drm_vmw_synccpu_arg) 138 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 139 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 140 struct drm_vmw_context_arg) 141 142 /** 143 * The core DRM version of this macro doesn't account for 144 * DRM_COMMAND_BASE. 145 */ 146 147 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 148 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 149 150 /** 151 * Ioctl definitions. 152 */ 153 154 static const struct drm_ioctl_desc vmw_ioctls[] = { 155 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 156 DRM_AUTH | DRM_RENDER_ALLOW), 157 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, 158 DRM_AUTH | DRM_RENDER_ALLOW), 159 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, 160 DRM_RENDER_ALLOW), 161 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 162 vmw_kms_cursor_bypass_ioctl, 163 DRM_MASTER | DRM_CONTROL_ALLOW), 164 165 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 166 DRM_MASTER | DRM_CONTROL_ALLOW), 167 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 168 DRM_MASTER | DRM_CONTROL_ALLOW), 169 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 170 DRM_MASTER | DRM_CONTROL_ALLOW), 171 172 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 173 DRM_AUTH | DRM_RENDER_ALLOW), 174 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 175 DRM_RENDER_ALLOW), 176 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 177 DRM_AUTH | DRM_RENDER_ALLOW), 178 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 179 DRM_RENDER_ALLOW), 180 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 181 DRM_AUTH | DRM_RENDER_ALLOW), 182 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | 183 DRM_RENDER_ALLOW), 184 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 185 DRM_RENDER_ALLOW), 186 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 187 vmw_fence_obj_signaled_ioctl, 188 DRM_RENDER_ALLOW), 189 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 190 DRM_RENDER_ALLOW), 191 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 192 DRM_AUTH | DRM_RENDER_ALLOW), 193 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 194 DRM_AUTH | DRM_RENDER_ALLOW), 195 196 /* these allow direct access to the framebuffers mark as master only */ 197 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 198 DRM_MASTER | DRM_AUTH), 199 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 200 vmw_present_readback_ioctl, 201 DRM_MASTER | DRM_AUTH), 202 /* 203 * The permissions of the below ioctl are overridden in 204 * vmw_generic_ioctl(). We require either 205 * DRM_MASTER or capable(CAP_SYS_ADMIN). 206 */ 207 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 208 vmw_kms_update_layout_ioctl, 209 DRM_RENDER_ALLOW), 210 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 211 vmw_shader_define_ioctl, 212 DRM_AUTH | DRM_RENDER_ALLOW), 213 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 214 vmw_shader_destroy_ioctl, 215 DRM_RENDER_ALLOW), 216 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 217 vmw_gb_surface_define_ioctl, 218 DRM_AUTH | DRM_RENDER_ALLOW), 219 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 220 vmw_gb_surface_reference_ioctl, 221 DRM_AUTH | DRM_RENDER_ALLOW), 222 VMW_IOCTL_DEF(VMW_SYNCCPU, 223 vmw_user_dmabuf_synccpu_ioctl, 224 DRM_RENDER_ALLOW), 225 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 226 vmw_extended_context_define_ioctl, 227 DRM_AUTH | DRM_RENDER_ALLOW), 228 }; 229 230 static const struct pci_device_id vmw_pci_id_list[] = { 231 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 232 {0, 0, 0} 233 }; 234 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 235 236 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 237 static int vmw_force_iommu; 238 static int vmw_restrict_iommu; 239 static int vmw_force_coherent; 240 static int vmw_restrict_dma_mask; 241 static int vmw_assume_16bpp; 242 243 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 244 static void vmw_master_init(struct vmw_master *); 245 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 246 void *ptr); 247 248 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 249 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 250 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 251 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 252 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 253 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 254 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 255 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 256 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 257 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 258 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 259 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 260 261 262 static void vmw_print_capabilities(uint32_t capabilities) 263 { 264 DRM_INFO("Capabilities:\n"); 265 if (capabilities & SVGA_CAP_RECT_COPY) 266 DRM_INFO(" Rect copy.\n"); 267 if (capabilities & SVGA_CAP_CURSOR) 268 DRM_INFO(" Cursor.\n"); 269 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 270 DRM_INFO(" Cursor bypass.\n"); 271 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 272 DRM_INFO(" Cursor bypass 2.\n"); 273 if (capabilities & SVGA_CAP_8BIT_EMULATION) 274 DRM_INFO(" 8bit emulation.\n"); 275 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 276 DRM_INFO(" Alpha cursor.\n"); 277 if (capabilities & SVGA_CAP_3D) 278 DRM_INFO(" 3D.\n"); 279 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 280 DRM_INFO(" Extended Fifo.\n"); 281 if (capabilities & SVGA_CAP_MULTIMON) 282 DRM_INFO(" Multimon.\n"); 283 if (capabilities & SVGA_CAP_PITCHLOCK) 284 DRM_INFO(" Pitchlock.\n"); 285 if (capabilities & SVGA_CAP_IRQMASK) 286 DRM_INFO(" Irq mask.\n"); 287 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 288 DRM_INFO(" Display Topology.\n"); 289 if (capabilities & SVGA_CAP_GMR) 290 DRM_INFO(" GMR.\n"); 291 if (capabilities & SVGA_CAP_TRACES) 292 DRM_INFO(" Traces.\n"); 293 if (capabilities & SVGA_CAP_GMR2) 294 DRM_INFO(" GMR2.\n"); 295 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 296 DRM_INFO(" Screen Object 2.\n"); 297 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 298 DRM_INFO(" Command Buffers.\n"); 299 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 300 DRM_INFO(" Command Buffers 2.\n"); 301 if (capabilities & SVGA_CAP_GBOBJECTS) 302 DRM_INFO(" Guest Backed Resources.\n"); 303 if (capabilities & SVGA_CAP_DX) 304 DRM_INFO(" DX Features.\n"); 305 } 306 307 /** 308 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 309 * 310 * @dev_priv: A device private structure. 311 * 312 * This function creates a small buffer object that holds the query 313 * result for dummy queries emitted as query barriers. 314 * The function will then map the first page and initialize a pending 315 * occlusion query result structure, Finally it will unmap the buffer. 316 * No interruptible waits are done within this function. 317 * 318 * Returns an error if bo creation or initialization fails. 319 */ 320 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 321 { 322 int ret; 323 struct vmw_dma_buffer *vbo; 324 struct ttm_bo_kmap_obj map; 325 volatile SVGA3dQueryResult *result; 326 bool dummy; 327 328 /* 329 * Create the vbo as pinned, so that a tryreserve will 330 * immediately succeed. This is because we're the only 331 * user of the bo currently. 332 */ 333 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 334 if (!vbo) 335 return -ENOMEM; 336 337 ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE, 338 &vmw_sys_ne_placement, false, 339 &vmw_dmabuf_bo_free); 340 if (unlikely(ret != 0)) 341 return ret; 342 343 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 344 BUG_ON(ret != 0); 345 vmw_bo_pin_reserved(vbo, true); 346 347 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 348 if (likely(ret == 0)) { 349 result = ttm_kmap_obj_virtual(&map, &dummy); 350 result->totalSize = sizeof(*result); 351 result->state = SVGA3D_QUERYSTATE_PENDING; 352 result->result32 = 0xff; 353 ttm_bo_kunmap(&map); 354 } 355 vmw_bo_pin_reserved(vbo, false); 356 ttm_bo_unreserve(&vbo->base); 357 358 if (unlikely(ret != 0)) { 359 DRM_ERROR("Dummy query buffer map failed.\n"); 360 vmw_dmabuf_unreference(&vbo); 361 } else 362 dev_priv->dummy_query_bo = vbo; 363 364 return ret; 365 } 366 367 /** 368 * vmw_request_device_late - Perform late device setup 369 * 370 * @dev_priv: Pointer to device private. 371 * 372 * This function performs setup of otables and enables large command 373 * buffer submission. These tasks are split out to a separate function 374 * because it reverts vmw_release_device_early and is intended to be used 375 * by an error path in the hibernation code. 376 */ 377 static int vmw_request_device_late(struct vmw_private *dev_priv) 378 { 379 int ret; 380 381 if (dev_priv->has_mob) { 382 ret = vmw_otables_setup(dev_priv); 383 if (unlikely(ret != 0)) { 384 DRM_ERROR("Unable to initialize " 385 "guest Memory OBjects.\n"); 386 return ret; 387 } 388 } 389 390 if (dev_priv->cman) { 391 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 392 256*4096, 2*4096); 393 if (ret) { 394 struct vmw_cmdbuf_man *man = dev_priv->cman; 395 396 dev_priv->cman = NULL; 397 vmw_cmdbuf_man_destroy(man); 398 } 399 } 400 401 return 0; 402 } 403 404 static int vmw_request_device(struct vmw_private *dev_priv) 405 { 406 int ret; 407 408 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 409 if (unlikely(ret != 0)) { 410 DRM_ERROR("Unable to initialize FIFO.\n"); 411 return ret; 412 } 413 vmw_fence_fifo_up(dev_priv->fman); 414 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 415 if (IS_ERR(dev_priv->cman)) { 416 dev_priv->cman = NULL; 417 dev_priv->has_dx = false; 418 } 419 420 ret = vmw_request_device_late(dev_priv); 421 if (ret) 422 goto out_no_mob; 423 424 ret = vmw_dummy_query_bo_create(dev_priv); 425 if (unlikely(ret != 0)) 426 goto out_no_query_bo; 427 428 return 0; 429 430 out_no_query_bo: 431 if (dev_priv->cman) 432 vmw_cmdbuf_remove_pool(dev_priv->cman); 433 if (dev_priv->has_mob) { 434 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 435 vmw_otables_takedown(dev_priv); 436 } 437 if (dev_priv->cman) 438 vmw_cmdbuf_man_destroy(dev_priv->cman); 439 out_no_mob: 440 vmw_fence_fifo_down(dev_priv->fman); 441 vmw_fifo_release(dev_priv, &dev_priv->fifo); 442 return ret; 443 } 444 445 /** 446 * vmw_release_device_early - Early part of fifo takedown. 447 * 448 * @dev_priv: Pointer to device private struct. 449 * 450 * This is the first part of command submission takedown, to be called before 451 * buffer management is taken down. 452 */ 453 static void vmw_release_device_early(struct vmw_private *dev_priv) 454 { 455 /* 456 * Previous destructions should've released 457 * the pinned bo. 458 */ 459 460 BUG_ON(dev_priv->pinned_bo != NULL); 461 462 vmw_dmabuf_unreference(&dev_priv->dummy_query_bo); 463 if (dev_priv->cman) 464 vmw_cmdbuf_remove_pool(dev_priv->cman); 465 466 if (dev_priv->has_mob) { 467 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 468 vmw_otables_takedown(dev_priv); 469 } 470 } 471 472 /** 473 * vmw_release_device_late - Late part of fifo takedown. 474 * 475 * @dev_priv: Pointer to device private struct. 476 * 477 * This is the last part of the command submission takedown, to be called when 478 * command submission is no longer needed. It may wait on pending fences. 479 */ 480 static void vmw_release_device_late(struct vmw_private *dev_priv) 481 { 482 vmw_fence_fifo_down(dev_priv->fman); 483 if (dev_priv->cman) 484 vmw_cmdbuf_man_destroy(dev_priv->cman); 485 486 vmw_fifo_release(dev_priv, &dev_priv->fifo); 487 } 488 489 /** 490 * Sets the initial_[width|height] fields on the given vmw_private. 491 * 492 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 493 * clamping the value to fb_max_[width|height] fields and the 494 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 495 * If the values appear to be invalid, set them to 496 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 497 */ 498 static void vmw_get_initial_size(struct vmw_private *dev_priv) 499 { 500 uint32_t width; 501 uint32_t height; 502 503 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 504 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 505 506 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 507 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 508 509 if (width > dev_priv->fb_max_width || 510 height > dev_priv->fb_max_height) { 511 512 /* 513 * This is a host error and shouldn't occur. 514 */ 515 516 width = VMW_MIN_INITIAL_WIDTH; 517 height = VMW_MIN_INITIAL_HEIGHT; 518 } 519 520 dev_priv->initial_width = width; 521 dev_priv->initial_height = height; 522 } 523 524 /** 525 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 526 * system. 527 * 528 * @dev_priv: Pointer to a struct vmw_private 529 * 530 * This functions tries to determine the IOMMU setup and what actions 531 * need to be taken by the driver to make system pages visible to the 532 * device. 533 * If this function decides that DMA is not possible, it returns -EINVAL. 534 * The driver may then try to disable features of the device that require 535 * DMA. 536 */ 537 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 538 { 539 static const char *names[vmw_dma_map_max] = { 540 [vmw_dma_phys] = "Using physical TTM page addresses.", 541 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 542 [vmw_dma_map_populate] = "Keeping DMA mappings.", 543 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 544 #ifdef CONFIG_X86 545 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); 546 547 #ifdef CONFIG_INTEL_IOMMU 548 if (intel_iommu_enabled) { 549 dev_priv->map_mode = vmw_dma_map_populate; 550 goto out_fixup; 551 } 552 #endif 553 554 if (!(vmw_force_iommu || vmw_force_coherent)) { 555 dev_priv->map_mode = vmw_dma_phys; 556 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 557 return 0; 558 } 559 560 dev_priv->map_mode = vmw_dma_map_populate; 561 562 if (dma_ops->sync_single_for_cpu) 563 dev_priv->map_mode = vmw_dma_alloc_coherent; 564 #ifdef CONFIG_SWIOTLB 565 if (swiotlb_nr_tbl() == 0) 566 dev_priv->map_mode = vmw_dma_map_populate; 567 #endif 568 569 #ifdef CONFIG_INTEL_IOMMU 570 out_fixup: 571 #endif 572 if (dev_priv->map_mode == vmw_dma_map_populate && 573 vmw_restrict_iommu) 574 dev_priv->map_mode = vmw_dma_map_bind; 575 576 if (vmw_force_coherent) 577 dev_priv->map_mode = vmw_dma_alloc_coherent; 578 579 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) 580 /* 581 * No coherent page pool 582 */ 583 if (dev_priv->map_mode == vmw_dma_alloc_coherent) 584 return -EINVAL; 585 #endif 586 587 #else /* CONFIG_X86 */ 588 dev_priv->map_mode = vmw_dma_map_populate; 589 #endif /* CONFIG_X86 */ 590 591 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 592 593 return 0; 594 } 595 596 /** 597 * vmw_dma_masks - set required page- and dma masks 598 * 599 * @dev: Pointer to struct drm-device 600 * 601 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 602 * restriction also for 64-bit systems. 603 */ 604 #ifdef CONFIG_INTEL_IOMMU 605 static int vmw_dma_masks(struct vmw_private *dev_priv) 606 { 607 struct drm_device *dev = dev_priv->dev; 608 609 if (intel_iommu_enabled && 610 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 611 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 612 return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); 613 } 614 return 0; 615 } 616 #else 617 static int vmw_dma_masks(struct vmw_private *dev_priv) 618 { 619 return 0; 620 } 621 #endif 622 623 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 624 { 625 struct vmw_private *dev_priv; 626 int ret; 627 uint32_t svga_id; 628 enum vmw_res_type i; 629 bool refuse_dma = false; 630 char host_log[100] = {0}; 631 632 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 633 if (unlikely(!dev_priv)) { 634 DRM_ERROR("Failed allocating a device private struct.\n"); 635 return -ENOMEM; 636 } 637 638 pci_set_master(dev->pdev); 639 640 dev_priv->dev = dev; 641 dev_priv->vmw_chipset = chipset; 642 dev_priv->last_read_seqno = (uint32_t) -100; 643 mutex_init(&dev_priv->cmdbuf_mutex); 644 mutex_init(&dev_priv->release_mutex); 645 mutex_init(&dev_priv->binding_mutex); 646 mutex_init(&dev_priv->global_kms_state_mutex); 647 rwlock_init(&dev_priv->resource_lock); 648 ttm_lock_init(&dev_priv->reservation_sem); 649 spin_lock_init(&dev_priv->hw_lock); 650 spin_lock_init(&dev_priv->waiter_lock); 651 spin_lock_init(&dev_priv->cap_lock); 652 spin_lock_init(&dev_priv->svga_lock); 653 spin_lock_init(&dev_priv->cursor_lock); 654 655 for (i = vmw_res_context; i < vmw_res_max; ++i) { 656 idr_init(&dev_priv->res_idr[i]); 657 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 658 } 659 660 mutex_init(&dev_priv->init_mutex); 661 init_waitqueue_head(&dev_priv->fence_queue); 662 init_waitqueue_head(&dev_priv->fifo_queue); 663 dev_priv->fence_queue_waiters = 0; 664 dev_priv->fifo_queue_waiters = 0; 665 666 dev_priv->used_memory_size = 0; 667 668 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 669 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 670 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 671 672 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 673 674 dev_priv->enable_fb = enable_fbdev; 675 676 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 677 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 678 if (svga_id != SVGA_ID_2) { 679 ret = -ENOSYS; 680 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 681 goto out_err0; 682 } 683 684 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 685 ret = vmw_dma_select_mode(dev_priv); 686 if (unlikely(ret != 0)) { 687 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 688 refuse_dma = true; 689 } 690 691 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 692 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 693 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 694 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 695 696 vmw_get_initial_size(dev_priv); 697 698 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 699 dev_priv->max_gmr_ids = 700 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 701 dev_priv->max_gmr_pages = 702 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 703 dev_priv->memory_size = 704 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 705 dev_priv->memory_size -= dev_priv->vram_size; 706 } else { 707 /* 708 * An arbitrary limit of 512MiB on surface 709 * memory. But all HWV8 hardware supports GMR2. 710 */ 711 dev_priv->memory_size = 512*1024*1024; 712 } 713 dev_priv->max_mob_pages = 0; 714 dev_priv->max_mob_size = 0; 715 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 716 uint64_t mem_size = 717 vmw_read(dev_priv, 718 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 719 720 /* 721 * Workaround for low memory 2D VMs to compensate for the 722 * allocation taken by fbdev 723 */ 724 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 725 mem_size *= 2; 726 727 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 728 dev_priv->prim_bb_mem = 729 vmw_read(dev_priv, 730 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 731 dev_priv->max_mob_size = 732 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 733 dev_priv->stdu_max_width = 734 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 735 dev_priv->stdu_max_height = 736 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 737 738 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 739 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 740 dev_priv->texture_max_width = vmw_read(dev_priv, 741 SVGA_REG_DEV_CAP); 742 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 743 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 744 dev_priv->texture_max_height = vmw_read(dev_priv, 745 SVGA_REG_DEV_CAP); 746 } else { 747 dev_priv->texture_max_width = 8192; 748 dev_priv->texture_max_height = 8192; 749 dev_priv->prim_bb_mem = dev_priv->vram_size; 750 } 751 752 vmw_print_capabilities(dev_priv->capabilities); 753 754 ret = vmw_dma_masks(dev_priv); 755 if (unlikely(ret != 0)) 756 goto out_err0; 757 758 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 759 DRM_INFO("Max GMR ids is %u\n", 760 (unsigned)dev_priv->max_gmr_ids); 761 DRM_INFO("Max number of GMR pages is %u\n", 762 (unsigned)dev_priv->max_gmr_pages); 763 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 764 (unsigned)dev_priv->memory_size / 1024); 765 } 766 DRM_INFO("Maximum display memory size is %u kiB\n", 767 dev_priv->prim_bb_mem / 1024); 768 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 769 dev_priv->vram_start, dev_priv->vram_size / 1024); 770 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 771 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 772 773 ret = vmw_ttm_global_init(dev_priv); 774 if (unlikely(ret != 0)) 775 goto out_err0; 776 777 778 vmw_master_init(&dev_priv->fbdev_master); 779 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 780 dev_priv->active_master = &dev_priv->fbdev_master; 781 782 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 783 dev_priv->mmio_size, MEMREMAP_WB); 784 785 if (unlikely(dev_priv->mmio_virt == NULL)) { 786 ret = -ENOMEM; 787 DRM_ERROR("Failed mapping MMIO.\n"); 788 goto out_err3; 789 } 790 791 /* Need mmio memory to check for fifo pitchlock cap. */ 792 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 793 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 794 !vmw_fifo_have_pitchlock(dev_priv)) { 795 ret = -ENOSYS; 796 DRM_ERROR("Hardware has no pitchlock\n"); 797 goto out_err4; 798 } 799 800 dev_priv->tdev = ttm_object_device_init 801 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); 802 803 if (unlikely(dev_priv->tdev == NULL)) { 804 DRM_ERROR("Unable to initialize TTM object management.\n"); 805 ret = -ENOMEM; 806 goto out_err4; 807 } 808 809 dev->dev_private = dev_priv; 810 811 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 812 dev_priv->stealth = (ret != 0); 813 if (dev_priv->stealth) { 814 /** 815 * Request at least the mmio PCI resource. 816 */ 817 818 DRM_INFO("It appears like vesafb is loaded. " 819 "Ignore above error if any.\n"); 820 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 821 if (unlikely(ret != 0)) { 822 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 823 goto out_no_device; 824 } 825 } 826 827 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 828 ret = drm_irq_install(dev, dev->pdev->irq); 829 if (ret != 0) { 830 DRM_ERROR("Failed installing irq: %d\n", ret); 831 goto out_no_irq; 832 } 833 } 834 835 dev_priv->fman = vmw_fence_manager_init(dev_priv); 836 if (unlikely(dev_priv->fman == NULL)) { 837 ret = -ENOMEM; 838 goto out_no_fman; 839 } 840 841 ret = ttm_bo_device_init(&dev_priv->bdev, 842 dev_priv->bo_global_ref.ref.object, 843 &vmw_bo_driver, 844 dev->anon_inode->i_mapping, 845 VMWGFX_FILE_PAGE_OFFSET, 846 false); 847 if (unlikely(ret != 0)) { 848 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 849 goto out_no_bdev; 850 } 851 852 /* 853 * Enable VRAM, but initially don't use it until SVGA is enabled and 854 * unhidden. 855 */ 856 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 857 (dev_priv->vram_size >> PAGE_SHIFT)); 858 if (unlikely(ret != 0)) { 859 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 860 goto out_no_vram; 861 } 862 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 863 864 dev_priv->has_gmr = true; 865 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 866 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 867 VMW_PL_GMR) != 0) { 868 DRM_INFO("No GMR memory available. " 869 "Graphics memory resources are very limited.\n"); 870 dev_priv->has_gmr = false; 871 } 872 873 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 874 dev_priv->has_mob = true; 875 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 876 VMW_PL_MOB) != 0) { 877 DRM_INFO("No MOB memory available. " 878 "3D will be disabled.\n"); 879 dev_priv->has_mob = false; 880 } 881 } 882 883 if (dev_priv->has_mob) { 884 spin_lock(&dev_priv->cap_lock); 885 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX); 886 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 887 spin_unlock(&dev_priv->cap_lock); 888 } 889 890 891 ret = vmw_kms_init(dev_priv); 892 if (unlikely(ret != 0)) 893 goto out_no_kms; 894 vmw_overlay_init(dev_priv); 895 896 ret = vmw_request_device(dev_priv); 897 if (ret) 898 goto out_no_fifo; 899 900 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 901 DRM_INFO("Atomic: %s\n", 902 (dev->driver->driver_features & DRIVER_ATOMIC) ? "yes" : "no"); 903 904 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 905 VMWGFX_REPO, VMWGFX_GIT_VERSION); 906 vmw_host_log(host_log); 907 908 memset(host_log, 0, sizeof(host_log)); 909 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 910 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 911 VMWGFX_DRIVER_PATCHLEVEL); 912 vmw_host_log(host_log); 913 914 if (dev_priv->enable_fb) { 915 vmw_fifo_resource_inc(dev_priv); 916 vmw_svga_enable(dev_priv); 917 vmw_fb_init(dev_priv); 918 } 919 920 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 921 register_pm_notifier(&dev_priv->pm_nb); 922 923 return 0; 924 925 out_no_fifo: 926 vmw_overlay_close(dev_priv); 927 vmw_kms_close(dev_priv); 928 out_no_kms: 929 if (dev_priv->has_mob) 930 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 931 if (dev_priv->has_gmr) 932 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 933 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 934 out_no_vram: 935 (void)ttm_bo_device_release(&dev_priv->bdev); 936 out_no_bdev: 937 vmw_fence_manager_takedown(dev_priv->fman); 938 out_no_fman: 939 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 940 drm_irq_uninstall(dev_priv->dev); 941 out_no_irq: 942 if (dev_priv->stealth) 943 pci_release_region(dev->pdev, 2); 944 else 945 pci_release_regions(dev->pdev); 946 out_no_device: 947 ttm_object_device_release(&dev_priv->tdev); 948 out_err4: 949 memunmap(dev_priv->mmio_virt); 950 out_err3: 951 vmw_ttm_global_release(dev_priv); 952 out_err0: 953 for (i = vmw_res_context; i < vmw_res_max; ++i) 954 idr_destroy(&dev_priv->res_idr[i]); 955 956 if (dev_priv->ctx.staged_bindings) 957 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 958 kfree(dev_priv); 959 return ret; 960 } 961 962 static void vmw_driver_unload(struct drm_device *dev) 963 { 964 struct vmw_private *dev_priv = vmw_priv(dev); 965 enum vmw_res_type i; 966 967 unregister_pm_notifier(&dev_priv->pm_nb); 968 969 if (dev_priv->ctx.res_ht_initialized) 970 drm_ht_remove(&dev_priv->ctx.res_ht); 971 vfree(dev_priv->ctx.cmd_bounce); 972 if (dev_priv->enable_fb) { 973 vmw_fb_off(dev_priv); 974 vmw_fb_close(dev_priv); 975 vmw_fifo_resource_dec(dev_priv); 976 vmw_svga_disable(dev_priv); 977 } 978 979 vmw_kms_close(dev_priv); 980 vmw_overlay_close(dev_priv); 981 982 if (dev_priv->has_gmr) 983 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 984 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 985 986 vmw_release_device_early(dev_priv); 987 if (dev_priv->has_mob) 988 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 989 (void) ttm_bo_device_release(&dev_priv->bdev); 990 vmw_release_device_late(dev_priv); 991 vmw_fence_manager_takedown(dev_priv->fman); 992 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 993 drm_irq_uninstall(dev_priv->dev); 994 if (dev_priv->stealth) 995 pci_release_region(dev->pdev, 2); 996 else 997 pci_release_regions(dev->pdev); 998 999 ttm_object_device_release(&dev_priv->tdev); 1000 memunmap(dev_priv->mmio_virt); 1001 if (dev_priv->ctx.staged_bindings) 1002 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1003 vmw_ttm_global_release(dev_priv); 1004 1005 for (i = vmw_res_context; i < vmw_res_max; ++i) 1006 idr_destroy(&dev_priv->res_idr[i]); 1007 1008 kfree(dev_priv); 1009 } 1010 1011 static void vmw_postclose(struct drm_device *dev, 1012 struct drm_file *file_priv) 1013 { 1014 struct vmw_fpriv *vmw_fp; 1015 1016 vmw_fp = vmw_fpriv(file_priv); 1017 1018 if (vmw_fp->locked_master) { 1019 struct vmw_master *vmaster = 1020 vmw_master(vmw_fp->locked_master); 1021 1022 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1023 ttm_vt_unlock(&vmaster->lock); 1024 drm_master_put(&vmw_fp->locked_master); 1025 } 1026 1027 ttm_object_file_release(&vmw_fp->tfile); 1028 kfree(vmw_fp); 1029 } 1030 1031 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1032 { 1033 struct vmw_private *dev_priv = vmw_priv(dev); 1034 struct vmw_fpriv *vmw_fp; 1035 int ret = -ENOMEM; 1036 1037 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1038 if (unlikely(!vmw_fp)) 1039 return ret; 1040 1041 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1042 if (unlikely(vmw_fp->tfile == NULL)) 1043 goto out_no_tfile; 1044 1045 file_priv->driver_priv = vmw_fp; 1046 1047 return 0; 1048 1049 out_no_tfile: 1050 kfree(vmw_fp); 1051 return ret; 1052 } 1053 1054 static struct vmw_master *vmw_master_check(struct drm_device *dev, 1055 struct drm_file *file_priv, 1056 unsigned int flags) 1057 { 1058 int ret; 1059 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1060 struct vmw_master *vmaster; 1061 1062 if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH)) 1063 return NULL; 1064 1065 ret = mutex_lock_interruptible(&dev->master_mutex); 1066 if (unlikely(ret != 0)) 1067 return ERR_PTR(-ERESTARTSYS); 1068 1069 if (drm_is_current_master(file_priv)) { 1070 mutex_unlock(&dev->master_mutex); 1071 return NULL; 1072 } 1073 1074 /* 1075 * Check if we were previously master, but now dropped. In that 1076 * case, allow at least render node functionality. 1077 */ 1078 if (vmw_fp->locked_master) { 1079 mutex_unlock(&dev->master_mutex); 1080 1081 if (flags & DRM_RENDER_ALLOW) 1082 return NULL; 1083 1084 DRM_ERROR("Dropped master trying to access ioctl that " 1085 "requires authentication.\n"); 1086 return ERR_PTR(-EACCES); 1087 } 1088 mutex_unlock(&dev->master_mutex); 1089 1090 /* 1091 * Take the TTM lock. Possibly sleep waiting for the authenticating 1092 * master to become master again, or for a SIGTERM if the 1093 * authenticating master exits. 1094 */ 1095 vmaster = vmw_master(file_priv->master); 1096 ret = ttm_read_lock(&vmaster->lock, true); 1097 if (unlikely(ret != 0)) 1098 vmaster = ERR_PTR(ret); 1099 1100 return vmaster; 1101 } 1102 1103 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1104 unsigned long arg, 1105 long (*ioctl_func)(struct file *, unsigned int, 1106 unsigned long)) 1107 { 1108 struct drm_file *file_priv = filp->private_data; 1109 struct drm_device *dev = file_priv->minor->dev; 1110 unsigned int nr = DRM_IOCTL_NR(cmd); 1111 struct vmw_master *vmaster; 1112 unsigned int flags; 1113 long ret; 1114 1115 /* 1116 * Do extra checking on driver private ioctls. 1117 */ 1118 1119 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1120 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1121 const struct drm_ioctl_desc *ioctl = 1122 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1123 1124 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1125 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); 1126 if (unlikely(ret != 0)) 1127 return ret; 1128 1129 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) 1130 goto out_io_encoding; 1131 1132 return (long) vmw_execbuf_ioctl(dev, arg, file_priv, 1133 _IOC_SIZE(cmd)); 1134 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1135 if (!drm_is_current_master(file_priv) && 1136 !capable(CAP_SYS_ADMIN)) 1137 return -EACCES; 1138 } 1139 1140 if (unlikely(ioctl->cmd != cmd)) 1141 goto out_io_encoding; 1142 1143 flags = ioctl->flags; 1144 } else if (!drm_ioctl_flags(nr, &flags)) 1145 return -EINVAL; 1146 1147 vmaster = vmw_master_check(dev, file_priv, flags); 1148 if (IS_ERR(vmaster)) { 1149 ret = PTR_ERR(vmaster); 1150 1151 if (ret != -ERESTARTSYS) 1152 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", 1153 nr, ret); 1154 return ret; 1155 } 1156 1157 ret = ioctl_func(filp, cmd, arg); 1158 if (vmaster) 1159 ttm_read_unlock(&vmaster->lock); 1160 1161 return ret; 1162 1163 out_io_encoding: 1164 DRM_ERROR("Invalid command format, ioctl %d\n", 1165 nr - DRM_COMMAND_BASE); 1166 1167 return -EINVAL; 1168 } 1169 1170 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1171 unsigned long arg) 1172 { 1173 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1174 } 1175 1176 #ifdef CONFIG_COMPAT 1177 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1178 unsigned long arg) 1179 { 1180 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1181 } 1182 #endif 1183 1184 static void vmw_lastclose(struct drm_device *dev) 1185 { 1186 } 1187 1188 static void vmw_master_init(struct vmw_master *vmaster) 1189 { 1190 ttm_lock_init(&vmaster->lock); 1191 } 1192 1193 static int vmw_master_create(struct drm_device *dev, 1194 struct drm_master *master) 1195 { 1196 struct vmw_master *vmaster; 1197 1198 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); 1199 if (unlikely(!vmaster)) 1200 return -ENOMEM; 1201 1202 vmw_master_init(vmaster); 1203 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1204 master->driver_priv = vmaster; 1205 1206 return 0; 1207 } 1208 1209 static void vmw_master_destroy(struct drm_device *dev, 1210 struct drm_master *master) 1211 { 1212 struct vmw_master *vmaster = vmw_master(master); 1213 1214 master->driver_priv = NULL; 1215 kfree(vmaster); 1216 } 1217 1218 static int vmw_master_set(struct drm_device *dev, 1219 struct drm_file *file_priv, 1220 bool from_open) 1221 { 1222 struct vmw_private *dev_priv = vmw_priv(dev); 1223 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1224 struct vmw_master *active = dev_priv->active_master; 1225 struct vmw_master *vmaster = vmw_master(file_priv->master); 1226 int ret = 0; 1227 1228 if (active) { 1229 BUG_ON(active != &dev_priv->fbdev_master); 1230 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 1231 if (unlikely(ret != 0)) 1232 return ret; 1233 1234 ttm_lock_set_kill(&active->lock, true, SIGTERM); 1235 dev_priv->active_master = NULL; 1236 } 1237 1238 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1239 if (!from_open) { 1240 ttm_vt_unlock(&vmaster->lock); 1241 BUG_ON(vmw_fp->locked_master != file_priv->master); 1242 drm_master_put(&vmw_fp->locked_master); 1243 } 1244 1245 dev_priv->active_master = vmaster; 1246 drm_sysfs_hotplug_event(dev); 1247 1248 return 0; 1249 } 1250 1251 static void vmw_master_drop(struct drm_device *dev, 1252 struct drm_file *file_priv) 1253 { 1254 struct vmw_private *dev_priv = vmw_priv(dev); 1255 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1256 struct vmw_master *vmaster = vmw_master(file_priv->master); 1257 int ret; 1258 1259 /** 1260 * Make sure the master doesn't disappear while we have 1261 * it locked. 1262 */ 1263 1264 vmw_fp->locked_master = drm_master_get(file_priv->master); 1265 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 1266 vmw_kms_legacy_hotspot_clear(dev_priv); 1267 if (unlikely((ret != 0))) { 1268 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 1269 drm_master_put(&vmw_fp->locked_master); 1270 } 1271 1272 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1273 1274 if (!dev_priv->enable_fb) 1275 vmw_svga_disable(dev_priv); 1276 1277 dev_priv->active_master = &dev_priv->fbdev_master; 1278 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 1279 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 1280 1281 if (dev_priv->enable_fb) 1282 vmw_fb_on(dev_priv); 1283 } 1284 1285 /** 1286 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1287 * 1288 * @dev_priv: Pointer to device private struct. 1289 * Needs the reservation sem to be held in non-exclusive mode. 1290 */ 1291 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1292 { 1293 spin_lock(&dev_priv->svga_lock); 1294 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1295 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1296 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1297 } 1298 spin_unlock(&dev_priv->svga_lock); 1299 } 1300 1301 /** 1302 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1303 * 1304 * @dev_priv: Pointer to device private struct. 1305 */ 1306 void vmw_svga_enable(struct vmw_private *dev_priv) 1307 { 1308 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1309 __vmw_svga_enable(dev_priv); 1310 ttm_read_unlock(&dev_priv->reservation_sem); 1311 } 1312 1313 /** 1314 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1315 * 1316 * @dev_priv: Pointer to device private struct. 1317 * Needs the reservation sem to be held in exclusive mode. 1318 * Will not empty VRAM. VRAM must be emptied by caller. 1319 */ 1320 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1321 { 1322 spin_lock(&dev_priv->svga_lock); 1323 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1324 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1325 vmw_write(dev_priv, SVGA_REG_ENABLE, 1326 SVGA_REG_ENABLE_HIDE | 1327 SVGA_REG_ENABLE_ENABLE); 1328 } 1329 spin_unlock(&dev_priv->svga_lock); 1330 } 1331 1332 /** 1333 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1334 * running. 1335 * 1336 * @dev_priv: Pointer to device private struct. 1337 * Will empty VRAM. 1338 */ 1339 void vmw_svga_disable(struct vmw_private *dev_priv) 1340 { 1341 ttm_write_lock(&dev_priv->reservation_sem, false); 1342 spin_lock(&dev_priv->svga_lock); 1343 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1344 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1345 spin_unlock(&dev_priv->svga_lock); 1346 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1347 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1348 vmw_write(dev_priv, SVGA_REG_ENABLE, 1349 SVGA_REG_ENABLE_HIDE | 1350 SVGA_REG_ENABLE_ENABLE); 1351 } else 1352 spin_unlock(&dev_priv->svga_lock); 1353 ttm_write_unlock(&dev_priv->reservation_sem); 1354 } 1355 1356 static void vmw_remove(struct pci_dev *pdev) 1357 { 1358 struct drm_device *dev = pci_get_drvdata(pdev); 1359 1360 pci_disable_device(pdev); 1361 drm_put_dev(dev); 1362 } 1363 1364 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1365 void *ptr) 1366 { 1367 struct vmw_private *dev_priv = 1368 container_of(nb, struct vmw_private, pm_nb); 1369 1370 switch (val) { 1371 case PM_HIBERNATION_PREPARE: 1372 if (dev_priv->enable_fb) 1373 vmw_fb_off(dev_priv); 1374 ttm_suspend_lock(&dev_priv->reservation_sem); 1375 1376 /* 1377 * This empties VRAM and unbinds all GMR bindings. 1378 * Buffer contents is moved to swappable memory. 1379 */ 1380 vmw_execbuf_release_pinned_bo(dev_priv); 1381 vmw_resource_evict_all(dev_priv); 1382 vmw_release_device_early(dev_priv); 1383 ttm_bo_swapout_all(&dev_priv->bdev); 1384 vmw_fence_fifo_down(dev_priv->fman); 1385 break; 1386 case PM_POST_HIBERNATION: 1387 case PM_POST_RESTORE: 1388 vmw_fence_fifo_up(dev_priv->fman); 1389 ttm_suspend_unlock(&dev_priv->reservation_sem); 1390 if (dev_priv->enable_fb) 1391 vmw_fb_on(dev_priv); 1392 break; 1393 case PM_RESTORE_PREPARE: 1394 break; 1395 default: 1396 break; 1397 } 1398 return 0; 1399 } 1400 1401 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1402 { 1403 struct drm_device *dev = pci_get_drvdata(pdev); 1404 struct vmw_private *dev_priv = vmw_priv(dev); 1405 1406 if (dev_priv->refuse_hibernation) 1407 return -EBUSY; 1408 1409 pci_save_state(pdev); 1410 pci_disable_device(pdev); 1411 pci_set_power_state(pdev, PCI_D3hot); 1412 return 0; 1413 } 1414 1415 static int vmw_pci_resume(struct pci_dev *pdev) 1416 { 1417 pci_set_power_state(pdev, PCI_D0); 1418 pci_restore_state(pdev); 1419 return pci_enable_device(pdev); 1420 } 1421 1422 static int vmw_pm_suspend(struct device *kdev) 1423 { 1424 struct pci_dev *pdev = to_pci_dev(kdev); 1425 struct pm_message dummy; 1426 1427 dummy.event = 0; 1428 1429 return vmw_pci_suspend(pdev, dummy); 1430 } 1431 1432 static int vmw_pm_resume(struct device *kdev) 1433 { 1434 struct pci_dev *pdev = to_pci_dev(kdev); 1435 1436 return vmw_pci_resume(pdev); 1437 } 1438 1439 static int vmw_pm_freeze(struct device *kdev) 1440 { 1441 struct pci_dev *pdev = to_pci_dev(kdev); 1442 struct drm_device *dev = pci_get_drvdata(pdev); 1443 struct vmw_private *dev_priv = vmw_priv(dev); 1444 1445 dev_priv->suspended = true; 1446 if (dev_priv->enable_fb) 1447 vmw_fifo_resource_dec(dev_priv); 1448 1449 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1450 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1451 if (dev_priv->enable_fb) 1452 vmw_fifo_resource_inc(dev_priv); 1453 WARN_ON(vmw_request_device_late(dev_priv)); 1454 dev_priv->suspended = false; 1455 return -EBUSY; 1456 } 1457 1458 if (dev_priv->enable_fb) 1459 __vmw_svga_disable(dev_priv); 1460 1461 vmw_release_device_late(dev_priv); 1462 1463 return 0; 1464 } 1465 1466 static int vmw_pm_restore(struct device *kdev) 1467 { 1468 struct pci_dev *pdev = to_pci_dev(kdev); 1469 struct drm_device *dev = pci_get_drvdata(pdev); 1470 struct vmw_private *dev_priv = vmw_priv(dev); 1471 int ret; 1472 1473 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1474 (void) vmw_read(dev_priv, SVGA_REG_ID); 1475 1476 if (dev_priv->enable_fb) 1477 vmw_fifo_resource_inc(dev_priv); 1478 1479 ret = vmw_request_device(dev_priv); 1480 if (ret) 1481 return ret; 1482 1483 if (dev_priv->enable_fb) 1484 __vmw_svga_enable(dev_priv); 1485 1486 dev_priv->suspended = false; 1487 1488 return 0; 1489 } 1490 1491 static const struct dev_pm_ops vmw_pm_ops = { 1492 .freeze = vmw_pm_freeze, 1493 .thaw = vmw_pm_restore, 1494 .restore = vmw_pm_restore, 1495 .suspend = vmw_pm_suspend, 1496 .resume = vmw_pm_resume, 1497 }; 1498 1499 static const struct file_operations vmwgfx_driver_fops = { 1500 .owner = THIS_MODULE, 1501 .open = drm_open, 1502 .release = drm_release, 1503 .unlocked_ioctl = vmw_unlocked_ioctl, 1504 .mmap = vmw_mmap, 1505 .poll = vmw_fops_poll, 1506 .read = vmw_fops_read, 1507 #if defined(CONFIG_COMPAT) 1508 .compat_ioctl = vmw_compat_ioctl, 1509 #endif 1510 .llseek = noop_llseek, 1511 }; 1512 1513 static struct drm_driver driver = { 1514 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | 1515 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC, 1516 .load = vmw_driver_load, 1517 .unload = vmw_driver_unload, 1518 .lastclose = vmw_lastclose, 1519 .irq_preinstall = vmw_irq_preinstall, 1520 .irq_postinstall = vmw_irq_postinstall, 1521 .irq_uninstall = vmw_irq_uninstall, 1522 .irq_handler = vmw_irq_handler, 1523 .get_vblank_counter = vmw_get_vblank_counter, 1524 .enable_vblank = vmw_enable_vblank, 1525 .disable_vblank = vmw_disable_vblank, 1526 .ioctls = vmw_ioctls, 1527 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1528 .master_create = vmw_master_create, 1529 .master_destroy = vmw_master_destroy, 1530 .master_set = vmw_master_set, 1531 .master_drop = vmw_master_drop, 1532 .open = vmw_driver_open, 1533 .postclose = vmw_postclose, 1534 .set_busid = drm_pci_set_busid, 1535 1536 .dumb_create = vmw_dumb_create, 1537 .dumb_map_offset = vmw_dumb_map_offset, 1538 .dumb_destroy = vmw_dumb_destroy, 1539 1540 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1541 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1542 1543 .fops = &vmwgfx_driver_fops, 1544 .name = VMWGFX_DRIVER_NAME, 1545 .desc = VMWGFX_DRIVER_DESC, 1546 .date = VMWGFX_DRIVER_DATE, 1547 .major = VMWGFX_DRIVER_MAJOR, 1548 .minor = VMWGFX_DRIVER_MINOR, 1549 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1550 }; 1551 1552 static struct pci_driver vmw_pci_driver = { 1553 .name = VMWGFX_DRIVER_NAME, 1554 .id_table = vmw_pci_id_list, 1555 .probe = vmw_probe, 1556 .remove = vmw_remove, 1557 .driver = { 1558 .pm = &vmw_pm_ops 1559 } 1560 }; 1561 1562 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1563 { 1564 return drm_get_pci_dev(pdev, ent, &driver); 1565 } 1566 1567 static int __init vmwgfx_init(void) 1568 { 1569 int ret; 1570 1571 if (vgacon_text_force()) 1572 return -EINVAL; 1573 1574 ret = drm_pci_init(&driver, &vmw_pci_driver); 1575 if (ret) 1576 DRM_ERROR("Failed initializing DRM.\n"); 1577 return ret; 1578 } 1579 1580 static void __exit vmwgfx_exit(void) 1581 { 1582 drm_pci_exit(&driver, &vmw_pci_driver); 1583 } 1584 1585 module_init(vmwgfx_init); 1586 module_exit(vmwgfx_exit); 1587 1588 MODULE_AUTHOR("VMware Inc. and others"); 1589 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1590 MODULE_LICENSE("GPL and additional rights"); 1591 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1592 __stringify(VMWGFX_DRIVER_MINOR) "." 1593 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1594 "0"); 1595