1 /************************************************************************** 2 * 3 * Copyright © 2009-2016 VMware, Inc., Palo Alto, CA., USA 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 #include <linux/module.h> 28 #include <linux/console.h> 29 30 #include <drm/drmP.h> 31 #include "vmwgfx_drv.h" 32 #include "vmwgfx_binding.h" 33 #include <drm/ttm/ttm_placement.h> 34 #include <drm/ttm/ttm_bo_driver.h> 35 #include <drm/ttm/ttm_object.h> 36 #include <drm/ttm/ttm_module.h> 37 #include <linux/dma_remapping.h> 38 39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 40 #define VMWGFX_CHIP_SVGAII 0 41 #define VMW_FB_RESERVATION 0 42 43 #define VMW_MIN_INITIAL_WIDTH 800 44 #define VMW_MIN_INITIAL_HEIGHT 600 45 46 #ifndef VMWGFX_GIT_VERSION 47 #define VMWGFX_GIT_VERSION "Unknown" 48 #endif 49 50 #define VMWGFX_REPO "In Tree" 51 52 53 /** 54 * Fully encoded drm commands. Might move to vmw_drm.h 55 */ 56 57 #define DRM_IOCTL_VMW_GET_PARAM \ 58 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 59 struct drm_vmw_getparam_arg) 60 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 61 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 62 union drm_vmw_alloc_dmabuf_arg) 63 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 65 struct drm_vmw_unref_dmabuf_arg) 66 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 67 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 68 struct drm_vmw_cursor_bypass_arg) 69 70 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 72 struct drm_vmw_control_stream_arg) 73 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 75 struct drm_vmw_stream_arg) 76 #define DRM_IOCTL_VMW_UNREF_STREAM \ 77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 78 struct drm_vmw_stream_arg) 79 80 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 81 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 82 struct drm_vmw_context_arg) 83 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 84 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 85 struct drm_vmw_context_arg) 86 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 87 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 88 union drm_vmw_surface_create_arg) 89 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 90 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 91 struct drm_vmw_surface_arg) 92 #define DRM_IOCTL_VMW_REF_SURFACE \ 93 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 94 union drm_vmw_surface_reference_arg) 95 #define DRM_IOCTL_VMW_EXECBUF \ 96 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 97 struct drm_vmw_execbuf_arg) 98 #define DRM_IOCTL_VMW_GET_3D_CAP \ 99 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 100 struct drm_vmw_get_3d_cap_arg) 101 #define DRM_IOCTL_VMW_FENCE_WAIT \ 102 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 103 struct drm_vmw_fence_wait_arg) 104 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 105 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 106 struct drm_vmw_fence_signaled_arg) 107 #define DRM_IOCTL_VMW_FENCE_UNREF \ 108 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 109 struct drm_vmw_fence_arg) 110 #define DRM_IOCTL_VMW_FENCE_EVENT \ 111 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 112 struct drm_vmw_fence_event_arg) 113 #define DRM_IOCTL_VMW_PRESENT \ 114 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 115 struct drm_vmw_present_arg) 116 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 117 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 118 struct drm_vmw_present_readback_arg) 119 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 121 struct drm_vmw_update_layout_arg) 122 #define DRM_IOCTL_VMW_CREATE_SHADER \ 123 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 124 struct drm_vmw_shader_create_arg) 125 #define DRM_IOCTL_VMW_UNREF_SHADER \ 126 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 127 struct drm_vmw_shader_arg) 128 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 129 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 130 union drm_vmw_gb_surface_create_arg) 131 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 132 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 133 union drm_vmw_gb_surface_reference_arg) 134 #define DRM_IOCTL_VMW_SYNCCPU \ 135 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 136 struct drm_vmw_synccpu_arg) 137 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 138 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 139 struct drm_vmw_context_arg) 140 141 /** 142 * The core DRM version of this macro doesn't account for 143 * DRM_COMMAND_BASE. 144 */ 145 146 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 147 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 148 149 /** 150 * Ioctl definitions. 151 */ 152 153 static const struct drm_ioctl_desc vmw_ioctls[] = { 154 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 155 DRM_AUTH | DRM_RENDER_ALLOW), 156 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, 157 DRM_AUTH | DRM_RENDER_ALLOW), 158 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, 159 DRM_RENDER_ALLOW), 160 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 161 vmw_kms_cursor_bypass_ioctl, 162 DRM_MASTER | DRM_CONTROL_ALLOW), 163 164 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 165 DRM_MASTER | DRM_CONTROL_ALLOW), 166 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 167 DRM_MASTER | DRM_CONTROL_ALLOW), 168 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 169 DRM_MASTER | DRM_CONTROL_ALLOW), 170 171 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 172 DRM_AUTH | DRM_RENDER_ALLOW), 173 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 174 DRM_RENDER_ALLOW), 175 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 176 DRM_AUTH | DRM_RENDER_ALLOW), 177 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 178 DRM_RENDER_ALLOW), 179 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 180 DRM_AUTH | DRM_RENDER_ALLOW), 181 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | 182 DRM_RENDER_ALLOW), 183 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 184 DRM_RENDER_ALLOW), 185 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 186 vmw_fence_obj_signaled_ioctl, 187 DRM_RENDER_ALLOW), 188 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 189 DRM_RENDER_ALLOW), 190 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 191 DRM_AUTH | DRM_RENDER_ALLOW), 192 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 193 DRM_AUTH | DRM_RENDER_ALLOW), 194 195 /* these allow direct access to the framebuffers mark as master only */ 196 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 197 DRM_MASTER | DRM_AUTH), 198 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 199 vmw_present_readback_ioctl, 200 DRM_MASTER | DRM_AUTH), 201 /* 202 * The permissions of the below ioctl are overridden in 203 * vmw_generic_ioctl(). We require either 204 * DRM_MASTER or capable(CAP_SYS_ADMIN). 205 */ 206 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 207 vmw_kms_update_layout_ioctl, 208 DRM_RENDER_ALLOW), 209 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 210 vmw_shader_define_ioctl, 211 DRM_AUTH | DRM_RENDER_ALLOW), 212 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 213 vmw_shader_destroy_ioctl, 214 DRM_RENDER_ALLOW), 215 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 216 vmw_gb_surface_define_ioctl, 217 DRM_AUTH | DRM_RENDER_ALLOW), 218 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 219 vmw_gb_surface_reference_ioctl, 220 DRM_AUTH | DRM_RENDER_ALLOW), 221 VMW_IOCTL_DEF(VMW_SYNCCPU, 222 vmw_user_dmabuf_synccpu_ioctl, 223 DRM_RENDER_ALLOW), 224 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 225 vmw_extended_context_define_ioctl, 226 DRM_AUTH | DRM_RENDER_ALLOW), 227 }; 228 229 static const struct pci_device_id vmw_pci_id_list[] = { 230 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 231 {0, 0, 0} 232 }; 233 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 234 235 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 236 static int vmw_force_iommu; 237 static int vmw_restrict_iommu; 238 static int vmw_force_coherent; 239 static int vmw_restrict_dma_mask; 240 static int vmw_assume_16bpp; 241 242 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 243 static void vmw_master_init(struct vmw_master *); 244 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 245 void *ptr); 246 247 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 248 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 249 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 250 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 251 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 252 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 253 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 254 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 255 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 256 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 257 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 258 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 259 260 261 static void vmw_print_capabilities(uint32_t capabilities) 262 { 263 DRM_INFO("Capabilities:\n"); 264 if (capabilities & SVGA_CAP_RECT_COPY) 265 DRM_INFO(" Rect copy.\n"); 266 if (capabilities & SVGA_CAP_CURSOR) 267 DRM_INFO(" Cursor.\n"); 268 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 269 DRM_INFO(" Cursor bypass.\n"); 270 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 271 DRM_INFO(" Cursor bypass 2.\n"); 272 if (capabilities & SVGA_CAP_8BIT_EMULATION) 273 DRM_INFO(" 8bit emulation.\n"); 274 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 275 DRM_INFO(" Alpha cursor.\n"); 276 if (capabilities & SVGA_CAP_3D) 277 DRM_INFO(" 3D.\n"); 278 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 279 DRM_INFO(" Extended Fifo.\n"); 280 if (capabilities & SVGA_CAP_MULTIMON) 281 DRM_INFO(" Multimon.\n"); 282 if (capabilities & SVGA_CAP_PITCHLOCK) 283 DRM_INFO(" Pitchlock.\n"); 284 if (capabilities & SVGA_CAP_IRQMASK) 285 DRM_INFO(" Irq mask.\n"); 286 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 287 DRM_INFO(" Display Topology.\n"); 288 if (capabilities & SVGA_CAP_GMR) 289 DRM_INFO(" GMR.\n"); 290 if (capabilities & SVGA_CAP_TRACES) 291 DRM_INFO(" Traces.\n"); 292 if (capabilities & SVGA_CAP_GMR2) 293 DRM_INFO(" GMR2.\n"); 294 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 295 DRM_INFO(" Screen Object 2.\n"); 296 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 297 DRM_INFO(" Command Buffers.\n"); 298 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 299 DRM_INFO(" Command Buffers 2.\n"); 300 if (capabilities & SVGA_CAP_GBOBJECTS) 301 DRM_INFO(" Guest Backed Resources.\n"); 302 if (capabilities & SVGA_CAP_DX) 303 DRM_INFO(" DX Features.\n"); 304 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 305 DRM_INFO(" HP Command Queue.\n"); 306 } 307 308 /** 309 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 310 * 311 * @dev_priv: A device private structure. 312 * 313 * This function creates a small buffer object that holds the query 314 * result for dummy queries emitted as query barriers. 315 * The function will then map the first page and initialize a pending 316 * occlusion query result structure, Finally it will unmap the buffer. 317 * No interruptible waits are done within this function. 318 * 319 * Returns an error if bo creation or initialization fails. 320 */ 321 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 322 { 323 int ret; 324 struct vmw_dma_buffer *vbo; 325 struct ttm_bo_kmap_obj map; 326 volatile SVGA3dQueryResult *result; 327 bool dummy; 328 329 /* 330 * Create the vbo as pinned, so that a tryreserve will 331 * immediately succeed. This is because we're the only 332 * user of the bo currently. 333 */ 334 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 335 if (!vbo) 336 return -ENOMEM; 337 338 ret = vmw_dmabuf_init(dev_priv, vbo, PAGE_SIZE, 339 &vmw_sys_ne_placement, false, 340 &vmw_dmabuf_bo_free); 341 if (unlikely(ret != 0)) 342 return ret; 343 344 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 345 BUG_ON(ret != 0); 346 vmw_bo_pin_reserved(vbo, true); 347 348 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 349 if (likely(ret == 0)) { 350 result = ttm_kmap_obj_virtual(&map, &dummy); 351 result->totalSize = sizeof(*result); 352 result->state = SVGA3D_QUERYSTATE_PENDING; 353 result->result32 = 0xff; 354 ttm_bo_kunmap(&map); 355 } 356 vmw_bo_pin_reserved(vbo, false); 357 ttm_bo_unreserve(&vbo->base); 358 359 if (unlikely(ret != 0)) { 360 DRM_ERROR("Dummy query buffer map failed.\n"); 361 vmw_dmabuf_unreference(&vbo); 362 } else 363 dev_priv->dummy_query_bo = vbo; 364 365 return ret; 366 } 367 368 /** 369 * vmw_request_device_late - Perform late device setup 370 * 371 * @dev_priv: Pointer to device private. 372 * 373 * This function performs setup of otables and enables large command 374 * buffer submission. These tasks are split out to a separate function 375 * because it reverts vmw_release_device_early and is intended to be used 376 * by an error path in the hibernation code. 377 */ 378 static int vmw_request_device_late(struct vmw_private *dev_priv) 379 { 380 int ret; 381 382 if (dev_priv->has_mob) { 383 ret = vmw_otables_setup(dev_priv); 384 if (unlikely(ret != 0)) { 385 DRM_ERROR("Unable to initialize " 386 "guest Memory OBjects.\n"); 387 return ret; 388 } 389 } 390 391 if (dev_priv->cman) { 392 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 393 256*4096, 2*4096); 394 if (ret) { 395 struct vmw_cmdbuf_man *man = dev_priv->cman; 396 397 dev_priv->cman = NULL; 398 vmw_cmdbuf_man_destroy(man); 399 } 400 } 401 402 return 0; 403 } 404 405 static int vmw_request_device(struct vmw_private *dev_priv) 406 { 407 int ret; 408 409 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 410 if (unlikely(ret != 0)) { 411 DRM_ERROR("Unable to initialize FIFO.\n"); 412 return ret; 413 } 414 vmw_fence_fifo_up(dev_priv->fman); 415 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 416 if (IS_ERR(dev_priv->cman)) { 417 dev_priv->cman = NULL; 418 dev_priv->has_dx = false; 419 } 420 421 ret = vmw_request_device_late(dev_priv); 422 if (ret) 423 goto out_no_mob; 424 425 ret = vmw_dummy_query_bo_create(dev_priv); 426 if (unlikely(ret != 0)) 427 goto out_no_query_bo; 428 429 return 0; 430 431 out_no_query_bo: 432 if (dev_priv->cman) 433 vmw_cmdbuf_remove_pool(dev_priv->cman); 434 if (dev_priv->has_mob) { 435 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 436 vmw_otables_takedown(dev_priv); 437 } 438 if (dev_priv->cman) 439 vmw_cmdbuf_man_destroy(dev_priv->cman); 440 out_no_mob: 441 vmw_fence_fifo_down(dev_priv->fman); 442 vmw_fifo_release(dev_priv, &dev_priv->fifo); 443 return ret; 444 } 445 446 /** 447 * vmw_release_device_early - Early part of fifo takedown. 448 * 449 * @dev_priv: Pointer to device private struct. 450 * 451 * This is the first part of command submission takedown, to be called before 452 * buffer management is taken down. 453 */ 454 static void vmw_release_device_early(struct vmw_private *dev_priv) 455 { 456 /* 457 * Previous destructions should've released 458 * the pinned bo. 459 */ 460 461 BUG_ON(dev_priv->pinned_bo != NULL); 462 463 vmw_dmabuf_unreference(&dev_priv->dummy_query_bo); 464 if (dev_priv->cman) 465 vmw_cmdbuf_remove_pool(dev_priv->cman); 466 467 if (dev_priv->has_mob) { 468 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 469 vmw_otables_takedown(dev_priv); 470 } 471 } 472 473 /** 474 * vmw_release_device_late - Late part of fifo takedown. 475 * 476 * @dev_priv: Pointer to device private struct. 477 * 478 * This is the last part of the command submission takedown, to be called when 479 * command submission is no longer needed. It may wait on pending fences. 480 */ 481 static void vmw_release_device_late(struct vmw_private *dev_priv) 482 { 483 vmw_fence_fifo_down(dev_priv->fman); 484 if (dev_priv->cman) 485 vmw_cmdbuf_man_destroy(dev_priv->cman); 486 487 vmw_fifo_release(dev_priv, &dev_priv->fifo); 488 } 489 490 /** 491 * Sets the initial_[width|height] fields on the given vmw_private. 492 * 493 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 494 * clamping the value to fb_max_[width|height] fields and the 495 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 496 * If the values appear to be invalid, set them to 497 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 498 */ 499 static void vmw_get_initial_size(struct vmw_private *dev_priv) 500 { 501 uint32_t width; 502 uint32_t height; 503 504 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 505 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 506 507 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 508 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 509 510 if (width > dev_priv->fb_max_width || 511 height > dev_priv->fb_max_height) { 512 513 /* 514 * This is a host error and shouldn't occur. 515 */ 516 517 width = VMW_MIN_INITIAL_WIDTH; 518 height = VMW_MIN_INITIAL_HEIGHT; 519 } 520 521 dev_priv->initial_width = width; 522 dev_priv->initial_height = height; 523 } 524 525 /** 526 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 527 * system. 528 * 529 * @dev_priv: Pointer to a struct vmw_private 530 * 531 * This functions tries to determine the IOMMU setup and what actions 532 * need to be taken by the driver to make system pages visible to the 533 * device. 534 * If this function decides that DMA is not possible, it returns -EINVAL. 535 * The driver may then try to disable features of the device that require 536 * DMA. 537 */ 538 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 539 { 540 static const char *names[vmw_dma_map_max] = { 541 [vmw_dma_phys] = "Using physical TTM page addresses.", 542 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 543 [vmw_dma_map_populate] = "Keeping DMA mappings.", 544 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 545 #ifdef CONFIG_X86 546 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); 547 548 #ifdef CONFIG_INTEL_IOMMU 549 if (intel_iommu_enabled) { 550 dev_priv->map_mode = vmw_dma_map_populate; 551 goto out_fixup; 552 } 553 #endif 554 555 if (!(vmw_force_iommu || vmw_force_coherent)) { 556 dev_priv->map_mode = vmw_dma_phys; 557 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 558 return 0; 559 } 560 561 dev_priv->map_mode = vmw_dma_map_populate; 562 563 if (dma_ops->sync_single_for_cpu) 564 dev_priv->map_mode = vmw_dma_alloc_coherent; 565 #ifdef CONFIG_SWIOTLB 566 if (swiotlb_nr_tbl() == 0) 567 dev_priv->map_mode = vmw_dma_map_populate; 568 #endif 569 570 #ifdef CONFIG_INTEL_IOMMU 571 out_fixup: 572 #endif 573 if (dev_priv->map_mode == vmw_dma_map_populate && 574 vmw_restrict_iommu) 575 dev_priv->map_mode = vmw_dma_map_bind; 576 577 if (vmw_force_coherent) 578 dev_priv->map_mode = vmw_dma_alloc_coherent; 579 580 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) 581 /* 582 * No coherent page pool 583 */ 584 if (dev_priv->map_mode == vmw_dma_alloc_coherent) 585 return -EINVAL; 586 #endif 587 588 #else /* CONFIG_X86 */ 589 dev_priv->map_mode = vmw_dma_map_populate; 590 #endif /* CONFIG_X86 */ 591 592 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 593 594 return 0; 595 } 596 597 /** 598 * vmw_dma_masks - set required page- and dma masks 599 * 600 * @dev: Pointer to struct drm-device 601 * 602 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 603 * restriction also for 64-bit systems. 604 */ 605 #ifdef CONFIG_INTEL_IOMMU 606 static int vmw_dma_masks(struct vmw_private *dev_priv) 607 { 608 struct drm_device *dev = dev_priv->dev; 609 610 if (intel_iommu_enabled && 611 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 612 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 613 return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); 614 } 615 return 0; 616 } 617 #else 618 static int vmw_dma_masks(struct vmw_private *dev_priv) 619 { 620 return 0; 621 } 622 #endif 623 624 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 625 { 626 struct vmw_private *dev_priv; 627 int ret; 628 uint32_t svga_id; 629 enum vmw_res_type i; 630 bool refuse_dma = false; 631 char host_log[100] = {0}; 632 633 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 634 if (unlikely(!dev_priv)) { 635 DRM_ERROR("Failed allocating a device private struct.\n"); 636 return -ENOMEM; 637 } 638 639 pci_set_master(dev->pdev); 640 641 dev_priv->dev = dev; 642 dev_priv->vmw_chipset = chipset; 643 dev_priv->last_read_seqno = (uint32_t) -100; 644 mutex_init(&dev_priv->cmdbuf_mutex); 645 mutex_init(&dev_priv->release_mutex); 646 mutex_init(&dev_priv->binding_mutex); 647 mutex_init(&dev_priv->global_kms_state_mutex); 648 rwlock_init(&dev_priv->resource_lock); 649 ttm_lock_init(&dev_priv->reservation_sem); 650 spin_lock_init(&dev_priv->hw_lock); 651 spin_lock_init(&dev_priv->waiter_lock); 652 spin_lock_init(&dev_priv->cap_lock); 653 spin_lock_init(&dev_priv->svga_lock); 654 spin_lock_init(&dev_priv->cursor_lock); 655 656 for (i = vmw_res_context; i < vmw_res_max; ++i) { 657 idr_init(&dev_priv->res_idr[i]); 658 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 659 } 660 661 mutex_init(&dev_priv->init_mutex); 662 init_waitqueue_head(&dev_priv->fence_queue); 663 init_waitqueue_head(&dev_priv->fifo_queue); 664 dev_priv->fence_queue_waiters = 0; 665 dev_priv->fifo_queue_waiters = 0; 666 667 dev_priv->used_memory_size = 0; 668 669 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 670 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 671 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 672 673 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 674 675 dev_priv->enable_fb = enable_fbdev; 676 677 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 678 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 679 if (svga_id != SVGA_ID_2) { 680 ret = -ENOSYS; 681 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 682 goto out_err0; 683 } 684 685 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 686 ret = vmw_dma_select_mode(dev_priv); 687 if (unlikely(ret != 0)) { 688 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 689 refuse_dma = true; 690 } 691 692 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 693 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 694 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 695 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 696 697 vmw_get_initial_size(dev_priv); 698 699 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 700 dev_priv->max_gmr_ids = 701 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 702 dev_priv->max_gmr_pages = 703 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 704 dev_priv->memory_size = 705 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 706 dev_priv->memory_size -= dev_priv->vram_size; 707 } else { 708 /* 709 * An arbitrary limit of 512MiB on surface 710 * memory. But all HWV8 hardware supports GMR2. 711 */ 712 dev_priv->memory_size = 512*1024*1024; 713 } 714 dev_priv->max_mob_pages = 0; 715 dev_priv->max_mob_size = 0; 716 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 717 uint64_t mem_size = 718 vmw_read(dev_priv, 719 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 720 721 /* 722 * Workaround for low memory 2D VMs to compensate for the 723 * allocation taken by fbdev 724 */ 725 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 726 mem_size *= 3; 727 728 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 729 dev_priv->prim_bb_mem = 730 vmw_read(dev_priv, 731 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 732 dev_priv->max_mob_size = 733 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 734 dev_priv->stdu_max_width = 735 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 736 dev_priv->stdu_max_height = 737 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 738 739 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 740 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 741 dev_priv->texture_max_width = vmw_read(dev_priv, 742 SVGA_REG_DEV_CAP); 743 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 744 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 745 dev_priv->texture_max_height = vmw_read(dev_priv, 746 SVGA_REG_DEV_CAP); 747 } else { 748 dev_priv->texture_max_width = 8192; 749 dev_priv->texture_max_height = 8192; 750 dev_priv->prim_bb_mem = dev_priv->vram_size; 751 } 752 753 vmw_print_capabilities(dev_priv->capabilities); 754 755 ret = vmw_dma_masks(dev_priv); 756 if (unlikely(ret != 0)) 757 goto out_err0; 758 759 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 760 DRM_INFO("Max GMR ids is %u\n", 761 (unsigned)dev_priv->max_gmr_ids); 762 DRM_INFO("Max number of GMR pages is %u\n", 763 (unsigned)dev_priv->max_gmr_pages); 764 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 765 (unsigned)dev_priv->memory_size / 1024); 766 } 767 DRM_INFO("Maximum display memory size is %u kiB\n", 768 dev_priv->prim_bb_mem / 1024); 769 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 770 dev_priv->vram_start, dev_priv->vram_size / 1024); 771 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 772 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 773 774 ret = vmw_ttm_global_init(dev_priv); 775 if (unlikely(ret != 0)) 776 goto out_err0; 777 778 779 vmw_master_init(&dev_priv->fbdev_master); 780 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 781 dev_priv->active_master = &dev_priv->fbdev_master; 782 783 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 784 dev_priv->mmio_size, MEMREMAP_WB); 785 786 if (unlikely(dev_priv->mmio_virt == NULL)) { 787 ret = -ENOMEM; 788 DRM_ERROR("Failed mapping MMIO.\n"); 789 goto out_err3; 790 } 791 792 /* Need mmio memory to check for fifo pitchlock cap. */ 793 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 794 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 795 !vmw_fifo_have_pitchlock(dev_priv)) { 796 ret = -ENOSYS; 797 DRM_ERROR("Hardware has no pitchlock\n"); 798 goto out_err4; 799 } 800 801 dev_priv->tdev = ttm_object_device_init 802 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); 803 804 if (unlikely(dev_priv->tdev == NULL)) { 805 DRM_ERROR("Unable to initialize TTM object management.\n"); 806 ret = -ENOMEM; 807 goto out_err4; 808 } 809 810 dev->dev_private = dev_priv; 811 812 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 813 dev_priv->stealth = (ret != 0); 814 if (dev_priv->stealth) { 815 /** 816 * Request at least the mmio PCI resource. 817 */ 818 819 DRM_INFO("It appears like vesafb is loaded. " 820 "Ignore above error if any.\n"); 821 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 822 if (unlikely(ret != 0)) { 823 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 824 goto out_no_device; 825 } 826 } 827 828 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 829 ret = vmw_irq_install(dev, dev->pdev->irq); 830 if (ret != 0) { 831 DRM_ERROR("Failed installing irq: %d\n", ret); 832 goto out_no_irq; 833 } 834 } 835 836 dev_priv->fman = vmw_fence_manager_init(dev_priv); 837 if (unlikely(dev_priv->fman == NULL)) { 838 ret = -ENOMEM; 839 goto out_no_fman; 840 } 841 842 ret = ttm_bo_device_init(&dev_priv->bdev, 843 dev_priv->bo_global_ref.ref.object, 844 &vmw_bo_driver, 845 dev->anon_inode->i_mapping, 846 VMWGFX_FILE_PAGE_OFFSET, 847 false); 848 if (unlikely(ret != 0)) { 849 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 850 goto out_no_bdev; 851 } 852 853 /* 854 * Enable VRAM, but initially don't use it until SVGA is enabled and 855 * unhidden. 856 */ 857 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 858 (dev_priv->vram_size >> PAGE_SHIFT)); 859 if (unlikely(ret != 0)) { 860 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 861 goto out_no_vram; 862 } 863 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 864 865 dev_priv->has_gmr = true; 866 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 867 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 868 VMW_PL_GMR) != 0) { 869 DRM_INFO("No GMR memory available. " 870 "Graphics memory resources are very limited.\n"); 871 dev_priv->has_gmr = false; 872 } 873 874 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 875 dev_priv->has_mob = true; 876 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 877 VMW_PL_MOB) != 0) { 878 DRM_INFO("No MOB memory available. " 879 "3D will be disabled.\n"); 880 dev_priv->has_mob = false; 881 } 882 } 883 884 if (dev_priv->has_mob) { 885 spin_lock(&dev_priv->cap_lock); 886 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DX); 887 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 888 spin_unlock(&dev_priv->cap_lock); 889 } 890 891 892 ret = vmw_kms_init(dev_priv); 893 if (unlikely(ret != 0)) 894 goto out_no_kms; 895 vmw_overlay_init(dev_priv); 896 897 ret = vmw_request_device(dev_priv); 898 if (ret) 899 goto out_no_fifo; 900 901 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 902 DRM_INFO("Atomic: %s\n", 903 (dev->driver->driver_features & DRIVER_ATOMIC) ? "yes" : "no"); 904 905 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 906 VMWGFX_REPO, VMWGFX_GIT_VERSION); 907 vmw_host_log(host_log); 908 909 memset(host_log, 0, sizeof(host_log)); 910 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 911 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 912 VMWGFX_DRIVER_PATCHLEVEL); 913 vmw_host_log(host_log); 914 915 if (dev_priv->enable_fb) { 916 vmw_fifo_resource_inc(dev_priv); 917 vmw_svga_enable(dev_priv); 918 vmw_fb_init(dev_priv); 919 } 920 921 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 922 register_pm_notifier(&dev_priv->pm_nb); 923 924 return 0; 925 926 out_no_fifo: 927 vmw_overlay_close(dev_priv); 928 vmw_kms_close(dev_priv); 929 out_no_kms: 930 if (dev_priv->has_mob) 931 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 932 if (dev_priv->has_gmr) 933 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 934 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 935 out_no_vram: 936 (void)ttm_bo_device_release(&dev_priv->bdev); 937 out_no_bdev: 938 vmw_fence_manager_takedown(dev_priv->fman); 939 out_no_fman: 940 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 941 vmw_irq_uninstall(dev_priv->dev); 942 out_no_irq: 943 if (dev_priv->stealth) 944 pci_release_region(dev->pdev, 2); 945 else 946 pci_release_regions(dev->pdev); 947 out_no_device: 948 ttm_object_device_release(&dev_priv->tdev); 949 out_err4: 950 memunmap(dev_priv->mmio_virt); 951 out_err3: 952 vmw_ttm_global_release(dev_priv); 953 out_err0: 954 for (i = vmw_res_context; i < vmw_res_max; ++i) 955 idr_destroy(&dev_priv->res_idr[i]); 956 957 if (dev_priv->ctx.staged_bindings) 958 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 959 kfree(dev_priv); 960 return ret; 961 } 962 963 static void vmw_driver_unload(struct drm_device *dev) 964 { 965 struct vmw_private *dev_priv = vmw_priv(dev); 966 enum vmw_res_type i; 967 968 unregister_pm_notifier(&dev_priv->pm_nb); 969 970 if (dev_priv->ctx.res_ht_initialized) 971 drm_ht_remove(&dev_priv->ctx.res_ht); 972 vfree(dev_priv->ctx.cmd_bounce); 973 if (dev_priv->enable_fb) { 974 vmw_fb_off(dev_priv); 975 vmw_fb_close(dev_priv); 976 vmw_fifo_resource_dec(dev_priv); 977 vmw_svga_disable(dev_priv); 978 } 979 980 vmw_kms_close(dev_priv); 981 vmw_overlay_close(dev_priv); 982 983 if (dev_priv->has_gmr) 984 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 985 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 986 987 vmw_release_device_early(dev_priv); 988 if (dev_priv->has_mob) 989 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 990 (void) ttm_bo_device_release(&dev_priv->bdev); 991 vmw_release_device_late(dev_priv); 992 vmw_fence_manager_takedown(dev_priv->fman); 993 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 994 vmw_irq_uninstall(dev_priv->dev); 995 if (dev_priv->stealth) 996 pci_release_region(dev->pdev, 2); 997 else 998 pci_release_regions(dev->pdev); 999 1000 ttm_object_device_release(&dev_priv->tdev); 1001 memunmap(dev_priv->mmio_virt); 1002 if (dev_priv->ctx.staged_bindings) 1003 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1004 vmw_ttm_global_release(dev_priv); 1005 1006 for (i = vmw_res_context; i < vmw_res_max; ++i) 1007 idr_destroy(&dev_priv->res_idr[i]); 1008 1009 kfree(dev_priv); 1010 } 1011 1012 static void vmw_postclose(struct drm_device *dev, 1013 struct drm_file *file_priv) 1014 { 1015 struct vmw_fpriv *vmw_fp; 1016 1017 vmw_fp = vmw_fpriv(file_priv); 1018 1019 if (vmw_fp->locked_master) { 1020 struct vmw_master *vmaster = 1021 vmw_master(vmw_fp->locked_master); 1022 1023 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1024 ttm_vt_unlock(&vmaster->lock); 1025 drm_master_put(&vmw_fp->locked_master); 1026 } 1027 1028 ttm_object_file_release(&vmw_fp->tfile); 1029 kfree(vmw_fp); 1030 } 1031 1032 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1033 { 1034 struct vmw_private *dev_priv = vmw_priv(dev); 1035 struct vmw_fpriv *vmw_fp; 1036 int ret = -ENOMEM; 1037 1038 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1039 if (unlikely(!vmw_fp)) 1040 return ret; 1041 1042 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1043 if (unlikely(vmw_fp->tfile == NULL)) 1044 goto out_no_tfile; 1045 1046 file_priv->driver_priv = vmw_fp; 1047 1048 return 0; 1049 1050 out_no_tfile: 1051 kfree(vmw_fp); 1052 return ret; 1053 } 1054 1055 static struct vmw_master *vmw_master_check(struct drm_device *dev, 1056 struct drm_file *file_priv, 1057 unsigned int flags) 1058 { 1059 int ret; 1060 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1061 struct vmw_master *vmaster; 1062 1063 if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH)) 1064 return NULL; 1065 1066 ret = mutex_lock_interruptible(&dev->master_mutex); 1067 if (unlikely(ret != 0)) 1068 return ERR_PTR(-ERESTARTSYS); 1069 1070 if (drm_is_current_master(file_priv)) { 1071 mutex_unlock(&dev->master_mutex); 1072 return NULL; 1073 } 1074 1075 /* 1076 * Check if we were previously master, but now dropped. In that 1077 * case, allow at least render node functionality. 1078 */ 1079 if (vmw_fp->locked_master) { 1080 mutex_unlock(&dev->master_mutex); 1081 1082 if (flags & DRM_RENDER_ALLOW) 1083 return NULL; 1084 1085 DRM_ERROR("Dropped master trying to access ioctl that " 1086 "requires authentication.\n"); 1087 return ERR_PTR(-EACCES); 1088 } 1089 mutex_unlock(&dev->master_mutex); 1090 1091 /* 1092 * Take the TTM lock. Possibly sleep waiting for the authenticating 1093 * master to become master again, or for a SIGTERM if the 1094 * authenticating master exits. 1095 */ 1096 vmaster = vmw_master(file_priv->master); 1097 ret = ttm_read_lock(&vmaster->lock, true); 1098 if (unlikely(ret != 0)) 1099 vmaster = ERR_PTR(ret); 1100 1101 return vmaster; 1102 } 1103 1104 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1105 unsigned long arg, 1106 long (*ioctl_func)(struct file *, unsigned int, 1107 unsigned long)) 1108 { 1109 struct drm_file *file_priv = filp->private_data; 1110 struct drm_device *dev = file_priv->minor->dev; 1111 unsigned int nr = DRM_IOCTL_NR(cmd); 1112 struct vmw_master *vmaster; 1113 unsigned int flags; 1114 long ret; 1115 1116 /* 1117 * Do extra checking on driver private ioctls. 1118 */ 1119 1120 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1121 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1122 const struct drm_ioctl_desc *ioctl = 1123 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1124 1125 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1126 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); 1127 if (unlikely(ret != 0)) 1128 return ret; 1129 1130 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) 1131 goto out_io_encoding; 1132 1133 return (long) vmw_execbuf_ioctl(dev, arg, file_priv, 1134 _IOC_SIZE(cmd)); 1135 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1136 if (!drm_is_current_master(file_priv) && 1137 !capable(CAP_SYS_ADMIN)) 1138 return -EACCES; 1139 } 1140 1141 if (unlikely(ioctl->cmd != cmd)) 1142 goto out_io_encoding; 1143 1144 flags = ioctl->flags; 1145 } else if (!drm_ioctl_flags(nr, &flags)) 1146 return -EINVAL; 1147 1148 vmaster = vmw_master_check(dev, file_priv, flags); 1149 if (IS_ERR(vmaster)) { 1150 ret = PTR_ERR(vmaster); 1151 1152 if (ret != -ERESTARTSYS) 1153 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", 1154 nr, ret); 1155 return ret; 1156 } 1157 1158 ret = ioctl_func(filp, cmd, arg); 1159 if (vmaster) 1160 ttm_read_unlock(&vmaster->lock); 1161 1162 return ret; 1163 1164 out_io_encoding: 1165 DRM_ERROR("Invalid command format, ioctl %d\n", 1166 nr - DRM_COMMAND_BASE); 1167 1168 return -EINVAL; 1169 } 1170 1171 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1172 unsigned long arg) 1173 { 1174 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1175 } 1176 1177 #ifdef CONFIG_COMPAT 1178 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1179 unsigned long arg) 1180 { 1181 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1182 } 1183 #endif 1184 1185 static void vmw_lastclose(struct drm_device *dev) 1186 { 1187 } 1188 1189 static void vmw_master_init(struct vmw_master *vmaster) 1190 { 1191 ttm_lock_init(&vmaster->lock); 1192 } 1193 1194 static int vmw_master_create(struct drm_device *dev, 1195 struct drm_master *master) 1196 { 1197 struct vmw_master *vmaster; 1198 1199 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); 1200 if (unlikely(!vmaster)) 1201 return -ENOMEM; 1202 1203 vmw_master_init(vmaster); 1204 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1205 master->driver_priv = vmaster; 1206 1207 return 0; 1208 } 1209 1210 static void vmw_master_destroy(struct drm_device *dev, 1211 struct drm_master *master) 1212 { 1213 struct vmw_master *vmaster = vmw_master(master); 1214 1215 master->driver_priv = NULL; 1216 kfree(vmaster); 1217 } 1218 1219 static int vmw_master_set(struct drm_device *dev, 1220 struct drm_file *file_priv, 1221 bool from_open) 1222 { 1223 struct vmw_private *dev_priv = vmw_priv(dev); 1224 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1225 struct vmw_master *active = dev_priv->active_master; 1226 struct vmw_master *vmaster = vmw_master(file_priv->master); 1227 int ret = 0; 1228 1229 if (active) { 1230 BUG_ON(active != &dev_priv->fbdev_master); 1231 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 1232 if (unlikely(ret != 0)) 1233 return ret; 1234 1235 ttm_lock_set_kill(&active->lock, true, SIGTERM); 1236 dev_priv->active_master = NULL; 1237 } 1238 1239 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1240 if (!from_open) { 1241 ttm_vt_unlock(&vmaster->lock); 1242 BUG_ON(vmw_fp->locked_master != file_priv->master); 1243 drm_master_put(&vmw_fp->locked_master); 1244 } 1245 1246 dev_priv->active_master = vmaster; 1247 drm_sysfs_hotplug_event(dev); 1248 1249 return 0; 1250 } 1251 1252 static void vmw_master_drop(struct drm_device *dev, 1253 struct drm_file *file_priv) 1254 { 1255 struct vmw_private *dev_priv = vmw_priv(dev); 1256 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1257 struct vmw_master *vmaster = vmw_master(file_priv->master); 1258 int ret; 1259 1260 /** 1261 * Make sure the master doesn't disappear while we have 1262 * it locked. 1263 */ 1264 1265 vmw_fp->locked_master = drm_master_get(file_priv->master); 1266 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 1267 vmw_kms_legacy_hotspot_clear(dev_priv); 1268 if (unlikely((ret != 0))) { 1269 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 1270 drm_master_put(&vmw_fp->locked_master); 1271 } 1272 1273 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1274 1275 if (!dev_priv->enable_fb) 1276 vmw_svga_disable(dev_priv); 1277 1278 dev_priv->active_master = &dev_priv->fbdev_master; 1279 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 1280 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 1281 1282 vmw_fb_refresh(dev_priv); 1283 } 1284 1285 /** 1286 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1287 * 1288 * @dev_priv: Pointer to device private struct. 1289 * Needs the reservation sem to be held in non-exclusive mode. 1290 */ 1291 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1292 { 1293 spin_lock(&dev_priv->svga_lock); 1294 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1295 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1296 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1297 } 1298 spin_unlock(&dev_priv->svga_lock); 1299 } 1300 1301 /** 1302 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1303 * 1304 * @dev_priv: Pointer to device private struct. 1305 */ 1306 void vmw_svga_enable(struct vmw_private *dev_priv) 1307 { 1308 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1309 __vmw_svga_enable(dev_priv); 1310 ttm_read_unlock(&dev_priv->reservation_sem); 1311 } 1312 1313 /** 1314 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1315 * 1316 * @dev_priv: Pointer to device private struct. 1317 * Needs the reservation sem to be held in exclusive mode. 1318 * Will not empty VRAM. VRAM must be emptied by caller. 1319 */ 1320 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1321 { 1322 spin_lock(&dev_priv->svga_lock); 1323 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1324 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1325 vmw_write(dev_priv, SVGA_REG_ENABLE, 1326 SVGA_REG_ENABLE_HIDE | 1327 SVGA_REG_ENABLE_ENABLE); 1328 } 1329 spin_unlock(&dev_priv->svga_lock); 1330 } 1331 1332 /** 1333 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1334 * running. 1335 * 1336 * @dev_priv: Pointer to device private struct. 1337 * Will empty VRAM. 1338 */ 1339 void vmw_svga_disable(struct vmw_private *dev_priv) 1340 { 1341 /* 1342 * Disabling SVGA will turn off device modesetting capabilities, so 1343 * notify KMS about that so that it doesn't cache atomic state that 1344 * isn't valid anymore, for example crtcs turned on. 1345 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1346 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1347 * end up with lock order reversal. Thus, a master may actually perform 1348 * a new modeset just after we call vmw_kms_lost_device() and race with 1349 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1350 * to be inconsistent with the device, causing modesetting problems. 1351 * 1352 */ 1353 vmw_kms_lost_device(dev_priv->dev); 1354 ttm_write_lock(&dev_priv->reservation_sem, false); 1355 spin_lock(&dev_priv->svga_lock); 1356 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1357 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1358 spin_unlock(&dev_priv->svga_lock); 1359 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1360 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1361 vmw_write(dev_priv, SVGA_REG_ENABLE, 1362 SVGA_REG_ENABLE_HIDE | 1363 SVGA_REG_ENABLE_ENABLE); 1364 } else 1365 spin_unlock(&dev_priv->svga_lock); 1366 ttm_write_unlock(&dev_priv->reservation_sem); 1367 } 1368 1369 static void vmw_remove(struct pci_dev *pdev) 1370 { 1371 struct drm_device *dev = pci_get_drvdata(pdev); 1372 1373 pci_disable_device(pdev); 1374 drm_put_dev(dev); 1375 } 1376 1377 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1378 void *ptr) 1379 { 1380 struct vmw_private *dev_priv = 1381 container_of(nb, struct vmw_private, pm_nb); 1382 1383 switch (val) { 1384 case PM_HIBERNATION_PREPARE: 1385 /* 1386 * Take the reservation sem in write mode, which will make sure 1387 * there are no other processes holding a buffer object 1388 * reservation, meaning we should be able to evict all buffer 1389 * objects if needed. 1390 * Once user-space processes have been frozen, we can release 1391 * the lock again. 1392 */ 1393 ttm_suspend_lock(&dev_priv->reservation_sem); 1394 dev_priv->suspend_locked = true; 1395 break; 1396 case PM_POST_HIBERNATION: 1397 case PM_POST_RESTORE: 1398 if (READ_ONCE(dev_priv->suspend_locked)) { 1399 dev_priv->suspend_locked = false; 1400 ttm_suspend_unlock(&dev_priv->reservation_sem); 1401 } 1402 break; 1403 default: 1404 break; 1405 } 1406 return 0; 1407 } 1408 1409 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1410 { 1411 struct drm_device *dev = pci_get_drvdata(pdev); 1412 struct vmw_private *dev_priv = vmw_priv(dev); 1413 1414 if (dev_priv->refuse_hibernation) 1415 return -EBUSY; 1416 1417 pci_save_state(pdev); 1418 pci_disable_device(pdev); 1419 pci_set_power_state(pdev, PCI_D3hot); 1420 return 0; 1421 } 1422 1423 static int vmw_pci_resume(struct pci_dev *pdev) 1424 { 1425 pci_set_power_state(pdev, PCI_D0); 1426 pci_restore_state(pdev); 1427 return pci_enable_device(pdev); 1428 } 1429 1430 static int vmw_pm_suspend(struct device *kdev) 1431 { 1432 struct pci_dev *pdev = to_pci_dev(kdev); 1433 struct pm_message dummy; 1434 1435 dummy.event = 0; 1436 1437 return vmw_pci_suspend(pdev, dummy); 1438 } 1439 1440 static int vmw_pm_resume(struct device *kdev) 1441 { 1442 struct pci_dev *pdev = to_pci_dev(kdev); 1443 1444 return vmw_pci_resume(pdev); 1445 } 1446 1447 static int vmw_pm_freeze(struct device *kdev) 1448 { 1449 struct pci_dev *pdev = to_pci_dev(kdev); 1450 struct drm_device *dev = pci_get_drvdata(pdev); 1451 struct vmw_private *dev_priv = vmw_priv(dev); 1452 int ret; 1453 1454 /* 1455 * Unlock for vmw_kms_suspend. 1456 * No user-space processes should be running now. 1457 */ 1458 ttm_suspend_unlock(&dev_priv->reservation_sem); 1459 ret = vmw_kms_suspend(dev_priv->dev); 1460 if (ret) { 1461 ttm_suspend_lock(&dev_priv->reservation_sem); 1462 DRM_ERROR("Failed to freeze modesetting.\n"); 1463 return ret; 1464 } 1465 if (dev_priv->enable_fb) 1466 vmw_fb_off(dev_priv); 1467 1468 ttm_suspend_lock(&dev_priv->reservation_sem); 1469 vmw_execbuf_release_pinned_bo(dev_priv); 1470 vmw_resource_evict_all(dev_priv); 1471 vmw_release_device_early(dev_priv); 1472 ttm_bo_swapout_all(&dev_priv->bdev); 1473 if (dev_priv->enable_fb) 1474 vmw_fifo_resource_dec(dev_priv); 1475 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1476 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1477 if (dev_priv->enable_fb) 1478 vmw_fifo_resource_inc(dev_priv); 1479 WARN_ON(vmw_request_device_late(dev_priv)); 1480 dev_priv->suspend_locked = false; 1481 ttm_suspend_unlock(&dev_priv->reservation_sem); 1482 if (dev_priv->suspend_state) 1483 vmw_kms_resume(dev); 1484 if (dev_priv->enable_fb) 1485 vmw_fb_on(dev_priv); 1486 vmw_fb_refresh(dev_priv); 1487 return -EBUSY; 1488 } 1489 1490 vmw_fence_fifo_down(dev_priv->fman); 1491 __vmw_svga_disable(dev_priv); 1492 1493 vmw_release_device_late(dev_priv); 1494 return 0; 1495 } 1496 1497 static int vmw_pm_restore(struct device *kdev) 1498 { 1499 struct pci_dev *pdev = to_pci_dev(kdev); 1500 struct drm_device *dev = pci_get_drvdata(pdev); 1501 struct vmw_private *dev_priv = vmw_priv(dev); 1502 int ret; 1503 1504 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1505 (void) vmw_read(dev_priv, SVGA_REG_ID); 1506 1507 if (dev_priv->enable_fb) 1508 vmw_fifo_resource_inc(dev_priv); 1509 1510 ret = vmw_request_device(dev_priv); 1511 if (ret) 1512 return ret; 1513 1514 if (dev_priv->enable_fb) 1515 __vmw_svga_enable(dev_priv); 1516 1517 vmw_fence_fifo_up(dev_priv->fman); 1518 dev_priv->suspend_locked = false; 1519 ttm_suspend_unlock(&dev_priv->reservation_sem); 1520 if (dev_priv->suspend_state) 1521 vmw_kms_resume(dev_priv->dev); 1522 1523 if (dev_priv->enable_fb) 1524 vmw_fb_on(dev_priv); 1525 1526 vmw_fb_refresh(dev_priv); 1527 1528 return 0; 1529 } 1530 1531 static const struct dev_pm_ops vmw_pm_ops = { 1532 .freeze = vmw_pm_freeze, 1533 .thaw = vmw_pm_restore, 1534 .restore = vmw_pm_restore, 1535 .suspend = vmw_pm_suspend, 1536 .resume = vmw_pm_resume, 1537 }; 1538 1539 static const struct file_operations vmwgfx_driver_fops = { 1540 .owner = THIS_MODULE, 1541 .open = drm_open, 1542 .release = drm_release, 1543 .unlocked_ioctl = vmw_unlocked_ioctl, 1544 .mmap = vmw_mmap, 1545 .poll = vmw_fops_poll, 1546 .read = vmw_fops_read, 1547 #if defined(CONFIG_COMPAT) 1548 .compat_ioctl = vmw_compat_ioctl, 1549 #endif 1550 .llseek = noop_llseek, 1551 }; 1552 1553 static struct drm_driver driver = { 1554 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | 1555 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC, 1556 .load = vmw_driver_load, 1557 .unload = vmw_driver_unload, 1558 .lastclose = vmw_lastclose, 1559 .get_vblank_counter = vmw_get_vblank_counter, 1560 .enable_vblank = vmw_enable_vblank, 1561 .disable_vblank = vmw_disable_vblank, 1562 .ioctls = vmw_ioctls, 1563 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1564 .master_create = vmw_master_create, 1565 .master_destroy = vmw_master_destroy, 1566 .master_set = vmw_master_set, 1567 .master_drop = vmw_master_drop, 1568 .open = vmw_driver_open, 1569 .postclose = vmw_postclose, 1570 1571 .dumb_create = vmw_dumb_create, 1572 .dumb_map_offset = vmw_dumb_map_offset, 1573 .dumb_destroy = vmw_dumb_destroy, 1574 1575 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1576 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1577 1578 .fops = &vmwgfx_driver_fops, 1579 .name = VMWGFX_DRIVER_NAME, 1580 .desc = VMWGFX_DRIVER_DESC, 1581 .date = VMWGFX_DRIVER_DATE, 1582 .major = VMWGFX_DRIVER_MAJOR, 1583 .minor = VMWGFX_DRIVER_MINOR, 1584 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1585 }; 1586 1587 static struct pci_driver vmw_pci_driver = { 1588 .name = VMWGFX_DRIVER_NAME, 1589 .id_table = vmw_pci_id_list, 1590 .probe = vmw_probe, 1591 .remove = vmw_remove, 1592 .driver = { 1593 .pm = &vmw_pm_ops 1594 } 1595 }; 1596 1597 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1598 { 1599 return drm_get_pci_dev(pdev, ent, &driver); 1600 } 1601 1602 static int __init vmwgfx_init(void) 1603 { 1604 int ret; 1605 1606 if (vgacon_text_force()) 1607 return -EINVAL; 1608 1609 ret = pci_register_driver(&vmw_pci_driver); 1610 if (ret) 1611 DRM_ERROR("Failed initializing DRM.\n"); 1612 return ret; 1613 } 1614 1615 static void __exit vmwgfx_exit(void) 1616 { 1617 pci_unregister_driver(&vmw_pci_driver); 1618 } 1619 1620 module_init(vmwgfx_init); 1621 module_exit(vmwgfx_exit); 1622 1623 MODULE_AUTHOR("VMware Inc. and others"); 1624 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1625 MODULE_LICENSE("GPL and additional rights"); 1626 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1627 __stringify(VMWGFX_DRIVER_MINOR) "." 1628 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1629 "0"); 1630