1 /************************************************************************** 2 * 3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include "drmP.h" 29 #include "vmwgfx_drv.h" 30 #include "ttm/ttm_placement.h" 31 #include "ttm/ttm_bo_driver.h" 32 #include "ttm/ttm_object.h" 33 #include "ttm/ttm_module.h" 34 35 #define VMWGFX_DRIVER_NAME "vmwgfx" 36 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 37 #define VMWGFX_CHIP_SVGAII 0 38 #define VMW_FB_RESERVATION 0 39 40 /** 41 * Fully encoded drm commands. Might move to vmw_drm.h 42 */ 43 44 #define DRM_IOCTL_VMW_GET_PARAM \ 45 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 46 struct drm_vmw_getparam_arg) 47 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 48 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 49 union drm_vmw_alloc_dmabuf_arg) 50 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 51 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 52 struct drm_vmw_unref_dmabuf_arg) 53 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 54 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 55 struct drm_vmw_cursor_bypass_arg) 56 57 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 58 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 59 struct drm_vmw_control_stream_arg) 60 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 61 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 62 struct drm_vmw_stream_arg) 63 #define DRM_IOCTL_VMW_UNREF_STREAM \ 64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 65 struct drm_vmw_stream_arg) 66 67 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 68 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 69 struct drm_vmw_context_arg) 70 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 71 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 72 struct drm_vmw_context_arg) 73 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 74 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 75 union drm_vmw_surface_create_arg) 76 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 78 struct drm_vmw_surface_arg) 79 #define DRM_IOCTL_VMW_REF_SURFACE \ 80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 81 union drm_vmw_surface_reference_arg) 82 #define DRM_IOCTL_VMW_EXECBUF \ 83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 84 struct drm_vmw_execbuf_arg) 85 #define DRM_IOCTL_VMW_FIFO_DEBUG \ 86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FIFO_DEBUG, \ 87 struct drm_vmw_fifo_debug_arg) 88 #define DRM_IOCTL_VMW_FENCE_WAIT \ 89 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 90 struct drm_vmw_fence_wait_arg) 91 92 93 /** 94 * The core DRM version of this macro doesn't account for 95 * DRM_COMMAND_BASE. 96 */ 97 98 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 99 [DRM_IOCTL_NR(ioctl) - DRM_COMMAND_BASE] = {ioctl, flags, func} 100 101 /** 102 * Ioctl definitions. 103 */ 104 105 static struct drm_ioctl_desc vmw_ioctls[] = { 106 VMW_IOCTL_DEF(DRM_IOCTL_VMW_GET_PARAM, vmw_getparam_ioctl, 107 DRM_AUTH | DRM_UNLOCKED), 108 VMW_IOCTL_DEF(DRM_IOCTL_VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, 109 DRM_AUTH | DRM_UNLOCKED), 110 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, 111 DRM_AUTH | DRM_UNLOCKED), 112 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CURSOR_BYPASS, 113 vmw_kms_cursor_bypass_ioctl, 114 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 115 116 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CONTROL_STREAM, vmw_overlay_ioctl, 117 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 118 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 119 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 120 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 121 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 122 123 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 124 DRM_AUTH | DRM_UNLOCKED), 125 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 126 DRM_AUTH | DRM_UNLOCKED), 127 VMW_IOCTL_DEF(DRM_IOCTL_VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 128 DRM_AUTH | DRM_UNLOCKED), 129 VMW_IOCTL_DEF(DRM_IOCTL_VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 130 DRM_AUTH | DRM_UNLOCKED), 131 VMW_IOCTL_DEF(DRM_IOCTL_VMW_REF_SURFACE, vmw_surface_reference_ioctl, 132 DRM_AUTH | DRM_UNLOCKED), 133 VMW_IOCTL_DEF(DRM_IOCTL_VMW_EXECBUF, vmw_execbuf_ioctl, 134 DRM_AUTH | DRM_UNLOCKED), 135 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl, 136 DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED), 137 VMW_IOCTL_DEF(DRM_IOCTL_VMW_FENCE_WAIT, vmw_fence_wait_ioctl, 138 DRM_AUTH | DRM_UNLOCKED) 139 }; 140 141 static struct pci_device_id vmw_pci_id_list[] = { 142 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 143 {0, 0, 0} 144 }; 145 146 static char *vmw_devname = "vmwgfx"; 147 148 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 149 static void vmw_master_init(struct vmw_master *); 150 151 static void vmw_print_capabilities(uint32_t capabilities) 152 { 153 DRM_INFO("Capabilities:\n"); 154 if (capabilities & SVGA_CAP_RECT_COPY) 155 DRM_INFO(" Rect copy.\n"); 156 if (capabilities & SVGA_CAP_CURSOR) 157 DRM_INFO(" Cursor.\n"); 158 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 159 DRM_INFO(" Cursor bypass.\n"); 160 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 161 DRM_INFO(" Cursor bypass 2.\n"); 162 if (capabilities & SVGA_CAP_8BIT_EMULATION) 163 DRM_INFO(" 8bit emulation.\n"); 164 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 165 DRM_INFO(" Alpha cursor.\n"); 166 if (capabilities & SVGA_CAP_3D) 167 DRM_INFO(" 3D.\n"); 168 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 169 DRM_INFO(" Extended Fifo.\n"); 170 if (capabilities & SVGA_CAP_MULTIMON) 171 DRM_INFO(" Multimon.\n"); 172 if (capabilities & SVGA_CAP_PITCHLOCK) 173 DRM_INFO(" Pitchlock.\n"); 174 if (capabilities & SVGA_CAP_IRQMASK) 175 DRM_INFO(" Irq mask.\n"); 176 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 177 DRM_INFO(" Display Topology.\n"); 178 if (capabilities & SVGA_CAP_GMR) 179 DRM_INFO(" GMR.\n"); 180 if (capabilities & SVGA_CAP_TRACES) 181 DRM_INFO(" Traces.\n"); 182 } 183 184 static int vmw_request_device(struct vmw_private *dev_priv) 185 { 186 int ret; 187 188 vmw_kms_save_vga(dev_priv); 189 190 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 191 if (unlikely(ret != 0)) { 192 DRM_ERROR("Unable to initialize FIFO.\n"); 193 return ret; 194 } 195 196 return 0; 197 } 198 199 static void vmw_release_device(struct vmw_private *dev_priv) 200 { 201 vmw_fifo_release(dev_priv, &dev_priv->fifo); 202 vmw_kms_restore_vga(dev_priv); 203 } 204 205 206 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 207 { 208 struct vmw_private *dev_priv; 209 int ret; 210 211 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 212 if (unlikely(dev_priv == NULL)) { 213 DRM_ERROR("Failed allocating a device private struct.\n"); 214 return -ENOMEM; 215 } 216 memset(dev_priv, 0, sizeof(*dev_priv)); 217 218 dev_priv->dev = dev; 219 dev_priv->vmw_chipset = chipset; 220 mutex_init(&dev_priv->hw_mutex); 221 mutex_init(&dev_priv->cmdbuf_mutex); 222 rwlock_init(&dev_priv->resource_lock); 223 idr_init(&dev_priv->context_idr); 224 idr_init(&dev_priv->surface_idr); 225 idr_init(&dev_priv->stream_idr); 226 ida_init(&dev_priv->gmr_ida); 227 mutex_init(&dev_priv->init_mutex); 228 init_waitqueue_head(&dev_priv->fence_queue); 229 init_waitqueue_head(&dev_priv->fifo_queue); 230 atomic_set(&dev_priv->fence_queue_waiters, 0); 231 atomic_set(&dev_priv->fifo_queue_waiters, 0); 232 INIT_LIST_HEAD(&dev_priv->gmr_lru); 233 234 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 235 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 236 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 237 238 mutex_lock(&dev_priv->hw_mutex); 239 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 240 241 if (dev_priv->capabilities & SVGA_CAP_GMR) { 242 dev_priv->max_gmr_descriptors = 243 vmw_read(dev_priv, 244 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH); 245 dev_priv->max_gmr_ids = 246 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 247 } 248 249 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 250 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 251 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 252 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 253 254 mutex_unlock(&dev_priv->hw_mutex); 255 256 vmw_print_capabilities(dev_priv->capabilities); 257 258 if (dev_priv->capabilities & SVGA_CAP_GMR) { 259 DRM_INFO("Max GMR ids is %u\n", 260 (unsigned)dev_priv->max_gmr_ids); 261 DRM_INFO("Max GMR descriptors is %u\n", 262 (unsigned)dev_priv->max_gmr_descriptors); 263 } 264 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 265 dev_priv->vram_start, dev_priv->vram_size / 1024); 266 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 267 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 268 269 ret = vmw_ttm_global_init(dev_priv); 270 if (unlikely(ret != 0)) 271 goto out_err0; 272 273 274 vmw_master_init(&dev_priv->fbdev_master); 275 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 276 dev_priv->active_master = &dev_priv->fbdev_master; 277 278 279 ret = ttm_bo_device_init(&dev_priv->bdev, 280 dev_priv->bo_global_ref.ref.object, 281 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET, 282 false); 283 if (unlikely(ret != 0)) { 284 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 285 goto out_err1; 286 } 287 288 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 289 (dev_priv->vram_size >> PAGE_SHIFT)); 290 if (unlikely(ret != 0)) { 291 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 292 goto out_err2; 293 } 294 295 dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start, 296 dev_priv->mmio_size, DRM_MTRR_WC); 297 298 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, 299 dev_priv->mmio_size); 300 301 if (unlikely(dev_priv->mmio_virt == NULL)) { 302 ret = -ENOMEM; 303 DRM_ERROR("Failed mapping MMIO.\n"); 304 goto out_err3; 305 } 306 307 dev_priv->tdev = ttm_object_device_init 308 (dev_priv->mem_global_ref.object, 12); 309 310 if (unlikely(dev_priv->tdev == NULL)) { 311 DRM_ERROR("Unable to initialize TTM object management.\n"); 312 ret = -ENOMEM; 313 goto out_err4; 314 } 315 316 dev->dev_private = dev_priv; 317 318 if (!dev->devname) 319 dev->devname = vmw_devname; 320 321 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 322 ret = drm_irq_install(dev); 323 if (unlikely(ret != 0)) { 324 DRM_ERROR("Failed installing irq: %d\n", ret); 325 goto out_no_irq; 326 } 327 } 328 329 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 330 dev_priv->stealth = (ret != 0); 331 if (dev_priv->stealth) { 332 /** 333 * Request at least the mmio PCI resource. 334 */ 335 336 DRM_INFO("It appears like vesafb is loaded. " 337 "Ignore above error if any. Entering stealth mode.\n"); 338 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 339 if (unlikely(ret != 0)) { 340 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 341 goto out_no_device; 342 } 343 vmw_kms_init(dev_priv); 344 vmw_overlay_init(dev_priv); 345 } else { 346 ret = vmw_request_device(dev_priv); 347 if (unlikely(ret != 0)) 348 goto out_no_device; 349 vmw_kms_init(dev_priv); 350 vmw_overlay_init(dev_priv); 351 vmw_fb_init(dev_priv); 352 } 353 354 return 0; 355 356 out_no_device: 357 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 358 drm_irq_uninstall(dev_priv->dev); 359 if (dev->devname == vmw_devname) 360 dev->devname = NULL; 361 out_no_irq: 362 ttm_object_device_release(&dev_priv->tdev); 363 out_err4: 364 iounmap(dev_priv->mmio_virt); 365 out_err3: 366 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start, 367 dev_priv->mmio_size, DRM_MTRR_WC); 368 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 369 out_err2: 370 (void)ttm_bo_device_release(&dev_priv->bdev); 371 out_err1: 372 vmw_ttm_global_release(dev_priv); 373 out_err0: 374 ida_destroy(&dev_priv->gmr_ida); 375 idr_destroy(&dev_priv->surface_idr); 376 idr_destroy(&dev_priv->context_idr); 377 idr_destroy(&dev_priv->stream_idr); 378 kfree(dev_priv); 379 return ret; 380 } 381 382 static int vmw_driver_unload(struct drm_device *dev) 383 { 384 struct vmw_private *dev_priv = vmw_priv(dev); 385 386 DRM_INFO(VMWGFX_DRIVER_NAME " unload.\n"); 387 388 if (!dev_priv->stealth) { 389 vmw_fb_close(dev_priv); 390 vmw_kms_close(dev_priv); 391 vmw_overlay_close(dev_priv); 392 vmw_release_device(dev_priv); 393 pci_release_regions(dev->pdev); 394 } else { 395 vmw_kms_close(dev_priv); 396 vmw_overlay_close(dev_priv); 397 pci_release_region(dev->pdev, 2); 398 } 399 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 400 drm_irq_uninstall(dev_priv->dev); 401 if (dev->devname == vmw_devname) 402 dev->devname = NULL; 403 ttm_object_device_release(&dev_priv->tdev); 404 iounmap(dev_priv->mmio_virt); 405 drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start, 406 dev_priv->mmio_size, DRM_MTRR_WC); 407 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 408 (void)ttm_bo_device_release(&dev_priv->bdev); 409 vmw_ttm_global_release(dev_priv); 410 ida_destroy(&dev_priv->gmr_ida); 411 idr_destroy(&dev_priv->surface_idr); 412 idr_destroy(&dev_priv->context_idr); 413 idr_destroy(&dev_priv->stream_idr); 414 415 kfree(dev_priv); 416 417 return 0; 418 } 419 420 static void vmw_postclose(struct drm_device *dev, 421 struct drm_file *file_priv) 422 { 423 struct vmw_fpriv *vmw_fp; 424 425 vmw_fp = vmw_fpriv(file_priv); 426 ttm_object_file_release(&vmw_fp->tfile); 427 if (vmw_fp->locked_master) 428 drm_master_put(&vmw_fp->locked_master); 429 kfree(vmw_fp); 430 } 431 432 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 433 { 434 struct vmw_private *dev_priv = vmw_priv(dev); 435 struct vmw_fpriv *vmw_fp; 436 int ret = -ENOMEM; 437 438 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 439 if (unlikely(vmw_fp == NULL)) 440 return ret; 441 442 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 443 if (unlikely(vmw_fp->tfile == NULL)) 444 goto out_no_tfile; 445 446 file_priv->driver_priv = vmw_fp; 447 448 if (unlikely(dev_priv->bdev.dev_mapping == NULL)) 449 dev_priv->bdev.dev_mapping = 450 file_priv->filp->f_path.dentry->d_inode->i_mapping; 451 452 return 0; 453 454 out_no_tfile: 455 kfree(vmw_fp); 456 return ret; 457 } 458 459 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 460 unsigned long arg) 461 { 462 struct drm_file *file_priv = filp->private_data; 463 struct drm_device *dev = file_priv->minor->dev; 464 unsigned int nr = DRM_IOCTL_NR(cmd); 465 466 /* 467 * Do extra checking on driver private ioctls. 468 */ 469 470 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 471 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 472 struct drm_ioctl_desc *ioctl = 473 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 474 475 if (unlikely(ioctl->cmd != cmd)) { 476 DRM_ERROR("Invalid command format, ioctl %d\n", 477 nr - DRM_COMMAND_BASE); 478 return -EINVAL; 479 } 480 } 481 482 return drm_ioctl(filp, cmd, arg); 483 } 484 485 static int vmw_firstopen(struct drm_device *dev) 486 { 487 struct vmw_private *dev_priv = vmw_priv(dev); 488 dev_priv->is_opened = true; 489 490 return 0; 491 } 492 493 static void vmw_lastclose(struct drm_device *dev) 494 { 495 struct vmw_private *dev_priv = vmw_priv(dev); 496 struct drm_crtc *crtc; 497 struct drm_mode_set set; 498 int ret; 499 500 /** 501 * Do nothing on the lastclose call from drm_unload. 502 */ 503 504 if (!dev_priv->is_opened) 505 return; 506 507 dev_priv->is_opened = false; 508 set.x = 0; 509 set.y = 0; 510 set.fb = NULL; 511 set.mode = NULL; 512 set.connectors = NULL; 513 set.num_connectors = 0; 514 515 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 516 set.crtc = crtc; 517 ret = crtc->funcs->set_config(&set); 518 WARN_ON(ret != 0); 519 } 520 521 } 522 523 static void vmw_master_init(struct vmw_master *vmaster) 524 { 525 ttm_lock_init(&vmaster->lock); 526 } 527 528 static int vmw_master_create(struct drm_device *dev, 529 struct drm_master *master) 530 { 531 struct vmw_master *vmaster; 532 533 DRM_INFO("Master create.\n"); 534 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); 535 if (unlikely(vmaster == NULL)) 536 return -ENOMEM; 537 538 ttm_lock_init(&vmaster->lock); 539 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 540 master->driver_priv = vmaster; 541 542 return 0; 543 } 544 545 static void vmw_master_destroy(struct drm_device *dev, 546 struct drm_master *master) 547 { 548 struct vmw_master *vmaster = vmw_master(master); 549 550 DRM_INFO("Master destroy.\n"); 551 master->driver_priv = NULL; 552 kfree(vmaster); 553 } 554 555 556 static int vmw_master_set(struct drm_device *dev, 557 struct drm_file *file_priv, 558 bool from_open) 559 { 560 struct vmw_private *dev_priv = vmw_priv(dev); 561 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 562 struct vmw_master *active = dev_priv->active_master; 563 struct vmw_master *vmaster = vmw_master(file_priv->master); 564 int ret = 0; 565 566 DRM_INFO("Master set.\n"); 567 if (dev_priv->stealth) { 568 ret = vmw_request_device(dev_priv); 569 if (unlikely(ret != 0)) 570 return ret; 571 } 572 573 if (active) { 574 BUG_ON(active != &dev_priv->fbdev_master); 575 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 576 if (unlikely(ret != 0)) 577 goto out_no_active_lock; 578 579 ttm_lock_set_kill(&active->lock, true, SIGTERM); 580 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); 581 if (unlikely(ret != 0)) { 582 DRM_ERROR("Unable to clean VRAM on " 583 "master drop.\n"); 584 } 585 586 dev_priv->active_master = NULL; 587 } 588 589 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 590 if (!from_open) { 591 ttm_vt_unlock(&vmaster->lock); 592 BUG_ON(vmw_fp->locked_master != file_priv->master); 593 drm_master_put(&vmw_fp->locked_master); 594 } 595 596 dev_priv->active_master = vmaster; 597 598 return 0; 599 600 out_no_active_lock: 601 vmw_release_device(dev_priv); 602 return ret; 603 } 604 605 static void vmw_master_drop(struct drm_device *dev, 606 struct drm_file *file_priv, 607 bool from_release) 608 { 609 struct vmw_private *dev_priv = vmw_priv(dev); 610 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 611 struct vmw_master *vmaster = vmw_master(file_priv->master); 612 int ret; 613 614 DRM_INFO("Master drop.\n"); 615 616 /** 617 * Make sure the master doesn't disappear while we have 618 * it locked. 619 */ 620 621 vmw_fp->locked_master = drm_master_get(file_priv->master); 622 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 623 624 if (unlikely((ret != 0))) { 625 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 626 drm_master_put(&vmw_fp->locked_master); 627 } 628 629 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 630 631 if (dev_priv->stealth) { 632 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); 633 if (unlikely(ret != 0)) 634 DRM_ERROR("Unable to clean VRAM on master drop.\n"); 635 vmw_release_device(dev_priv); 636 } 637 dev_priv->active_master = &dev_priv->fbdev_master; 638 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 639 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 640 641 if (!dev_priv->stealth) 642 vmw_fb_on(dev_priv); 643 } 644 645 646 static void vmw_remove(struct pci_dev *pdev) 647 { 648 struct drm_device *dev = pci_get_drvdata(pdev); 649 650 drm_put_dev(dev); 651 } 652 653 static struct drm_driver driver = { 654 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | 655 DRIVER_MODESET, 656 .load = vmw_driver_load, 657 .unload = vmw_driver_unload, 658 .firstopen = vmw_firstopen, 659 .lastclose = vmw_lastclose, 660 .irq_preinstall = vmw_irq_preinstall, 661 .irq_postinstall = vmw_irq_postinstall, 662 .irq_uninstall = vmw_irq_uninstall, 663 .irq_handler = vmw_irq_handler, 664 .reclaim_buffers_locked = NULL, 665 .get_map_ofs = drm_core_get_map_ofs, 666 .get_reg_ofs = drm_core_get_reg_ofs, 667 .ioctls = vmw_ioctls, 668 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls), 669 .dma_quiescent = NULL, /*vmw_dma_quiescent, */ 670 .master_create = vmw_master_create, 671 .master_destroy = vmw_master_destroy, 672 .master_set = vmw_master_set, 673 .master_drop = vmw_master_drop, 674 .open = vmw_driver_open, 675 .postclose = vmw_postclose, 676 .fops = { 677 .owner = THIS_MODULE, 678 .open = drm_open, 679 .release = drm_release, 680 .unlocked_ioctl = vmw_unlocked_ioctl, 681 .mmap = vmw_mmap, 682 .poll = drm_poll, 683 .fasync = drm_fasync, 684 #if defined(CONFIG_COMPAT) 685 .compat_ioctl = drm_compat_ioctl, 686 #endif 687 }, 688 .pci_driver = { 689 .name = VMWGFX_DRIVER_NAME, 690 .id_table = vmw_pci_id_list, 691 .probe = vmw_probe, 692 .remove = vmw_remove 693 }, 694 .name = VMWGFX_DRIVER_NAME, 695 .desc = VMWGFX_DRIVER_DESC, 696 .date = VMWGFX_DRIVER_DATE, 697 .major = VMWGFX_DRIVER_MAJOR, 698 .minor = VMWGFX_DRIVER_MINOR, 699 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 700 }; 701 702 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 703 { 704 return drm_get_dev(pdev, ent, &driver); 705 } 706 707 static int __init vmwgfx_init(void) 708 { 709 int ret; 710 ret = drm_init(&driver); 711 if (ret) 712 DRM_ERROR("Failed initializing DRM.\n"); 713 return ret; 714 } 715 716 static void __exit vmwgfx_exit(void) 717 { 718 drm_exit(&driver); 719 } 720 721 module_init(vmwgfx_init); 722 module_exit(vmwgfx_exit); 723 724 MODULE_AUTHOR("VMware Inc. and others"); 725 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 726 MODULE_LICENSE("GPL and additional rights"); 727