1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2022 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29 #include "vmwgfx_drv.h" 30 31 #include "vmwgfx_devcaps.h" 32 #include "vmwgfx_mksstat.h" 33 #include "vmwgfx_binding.h" 34 #include "ttm_object.h" 35 36 #include <drm/drm_aperture.h> 37 #include <drm/drm_drv.h> 38 #include <drm/drm_fbdev_generic.h> 39 #include <drm/drm_gem_ttm_helper.h> 40 #include <drm/drm_ioctl.h> 41 #include <drm/drm_module.h> 42 #include <drm/drm_sysfs.h> 43 #include <drm/ttm/ttm_range_manager.h> 44 #include <drm/ttm/ttm_placement.h> 45 #include <generated/utsrelease.h> 46 47 #include <linux/cc_platform.h> 48 #include <linux/dma-mapping.h> 49 #include <linux/module.h> 50 #include <linux/pci.h> 51 #include <linux/version.h> 52 53 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 54 55 /* 56 * Fully encoded drm commands. Might move to vmw_drm.h 57 */ 58 59 #define DRM_IOCTL_VMW_GET_PARAM \ 60 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 61 struct drm_vmw_getparam_arg) 62 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 63 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 64 union drm_vmw_alloc_dmabuf_arg) 65 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 66 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 67 struct drm_vmw_unref_dmabuf_arg) 68 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 69 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 70 struct drm_vmw_cursor_bypass_arg) 71 72 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 73 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 74 struct drm_vmw_control_stream_arg) 75 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 76 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 77 struct drm_vmw_stream_arg) 78 #define DRM_IOCTL_VMW_UNREF_STREAM \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 80 struct drm_vmw_stream_arg) 81 82 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 83 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 84 struct drm_vmw_context_arg) 85 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 86 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 87 struct drm_vmw_context_arg) 88 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 89 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 90 union drm_vmw_surface_create_arg) 91 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 93 struct drm_vmw_surface_arg) 94 #define DRM_IOCTL_VMW_REF_SURFACE \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 96 union drm_vmw_surface_reference_arg) 97 #define DRM_IOCTL_VMW_EXECBUF \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 99 struct drm_vmw_execbuf_arg) 100 #define DRM_IOCTL_VMW_GET_3D_CAP \ 101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 102 struct drm_vmw_get_3d_cap_arg) 103 #define DRM_IOCTL_VMW_FENCE_WAIT \ 104 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 105 struct drm_vmw_fence_wait_arg) 106 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 107 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 108 struct drm_vmw_fence_signaled_arg) 109 #define DRM_IOCTL_VMW_FENCE_UNREF \ 110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 111 struct drm_vmw_fence_arg) 112 #define DRM_IOCTL_VMW_FENCE_EVENT \ 113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 114 struct drm_vmw_fence_event_arg) 115 #define DRM_IOCTL_VMW_PRESENT \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 117 struct drm_vmw_present_arg) 118 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 120 struct drm_vmw_present_readback_arg) 121 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 123 struct drm_vmw_update_layout_arg) 124 #define DRM_IOCTL_VMW_CREATE_SHADER \ 125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 126 struct drm_vmw_shader_create_arg) 127 #define DRM_IOCTL_VMW_UNREF_SHADER \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 129 struct drm_vmw_shader_arg) 130 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 132 union drm_vmw_gb_surface_create_arg) 133 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 134 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 135 union drm_vmw_gb_surface_reference_arg) 136 #define DRM_IOCTL_VMW_SYNCCPU \ 137 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 138 struct drm_vmw_synccpu_arg) 139 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 141 struct drm_vmw_context_arg) 142 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 143 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 144 union drm_vmw_gb_surface_create_ext_arg) 145 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 147 union drm_vmw_gb_surface_reference_ext_arg) 148 #define DRM_IOCTL_VMW_MSG \ 149 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 150 struct drm_vmw_msg_arg) 151 #define DRM_IOCTL_VMW_MKSSTAT_RESET \ 152 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) 153 #define DRM_IOCTL_VMW_MKSSTAT_ADD \ 154 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ 155 struct drm_vmw_mksstat_add_arg) 156 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ 157 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ 158 struct drm_vmw_mksstat_remove_arg) 159 160 /* 161 * Ioctl definitions. 162 */ 163 164 static const struct drm_ioctl_desc vmw_ioctls[] = { 165 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, 166 DRM_RENDER_ALLOW), 167 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, 168 DRM_RENDER_ALLOW), 169 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 170 DRM_RENDER_ALLOW), 171 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, 172 vmw_kms_cursor_bypass_ioctl, 173 DRM_MASTER), 174 175 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 176 DRM_MASTER), 177 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 178 DRM_MASTER), 179 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 180 DRM_MASTER), 181 182 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 183 DRM_RENDER_ALLOW), 184 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 185 DRM_RENDER_ALLOW), 186 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 187 DRM_RENDER_ALLOW), 188 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 189 DRM_RENDER_ALLOW), 190 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 191 DRM_RENDER_ALLOW), 192 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, 193 DRM_RENDER_ALLOW), 194 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 195 DRM_RENDER_ALLOW), 196 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, 197 vmw_fence_obj_signaled_ioctl, 198 DRM_RENDER_ALLOW), 199 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 200 DRM_RENDER_ALLOW), 201 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 202 DRM_RENDER_ALLOW), 203 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 204 DRM_RENDER_ALLOW), 205 206 /* these allow direct access to the framebuffers mark as master only */ 207 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, 208 DRM_MASTER | DRM_AUTH), 209 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, 210 vmw_present_readback_ioctl, 211 DRM_MASTER | DRM_AUTH), 212 /* 213 * The permissions of the below ioctl are overridden in 214 * vmw_generic_ioctl(). We require either 215 * DRM_MASTER or capable(CAP_SYS_ADMIN). 216 */ 217 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, 218 vmw_kms_update_layout_ioctl, 219 DRM_RENDER_ALLOW), 220 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, 221 vmw_shader_define_ioctl, 222 DRM_RENDER_ALLOW), 223 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, 224 vmw_shader_destroy_ioctl, 225 DRM_RENDER_ALLOW), 226 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, 227 vmw_gb_surface_define_ioctl, 228 DRM_RENDER_ALLOW), 229 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, 230 vmw_gb_surface_reference_ioctl, 231 DRM_RENDER_ALLOW), 232 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, 233 vmw_user_bo_synccpu_ioctl, 234 DRM_RENDER_ALLOW), 235 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, 236 vmw_extended_context_define_ioctl, 237 DRM_RENDER_ALLOW), 238 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, 239 vmw_gb_surface_define_ext_ioctl, 240 DRM_RENDER_ALLOW), 241 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, 242 vmw_gb_surface_reference_ext_ioctl, 243 DRM_RENDER_ALLOW), 244 DRM_IOCTL_DEF_DRV(VMW_MSG, 245 vmw_msg_ioctl, 246 DRM_RENDER_ALLOW), 247 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, 248 vmw_mksstat_reset_ioctl, 249 DRM_RENDER_ALLOW), 250 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, 251 vmw_mksstat_add_ioctl, 252 DRM_RENDER_ALLOW), 253 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, 254 vmw_mksstat_remove_ioctl, 255 DRM_RENDER_ALLOW), 256 }; 257 258 static const struct pci_device_id vmw_pci_id_list[] = { 259 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, 260 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, 261 { } 262 }; 263 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 264 265 static int vmw_restrict_iommu; 266 static int vmw_force_coherent; 267 static int vmw_restrict_dma_mask; 268 static int vmw_assume_16bpp; 269 270 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 271 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 272 void *ptr); 273 274 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 275 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 276 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 277 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 278 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 279 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 280 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 281 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 282 283 284 struct bitmap_name { 285 uint32 value; 286 const char *name; 287 }; 288 289 static const struct bitmap_name cap1_names[] = { 290 { SVGA_CAP_RECT_COPY, "rect copy" }, 291 { SVGA_CAP_CURSOR, "cursor" }, 292 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, 293 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, 294 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, 295 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, 296 { SVGA_CAP_3D, "3D" }, 297 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, 298 { SVGA_CAP_MULTIMON, "multimon" }, 299 { SVGA_CAP_PITCHLOCK, "pitchlock" }, 300 { SVGA_CAP_IRQMASK, "irq mask" }, 301 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, 302 { SVGA_CAP_GMR, "gmr" }, 303 { SVGA_CAP_TRACES, "traces" }, 304 { SVGA_CAP_GMR2, "gmr2" }, 305 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, 306 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, 307 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, 308 { SVGA_CAP_GBOBJECTS, "gbobject" }, 309 { SVGA_CAP_DX, "dx" }, 310 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, 311 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, 312 { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, 313 }; 314 315 316 static const struct bitmap_name cap2_names[] = { 317 { SVGA_CAP2_GROW_OTABLE, "grow otable" }, 318 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, 319 { SVGA_CAP2_DX2, "dx2" }, 320 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, 321 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, 322 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, 323 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, 324 { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, 325 { SVGA_CAP2_MSHINT, "mshint" }, 326 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, 327 { SVGA_CAP2_DX3, "dx3" }, 328 { SVGA_CAP2_FRAME_TYPE, "frame type" }, 329 { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, 330 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, 331 { SVGA_CAP2_EXTRA_REGS, "extra regs" }, 332 { SVGA_CAP2_LO_STAGING, "lo staging" }, 333 }; 334 335 static void vmw_print_bitmap(struct drm_device *drm, 336 const char *prefix, uint32_t bitmap, 337 const struct bitmap_name *bnames, 338 uint32_t num_names) 339 { 340 char buf[512]; 341 uint32_t i; 342 uint32_t offset = 0; 343 for (i = 0; i < num_names; ++i) { 344 if ((bitmap & bnames[i].value) != 0) { 345 offset += snprintf(buf + offset, 346 ARRAY_SIZE(buf) - offset, 347 "%s, ", bnames[i].name); 348 bitmap &= ~bnames[i].value; 349 } 350 } 351 352 drm_info(drm, "%s: %s\n", prefix, buf); 353 if (bitmap != 0) 354 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap); 355 } 356 357 358 static void vmw_print_sm_type(struct vmw_private *dev_priv) 359 { 360 static const char *names[] = { 361 [VMW_SM_LEGACY] = "Legacy", 362 [VMW_SM_4] = "SM4", 363 [VMW_SM_4_1] = "SM4_1", 364 [VMW_SM_5] = "SM_5", 365 [VMW_SM_5_1X] = "SM_5_1X", 366 [VMW_SM_MAX] = "Invalid" 367 }; 368 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); 369 drm_info(&dev_priv->drm, "Available shader model: %s.\n", 370 names[dev_priv->sm_type]); 371 } 372 373 /** 374 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 375 * 376 * @dev_priv: A device private structure. 377 * 378 * This function creates a small buffer object that holds the query 379 * result for dummy queries emitted as query barriers. 380 * The function will then map the first page and initialize a pending 381 * occlusion query result structure, Finally it will unmap the buffer. 382 * No interruptible waits are done within this function. 383 * 384 * Returns an error if bo creation or initialization fails. 385 */ 386 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 387 { 388 int ret; 389 struct vmw_buffer_object *vbo; 390 struct ttm_bo_kmap_obj map; 391 volatile SVGA3dQueryResult *result; 392 bool dummy; 393 394 /* 395 * Create the vbo as pinned, so that a tryreserve will 396 * immediately succeed. This is because we're the only 397 * user of the bo currently. 398 */ 399 ret = vmw_bo_create(dev_priv, PAGE_SIZE, 400 &vmw_sys_placement, false, true, 401 &vmw_bo_bo_free, &vbo); 402 if (unlikely(ret != 0)) 403 return ret; 404 405 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 406 BUG_ON(ret != 0); 407 vmw_bo_pin_reserved(vbo, true); 408 409 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 410 if (likely(ret == 0)) { 411 result = ttm_kmap_obj_virtual(&map, &dummy); 412 result->totalSize = sizeof(*result); 413 result->state = SVGA3D_QUERYSTATE_PENDING; 414 result->result32 = 0xff; 415 ttm_bo_kunmap(&map); 416 } 417 vmw_bo_pin_reserved(vbo, false); 418 ttm_bo_unreserve(&vbo->base); 419 420 if (unlikely(ret != 0)) { 421 DRM_ERROR("Dummy query buffer map failed.\n"); 422 vmw_bo_unreference(&vbo); 423 } else 424 dev_priv->dummy_query_bo = vbo; 425 426 return ret; 427 } 428 429 static int vmw_device_init(struct vmw_private *dev_priv) 430 { 431 bool uses_fb_traces = false; 432 433 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 434 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 435 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 436 437 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | 438 SVGA_REG_ENABLE_HIDE); 439 440 uses_fb_traces = !vmw_cmd_supported(dev_priv) && 441 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; 442 443 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); 444 dev_priv->fifo = vmw_fifo_create(dev_priv); 445 if (IS_ERR(dev_priv->fifo)) { 446 int err = PTR_ERR(dev_priv->fifo); 447 dev_priv->fifo = NULL; 448 return err; 449 } else if (!dev_priv->fifo) { 450 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); 451 } 452 453 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); 454 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); 455 return 0; 456 } 457 458 static void vmw_device_fini(struct vmw_private *vmw) 459 { 460 /* 461 * Legacy sync 462 */ 463 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 464 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) 465 ; 466 467 vmw->last_read_seqno = vmw_fence_read(vmw); 468 469 vmw_write(vmw, SVGA_REG_CONFIG_DONE, 470 vmw->config_done_state); 471 vmw_write(vmw, SVGA_REG_ENABLE, 472 vmw->enable_state); 473 vmw_write(vmw, SVGA_REG_TRACES, 474 vmw->traces_state); 475 476 vmw_fifo_destroy(vmw); 477 } 478 479 /** 480 * vmw_request_device_late - Perform late device setup 481 * 482 * @dev_priv: Pointer to device private. 483 * 484 * This function performs setup of otables and enables large command 485 * buffer submission. These tasks are split out to a separate function 486 * because it reverts vmw_release_device_early and is intended to be used 487 * by an error path in the hibernation code. 488 */ 489 static int vmw_request_device_late(struct vmw_private *dev_priv) 490 { 491 int ret; 492 493 if (dev_priv->has_mob) { 494 ret = vmw_otables_setup(dev_priv); 495 if (unlikely(ret != 0)) { 496 DRM_ERROR("Unable to initialize " 497 "guest Memory OBjects.\n"); 498 return ret; 499 } 500 } 501 502 if (dev_priv->cman) { 503 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096); 504 if (ret) { 505 struct vmw_cmdbuf_man *man = dev_priv->cman; 506 507 dev_priv->cman = NULL; 508 vmw_cmdbuf_man_destroy(man); 509 } 510 } 511 512 return 0; 513 } 514 515 static int vmw_request_device(struct vmw_private *dev_priv) 516 { 517 int ret; 518 519 ret = vmw_device_init(dev_priv); 520 if (unlikely(ret != 0)) { 521 DRM_ERROR("Unable to initialize the device.\n"); 522 return ret; 523 } 524 vmw_fence_fifo_up(dev_priv->fman); 525 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 526 if (IS_ERR(dev_priv->cman)) { 527 dev_priv->cman = NULL; 528 dev_priv->sm_type = VMW_SM_LEGACY; 529 } 530 531 ret = vmw_request_device_late(dev_priv); 532 if (ret) 533 goto out_no_mob; 534 535 ret = vmw_dummy_query_bo_create(dev_priv); 536 if (unlikely(ret != 0)) 537 goto out_no_query_bo; 538 539 return 0; 540 541 out_no_query_bo: 542 if (dev_priv->cman) 543 vmw_cmdbuf_remove_pool(dev_priv->cman); 544 if (dev_priv->has_mob) { 545 struct ttm_resource_manager *man; 546 547 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 548 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 549 vmw_otables_takedown(dev_priv); 550 } 551 if (dev_priv->cman) 552 vmw_cmdbuf_man_destroy(dev_priv->cman); 553 out_no_mob: 554 vmw_fence_fifo_down(dev_priv->fman); 555 vmw_device_fini(dev_priv); 556 return ret; 557 } 558 559 /** 560 * vmw_release_device_early - Early part of fifo takedown. 561 * 562 * @dev_priv: Pointer to device private struct. 563 * 564 * This is the first part of command submission takedown, to be called before 565 * buffer management is taken down. 566 */ 567 static void vmw_release_device_early(struct vmw_private *dev_priv) 568 { 569 /* 570 * Previous destructions should've released 571 * the pinned bo. 572 */ 573 574 BUG_ON(dev_priv->pinned_bo != NULL); 575 576 vmw_bo_unreference(&dev_priv->dummy_query_bo); 577 if (dev_priv->cman) 578 vmw_cmdbuf_remove_pool(dev_priv->cman); 579 580 if (dev_priv->has_mob) { 581 struct ttm_resource_manager *man; 582 583 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 584 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 585 vmw_otables_takedown(dev_priv); 586 } 587 } 588 589 /** 590 * vmw_release_device_late - Late part of fifo takedown. 591 * 592 * @dev_priv: Pointer to device private struct. 593 * 594 * This is the last part of the command submission takedown, to be called when 595 * command submission is no longer needed. It may wait on pending fences. 596 */ 597 static void vmw_release_device_late(struct vmw_private *dev_priv) 598 { 599 vmw_fence_fifo_down(dev_priv->fman); 600 if (dev_priv->cman) 601 vmw_cmdbuf_man_destroy(dev_priv->cman); 602 603 vmw_device_fini(dev_priv); 604 } 605 606 /* 607 * Sets the initial_[width|height] fields on the given vmw_private. 608 * 609 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 610 * clamping the value to fb_max_[width|height] fields and the 611 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 612 * If the values appear to be invalid, set them to 613 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 614 */ 615 static void vmw_get_initial_size(struct vmw_private *dev_priv) 616 { 617 uint32_t width; 618 uint32_t height; 619 620 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 621 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 622 623 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH); 624 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT); 625 626 if (width > dev_priv->fb_max_width || 627 height > dev_priv->fb_max_height) { 628 629 /* 630 * This is a host error and shouldn't occur. 631 */ 632 633 width = VMWGFX_MIN_INITIAL_WIDTH; 634 height = VMWGFX_MIN_INITIAL_HEIGHT; 635 } 636 637 dev_priv->initial_width = width; 638 dev_priv->initial_height = height; 639 } 640 641 /** 642 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 643 * system. 644 * 645 * @dev_priv: Pointer to a struct vmw_private 646 * 647 * This functions tries to determine what actions need to be taken by the 648 * driver to make system pages visible to the device. 649 * If this function decides that DMA is not possible, it returns -EINVAL. 650 * The driver may then try to disable features of the device that require 651 * DMA. 652 */ 653 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 654 { 655 static const char *names[vmw_dma_map_max] = { 656 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 657 [vmw_dma_map_populate] = "Caching DMA mappings.", 658 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 659 660 /* TTM currently doesn't fully support SEV encryption. */ 661 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT)) 662 return -EINVAL; 663 664 if (vmw_force_coherent) 665 dev_priv->map_mode = vmw_dma_alloc_coherent; 666 else if (vmw_restrict_iommu) 667 dev_priv->map_mode = vmw_dma_map_bind; 668 else 669 dev_priv->map_mode = vmw_dma_map_populate; 670 671 drm_info(&dev_priv->drm, 672 "DMA map mode: %s\n", names[dev_priv->map_mode]); 673 return 0; 674 } 675 676 /** 677 * vmw_dma_masks - set required page- and dma masks 678 * 679 * @dev_priv: Pointer to struct drm-device 680 * 681 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 682 * restriction also for 64-bit systems. 683 */ 684 static int vmw_dma_masks(struct vmw_private *dev_priv) 685 { 686 struct drm_device *dev = &dev_priv->drm; 687 int ret = 0; 688 689 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 690 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { 691 drm_info(&dev_priv->drm, 692 "Restricting DMA addresses to 44 bits.\n"); 693 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 694 } 695 696 return ret; 697 } 698 699 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 700 { 701 int ret; 702 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 703 dev_priv->vram_size >> PAGE_SHIFT); 704 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 705 return ret; 706 } 707 708 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 709 { 710 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 711 } 712 713 static int vmw_setup_pci_resources(struct vmw_private *dev, 714 u32 pci_id) 715 { 716 resource_size_t rmmio_start; 717 resource_size_t rmmio_size; 718 resource_size_t fifo_start; 719 resource_size_t fifo_size; 720 int ret; 721 struct pci_dev *pdev = to_pci_dev(dev->drm.dev); 722 723 pci_set_master(pdev); 724 725 ret = pci_request_regions(pdev, "vmwgfx probe"); 726 if (ret) 727 return ret; 728 729 dev->pci_id = pci_id; 730 if (pci_id == VMWGFX_PCI_ID_SVGA3) { 731 rmmio_start = pci_resource_start(pdev, 0); 732 rmmio_size = pci_resource_len(pdev, 0); 733 dev->vram_start = pci_resource_start(pdev, 2); 734 dev->vram_size = pci_resource_len(pdev, 2); 735 736 drm_info(&dev->drm, 737 "Register MMIO at 0x%pa size is %llu kiB\n", 738 &rmmio_start, (uint64_t)rmmio_size / 1024); 739 dev->rmmio = devm_ioremap(dev->drm.dev, 740 rmmio_start, 741 rmmio_size); 742 if (!dev->rmmio) { 743 drm_err(&dev->drm, 744 "Failed mapping registers mmio memory.\n"); 745 pci_release_regions(pdev); 746 return -ENOMEM; 747 } 748 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { 749 dev->io_start = pci_resource_start(pdev, 0); 750 dev->vram_start = pci_resource_start(pdev, 1); 751 dev->vram_size = pci_resource_len(pdev, 1); 752 fifo_start = pci_resource_start(pdev, 2); 753 fifo_size = pci_resource_len(pdev, 2); 754 755 drm_info(&dev->drm, 756 "FIFO at %pa size is %llu kiB\n", 757 &fifo_start, (uint64_t)fifo_size / 1024); 758 dev->fifo_mem = devm_memremap(dev->drm.dev, 759 fifo_start, 760 fifo_size, 761 MEMREMAP_WB); 762 763 if (IS_ERR(dev->fifo_mem)) { 764 drm_err(&dev->drm, 765 "Failed mapping FIFO memory.\n"); 766 pci_release_regions(pdev); 767 return PTR_ERR(dev->fifo_mem); 768 } 769 } else { 770 pci_release_regions(pdev); 771 return -EINVAL; 772 } 773 774 /* 775 * This is approximate size of the vram, the exact size will only 776 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource 777 * size will be equal to or bigger than the size reported by 778 * SVGA_REG_VRAM_SIZE. 779 */ 780 drm_info(&dev->drm, 781 "VRAM at %pa size is %llu kiB\n", 782 &dev->vram_start, (uint64_t)dev->vram_size / 1024); 783 784 return 0; 785 } 786 787 static int vmw_detect_version(struct vmw_private *dev) 788 { 789 uint32_t svga_id; 790 791 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? 792 SVGA_ID_3 : SVGA_ID_2); 793 svga_id = vmw_read(dev, SVGA_REG_ID); 794 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { 795 drm_err(&dev->drm, 796 "Unsupported SVGA ID 0x%x on chipset 0x%x\n", 797 svga_id, dev->pci_id); 798 return -ENOSYS; 799 } 800 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); 801 drm_info(&dev->drm, 802 "Running on SVGA version %d.\n", (svga_id & 0xff)); 803 return 0; 804 } 805 806 static void vmw_write_driver_id(struct vmw_private *dev) 807 { 808 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) { 809 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 810 SVGA_REG_GUEST_DRIVER_ID_LINUX); 811 812 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1, 813 LINUX_VERSION_MAJOR << 24 | 814 LINUX_VERSION_PATCHLEVEL << 16 | 815 LINUX_VERSION_SUBLEVEL); 816 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2, 817 VMWGFX_DRIVER_MAJOR << 24 | 818 VMWGFX_DRIVER_MINOR << 16 | 819 VMWGFX_DRIVER_PATCHLEVEL); 820 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0); 821 822 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 823 SVGA_REG_GUEST_DRIVER_ID_SUBMIT); 824 } 825 } 826 827 static void vmw_sw_context_init(struct vmw_private *dev_priv) 828 { 829 struct vmw_sw_context *sw_context = &dev_priv->ctx; 830 831 hash_init(sw_context->res_ht); 832 } 833 834 static void vmw_sw_context_fini(struct vmw_private *dev_priv) 835 { 836 struct vmw_sw_context *sw_context = &dev_priv->ctx; 837 838 vfree(sw_context->cmd_bounce); 839 if (sw_context->staged_bindings) 840 vmw_binding_state_free(sw_context->staged_bindings); 841 } 842 843 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 844 { 845 int ret; 846 enum vmw_res_type i; 847 bool refuse_dma = false; 848 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 849 850 dev_priv->drm.dev_private = dev_priv; 851 852 vmw_sw_context_init(dev_priv); 853 854 mutex_init(&dev_priv->cmdbuf_mutex); 855 mutex_init(&dev_priv->binding_mutex); 856 spin_lock_init(&dev_priv->resource_lock); 857 spin_lock_init(&dev_priv->hw_lock); 858 spin_lock_init(&dev_priv->waiter_lock); 859 spin_lock_init(&dev_priv->cursor_lock); 860 861 ret = vmw_setup_pci_resources(dev_priv, pci_id); 862 if (ret) 863 return ret; 864 ret = vmw_detect_version(dev_priv); 865 if (ret) 866 goto out_no_pci_or_version; 867 868 869 for (i = vmw_res_context; i < vmw_res_max; ++i) { 870 idr_init_base(&dev_priv->res_idr[i], 1); 871 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 872 } 873 874 init_waitqueue_head(&dev_priv->fence_queue); 875 init_waitqueue_head(&dev_priv->fifo_queue); 876 dev_priv->fence_queue_waiters = 0; 877 dev_priv->fifo_queue_waiters = 0; 878 879 dev_priv->used_memory_size = 0; 880 881 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 882 883 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 884 vmw_print_bitmap(&dev_priv->drm, "Capabilities", 885 dev_priv->capabilities, 886 cap1_names, ARRAY_SIZE(cap1_names)); 887 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 888 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 889 vmw_print_bitmap(&dev_priv->drm, "Capabilities2", 890 dev_priv->capabilities2, 891 cap2_names, ARRAY_SIZE(cap2_names)); 892 } 893 894 ret = vmw_dma_select_mode(dev_priv); 895 if (unlikely(ret != 0)) { 896 drm_info(&dev_priv->drm, 897 "Restricting capabilities since DMA not available.\n"); 898 refuse_dma = true; 899 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 900 drm_info(&dev_priv->drm, 901 "Disabling 3D acceleration.\n"); 902 } 903 904 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 905 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 906 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 907 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 908 909 vmw_get_initial_size(dev_priv); 910 911 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 912 dev_priv->max_gmr_ids = 913 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 914 dev_priv->max_gmr_pages = 915 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 916 dev_priv->memory_size = 917 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 918 dev_priv->memory_size -= dev_priv->vram_size; 919 } else { 920 /* 921 * An arbitrary limit of 512MiB on surface 922 * memory. But all HWV8 hardware supports GMR2. 923 */ 924 dev_priv->memory_size = 512*1024*1024; 925 } 926 dev_priv->max_mob_pages = 0; 927 dev_priv->max_mob_size = 0; 928 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 929 uint64_t mem_size; 930 931 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 932 mem_size = vmw_read(dev_priv, 933 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 934 else 935 mem_size = 936 vmw_read(dev_priv, 937 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 938 939 /* 940 * Workaround for low memory 2D VMs to compensate for the 941 * allocation taken by fbdev 942 */ 943 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 944 mem_size *= 3; 945 946 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 947 dev_priv->max_primary_mem = 948 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM); 949 dev_priv->max_mob_size = 950 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 951 dev_priv->stdu_max_width = 952 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 953 dev_priv->stdu_max_height = 954 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 955 956 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 957 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 958 dev_priv->texture_max_width = vmw_read(dev_priv, 959 SVGA_REG_DEV_CAP); 960 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 961 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 962 dev_priv->texture_max_height = vmw_read(dev_priv, 963 SVGA_REG_DEV_CAP); 964 } else { 965 dev_priv->texture_max_width = 8192; 966 dev_priv->texture_max_height = 8192; 967 dev_priv->max_primary_mem = dev_priv->vram_size; 968 } 969 drm_info(&dev_priv->drm, 970 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n", 971 (u64)dev_priv->vram_size / 1024, 972 (u64)dev_priv->fifo_mem_size / 1024, 973 dev_priv->memory_size / 1024); 974 975 drm_info(&dev_priv->drm, 976 "MOB limits: max mob size = %u kB, max mob pages = %u\n", 977 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); 978 979 ret = vmw_dma_masks(dev_priv); 980 if (unlikely(ret != 0)) 981 goto out_err0; 982 983 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX); 984 985 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 986 drm_info(&dev_priv->drm, 987 "Max GMR ids is %u\n", 988 (unsigned)dev_priv->max_gmr_ids); 989 drm_info(&dev_priv->drm, 990 "Max number of GMR pages is %u\n", 991 (unsigned)dev_priv->max_gmr_pages); 992 } 993 drm_info(&dev_priv->drm, 994 "Maximum display memory size is %llu kiB\n", 995 (uint64_t)dev_priv->max_primary_mem / 1024); 996 997 /* Need mmio memory to check for fifo pitchlock cap. */ 998 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 999 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 1000 !vmw_fifo_have_pitchlock(dev_priv)) { 1001 ret = -ENOSYS; 1002 DRM_ERROR("Hardware has no pitchlock\n"); 1003 goto out_err0; 1004 } 1005 1006 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops); 1007 1008 if (unlikely(dev_priv->tdev == NULL)) { 1009 drm_err(&dev_priv->drm, 1010 "Unable to initialize TTM object management.\n"); 1011 ret = -ENOMEM; 1012 goto out_err0; 1013 } 1014 1015 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 1016 ret = vmw_irq_install(dev_priv); 1017 if (ret != 0) { 1018 drm_err(&dev_priv->drm, 1019 "Failed installing irq: %d\n", ret); 1020 goto out_no_irq; 1021 } 1022 } 1023 1024 dev_priv->fman = vmw_fence_manager_init(dev_priv); 1025 if (unlikely(dev_priv->fman == NULL)) { 1026 ret = -ENOMEM; 1027 goto out_no_fman; 1028 } 1029 1030 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver, 1031 dev_priv->drm.dev, 1032 dev_priv->drm.anon_inode->i_mapping, 1033 dev_priv->drm.vma_offset_manager, 1034 dev_priv->map_mode == vmw_dma_alloc_coherent, 1035 false); 1036 if (unlikely(ret != 0)) { 1037 drm_err(&dev_priv->drm, 1038 "Failed initializing TTM buffer object driver.\n"); 1039 goto out_no_bdev; 1040 } 1041 1042 /* 1043 * Enable VRAM, but initially don't use it until SVGA is enabled and 1044 * unhidden. 1045 */ 1046 1047 ret = vmw_vram_manager_init(dev_priv); 1048 if (unlikely(ret != 0)) { 1049 drm_err(&dev_priv->drm, 1050 "Failed initializing memory manager for VRAM.\n"); 1051 goto out_no_vram; 1052 } 1053 1054 ret = vmw_devcaps_create(dev_priv); 1055 if (unlikely(ret != 0)) { 1056 drm_err(&dev_priv->drm, 1057 "Failed initializing device caps.\n"); 1058 goto out_no_vram; 1059 } 1060 1061 /* 1062 * "Guest Memory Regions" is an aperture like feature with 1063 * one slot per bo. There is an upper limit of the number of 1064 * slots as well as the bo size. 1065 */ 1066 dev_priv->has_gmr = true; 1067 /* TODO: This is most likely not correct */ 1068 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 1069 refuse_dma || 1070 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 1071 drm_info(&dev_priv->drm, 1072 "No GMR memory available. " 1073 "Graphics memory resources are very limited.\n"); 1074 dev_priv->has_gmr = false; 1075 } 1076 1077 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 1078 dev_priv->has_mob = true; 1079 1080 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 1081 drm_info(&dev_priv->drm, 1082 "No MOB memory available. " 1083 "3D will be disabled.\n"); 1084 dev_priv->has_mob = false; 1085 } 1086 if (vmw_sys_man_init(dev_priv) != 0) { 1087 drm_info(&dev_priv->drm, 1088 "No MOB page table memory available. " 1089 "3D will be disabled.\n"); 1090 dev_priv->has_mob = false; 1091 } 1092 } 1093 1094 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 1095 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) 1096 dev_priv->sm_type = VMW_SM_4; 1097 } 1098 1099 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 1100 if (has_sm4_context(dev_priv) && 1101 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 1102 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41)) 1103 dev_priv->sm_type = VMW_SM_4_1; 1104 if (has_sm4_1_context(dev_priv) && 1105 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 1106 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) { 1107 dev_priv->sm_type = VMW_SM_5; 1108 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43)) 1109 dev_priv->sm_type = VMW_SM_5_1X; 1110 } 1111 } 1112 } 1113 1114 ret = vmw_kms_init(dev_priv); 1115 if (unlikely(ret != 0)) 1116 goto out_no_kms; 1117 vmw_overlay_init(dev_priv); 1118 1119 ret = vmw_request_device(dev_priv); 1120 if (ret) 1121 goto out_no_fifo; 1122 1123 vmw_print_sm_type(dev_priv); 1124 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)", 1125 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 1126 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); 1127 vmw_write_driver_id(dev_priv); 1128 1129 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 1130 register_pm_notifier(&dev_priv->pm_nb); 1131 1132 return 0; 1133 1134 out_no_fifo: 1135 vmw_overlay_close(dev_priv); 1136 vmw_kms_close(dev_priv); 1137 out_no_kms: 1138 if (dev_priv->has_mob) { 1139 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1140 vmw_sys_man_fini(dev_priv); 1141 } 1142 if (dev_priv->has_gmr) 1143 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1144 vmw_devcaps_destroy(dev_priv); 1145 vmw_vram_manager_fini(dev_priv); 1146 out_no_vram: 1147 ttm_device_fini(&dev_priv->bdev); 1148 out_no_bdev: 1149 vmw_fence_manager_takedown(dev_priv->fman); 1150 out_no_fman: 1151 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1152 vmw_irq_uninstall(&dev_priv->drm); 1153 out_no_irq: 1154 ttm_object_device_release(&dev_priv->tdev); 1155 out_err0: 1156 for (i = vmw_res_context; i < vmw_res_max; ++i) 1157 idr_destroy(&dev_priv->res_idr[i]); 1158 1159 if (dev_priv->ctx.staged_bindings) 1160 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1161 out_no_pci_or_version: 1162 pci_release_regions(pdev); 1163 return ret; 1164 } 1165 1166 static void vmw_driver_unload(struct drm_device *dev) 1167 { 1168 struct vmw_private *dev_priv = vmw_priv(dev); 1169 struct pci_dev *pdev = to_pci_dev(dev->dev); 1170 enum vmw_res_type i; 1171 1172 unregister_pm_notifier(&dev_priv->pm_nb); 1173 1174 vmw_sw_context_fini(dev_priv); 1175 vmw_fifo_resource_dec(dev_priv); 1176 1177 vmw_svga_disable(dev_priv); 1178 1179 vmw_kms_close(dev_priv); 1180 vmw_overlay_close(dev_priv); 1181 1182 if (dev_priv->has_gmr) 1183 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1184 1185 vmw_release_device_early(dev_priv); 1186 if (dev_priv->has_mob) { 1187 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1188 vmw_sys_man_fini(dev_priv); 1189 } 1190 vmw_devcaps_destroy(dev_priv); 1191 vmw_vram_manager_fini(dev_priv); 1192 ttm_device_fini(&dev_priv->bdev); 1193 vmw_release_device_late(dev_priv); 1194 vmw_fence_manager_takedown(dev_priv->fman); 1195 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1196 vmw_irq_uninstall(&dev_priv->drm); 1197 1198 ttm_object_device_release(&dev_priv->tdev); 1199 1200 for (i = vmw_res_context; i < vmw_res_max; ++i) 1201 idr_destroy(&dev_priv->res_idr[i]); 1202 1203 vmw_mksstat_remove_all(dev_priv); 1204 1205 pci_release_regions(pdev); 1206 } 1207 1208 static void vmw_postclose(struct drm_device *dev, 1209 struct drm_file *file_priv) 1210 { 1211 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1212 1213 ttm_object_file_release(&vmw_fp->tfile); 1214 kfree(vmw_fp); 1215 } 1216 1217 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1218 { 1219 struct vmw_private *dev_priv = vmw_priv(dev); 1220 struct vmw_fpriv *vmw_fp; 1221 int ret = -ENOMEM; 1222 1223 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1224 if (unlikely(!vmw_fp)) 1225 return ret; 1226 1227 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev); 1228 if (unlikely(vmw_fp->tfile == NULL)) 1229 goto out_no_tfile; 1230 1231 file_priv->driver_priv = vmw_fp; 1232 1233 return 0; 1234 1235 out_no_tfile: 1236 kfree(vmw_fp); 1237 return ret; 1238 } 1239 1240 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1241 unsigned long arg, 1242 long (*ioctl_func)(struct file *, unsigned int, 1243 unsigned long)) 1244 { 1245 struct drm_file *file_priv = filp->private_data; 1246 struct drm_device *dev = file_priv->minor->dev; 1247 unsigned int nr = DRM_IOCTL_NR(cmd); 1248 unsigned int flags; 1249 1250 /* 1251 * Do extra checking on driver private ioctls. 1252 */ 1253 1254 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1255 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1256 const struct drm_ioctl_desc *ioctl = 1257 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1258 1259 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1260 return ioctl_func(filp, cmd, arg); 1261 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1262 if (!drm_is_current_master(file_priv) && 1263 !capable(CAP_SYS_ADMIN)) 1264 return -EACCES; 1265 } 1266 1267 if (unlikely(ioctl->cmd != cmd)) 1268 goto out_io_encoding; 1269 1270 flags = ioctl->flags; 1271 } else if (!drm_ioctl_flags(nr, &flags)) 1272 return -EINVAL; 1273 1274 return ioctl_func(filp, cmd, arg); 1275 1276 out_io_encoding: 1277 DRM_ERROR("Invalid command format, ioctl %d\n", 1278 nr - DRM_COMMAND_BASE); 1279 1280 return -EINVAL; 1281 } 1282 1283 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1284 unsigned long arg) 1285 { 1286 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1287 } 1288 1289 #ifdef CONFIG_COMPAT 1290 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1291 unsigned long arg) 1292 { 1293 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1294 } 1295 #endif 1296 1297 static void vmw_master_set(struct drm_device *dev, 1298 struct drm_file *file_priv, 1299 bool from_open) 1300 { 1301 /* 1302 * Inform a new master that the layout may have changed while 1303 * it was gone. 1304 */ 1305 if (!from_open) 1306 drm_sysfs_hotplug_event(dev); 1307 } 1308 1309 static void vmw_master_drop(struct drm_device *dev, 1310 struct drm_file *file_priv) 1311 { 1312 struct vmw_private *dev_priv = vmw_priv(dev); 1313 1314 vmw_kms_legacy_hotspot_clear(dev_priv); 1315 } 1316 1317 /** 1318 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1319 * 1320 * @dev_priv: Pointer to device private struct. 1321 * Needs the reservation sem to be held in non-exclusive mode. 1322 */ 1323 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1324 { 1325 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1326 1327 if (!ttm_resource_manager_used(man)) { 1328 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE); 1329 ttm_resource_manager_set_used(man, true); 1330 } 1331 } 1332 1333 /** 1334 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1335 * 1336 * @dev_priv: Pointer to device private struct. 1337 */ 1338 void vmw_svga_enable(struct vmw_private *dev_priv) 1339 { 1340 __vmw_svga_enable(dev_priv); 1341 } 1342 1343 /** 1344 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1345 * 1346 * @dev_priv: Pointer to device private struct. 1347 * Needs the reservation sem to be held in exclusive mode. 1348 * Will not empty VRAM. VRAM must be emptied by caller. 1349 */ 1350 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1351 { 1352 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1353 1354 if (ttm_resource_manager_used(man)) { 1355 ttm_resource_manager_set_used(man, false); 1356 vmw_write(dev_priv, SVGA_REG_ENABLE, 1357 SVGA_REG_ENABLE_HIDE | 1358 SVGA_REG_ENABLE_ENABLE); 1359 } 1360 } 1361 1362 /** 1363 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1364 * running. 1365 * 1366 * @dev_priv: Pointer to device private struct. 1367 * Will empty VRAM. 1368 */ 1369 void vmw_svga_disable(struct vmw_private *dev_priv) 1370 { 1371 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1372 /* 1373 * Disabling SVGA will turn off device modesetting capabilities, so 1374 * notify KMS about that so that it doesn't cache atomic state that 1375 * isn't valid anymore, for example crtcs turned on. 1376 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1377 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1378 * end up with lock order reversal. Thus, a master may actually perform 1379 * a new modeset just after we call vmw_kms_lost_device() and race with 1380 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1381 * to be inconsistent with the device, causing modesetting problems. 1382 * 1383 */ 1384 vmw_kms_lost_device(&dev_priv->drm); 1385 if (ttm_resource_manager_used(man)) { 1386 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1387 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1388 ttm_resource_manager_set_used(man, false); 1389 vmw_write(dev_priv, SVGA_REG_ENABLE, 1390 SVGA_REG_ENABLE_HIDE | 1391 SVGA_REG_ENABLE_ENABLE); 1392 } 1393 } 1394 1395 static void vmw_remove(struct pci_dev *pdev) 1396 { 1397 struct drm_device *dev = pci_get_drvdata(pdev); 1398 1399 drm_dev_unregister(dev); 1400 vmw_driver_unload(dev); 1401 } 1402 1403 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw) 1404 { 1405 struct drm_minor *minor = vmw->drm.primary; 1406 struct dentry *root = minor->debugfs_root; 1407 1408 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM), 1409 root, "system_ttm"); 1410 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM), 1411 root, "vram_ttm"); 1412 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR), 1413 root, "gmr_ttm"); 1414 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB), 1415 root, "mob_ttm"); 1416 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM), 1417 root, "system_mob_ttm"); 1418 } 1419 1420 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1421 void *ptr) 1422 { 1423 struct vmw_private *dev_priv = 1424 container_of(nb, struct vmw_private, pm_nb); 1425 1426 switch (val) { 1427 case PM_HIBERNATION_PREPARE: 1428 /* 1429 * Take the reservation sem in write mode, which will make sure 1430 * there are no other processes holding a buffer object 1431 * reservation, meaning we should be able to evict all buffer 1432 * objects if needed. 1433 * Once user-space processes have been frozen, we can release 1434 * the lock again. 1435 */ 1436 dev_priv->suspend_locked = true; 1437 break; 1438 case PM_POST_HIBERNATION: 1439 case PM_POST_RESTORE: 1440 if (READ_ONCE(dev_priv->suspend_locked)) { 1441 dev_priv->suspend_locked = false; 1442 } 1443 break; 1444 default: 1445 break; 1446 } 1447 return 0; 1448 } 1449 1450 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1451 { 1452 struct drm_device *dev = pci_get_drvdata(pdev); 1453 struct vmw_private *dev_priv = vmw_priv(dev); 1454 1455 if (dev_priv->refuse_hibernation) 1456 return -EBUSY; 1457 1458 pci_save_state(pdev); 1459 pci_disable_device(pdev); 1460 pci_set_power_state(pdev, PCI_D3hot); 1461 return 0; 1462 } 1463 1464 static int vmw_pci_resume(struct pci_dev *pdev) 1465 { 1466 pci_set_power_state(pdev, PCI_D0); 1467 pci_restore_state(pdev); 1468 return pci_enable_device(pdev); 1469 } 1470 1471 static int vmw_pm_suspend(struct device *kdev) 1472 { 1473 struct pci_dev *pdev = to_pci_dev(kdev); 1474 struct pm_message dummy; 1475 1476 dummy.event = 0; 1477 1478 return vmw_pci_suspend(pdev, dummy); 1479 } 1480 1481 static int vmw_pm_resume(struct device *kdev) 1482 { 1483 struct pci_dev *pdev = to_pci_dev(kdev); 1484 1485 return vmw_pci_resume(pdev); 1486 } 1487 1488 static int vmw_pm_freeze(struct device *kdev) 1489 { 1490 struct pci_dev *pdev = to_pci_dev(kdev); 1491 struct drm_device *dev = pci_get_drvdata(pdev); 1492 struct vmw_private *dev_priv = vmw_priv(dev); 1493 struct ttm_operation_ctx ctx = { 1494 .interruptible = false, 1495 .no_wait_gpu = false 1496 }; 1497 int ret; 1498 1499 /* 1500 * No user-space processes should be running now. 1501 */ 1502 ret = vmw_kms_suspend(&dev_priv->drm); 1503 if (ret) { 1504 DRM_ERROR("Failed to freeze modesetting.\n"); 1505 return ret; 1506 } 1507 1508 vmw_execbuf_release_pinned_bo(dev_priv); 1509 vmw_resource_evict_all(dev_priv); 1510 vmw_release_device_early(dev_priv); 1511 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0); 1512 vmw_fifo_resource_dec(dev_priv); 1513 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1514 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1515 vmw_fifo_resource_inc(dev_priv); 1516 WARN_ON(vmw_request_device_late(dev_priv)); 1517 dev_priv->suspend_locked = false; 1518 if (dev_priv->suspend_state) 1519 vmw_kms_resume(dev); 1520 return -EBUSY; 1521 } 1522 1523 vmw_fence_fifo_down(dev_priv->fman); 1524 __vmw_svga_disable(dev_priv); 1525 1526 vmw_release_device_late(dev_priv); 1527 return 0; 1528 } 1529 1530 static int vmw_pm_restore(struct device *kdev) 1531 { 1532 struct pci_dev *pdev = to_pci_dev(kdev); 1533 struct drm_device *dev = pci_get_drvdata(pdev); 1534 struct vmw_private *dev_priv = vmw_priv(dev); 1535 int ret; 1536 1537 vmw_detect_version(dev_priv); 1538 1539 vmw_fifo_resource_inc(dev_priv); 1540 1541 ret = vmw_request_device(dev_priv); 1542 if (ret) 1543 return ret; 1544 1545 __vmw_svga_enable(dev_priv); 1546 1547 vmw_fence_fifo_up(dev_priv->fman); 1548 dev_priv->suspend_locked = false; 1549 if (dev_priv->suspend_state) 1550 vmw_kms_resume(&dev_priv->drm); 1551 1552 return 0; 1553 } 1554 1555 static const struct dev_pm_ops vmw_pm_ops = { 1556 .freeze = vmw_pm_freeze, 1557 .thaw = vmw_pm_restore, 1558 .restore = vmw_pm_restore, 1559 .suspend = vmw_pm_suspend, 1560 .resume = vmw_pm_resume, 1561 }; 1562 1563 static const struct file_operations vmwgfx_driver_fops = { 1564 .owner = THIS_MODULE, 1565 .open = drm_open, 1566 .release = drm_release, 1567 .unlocked_ioctl = vmw_unlocked_ioctl, 1568 .mmap = vmw_mmap, 1569 .poll = drm_poll, 1570 .read = drm_read, 1571 #if defined(CONFIG_COMPAT) 1572 .compat_ioctl = vmw_compat_ioctl, 1573 #endif 1574 .llseek = noop_llseek, 1575 }; 1576 1577 static const struct drm_driver driver = { 1578 .driver_features = 1579 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM, 1580 .ioctls = vmw_ioctls, 1581 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1582 .master_set = vmw_master_set, 1583 .master_drop = vmw_master_drop, 1584 .open = vmw_driver_open, 1585 .postclose = vmw_postclose, 1586 1587 .dumb_create = vmw_dumb_create, 1588 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1589 1590 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1591 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1592 1593 .fops = &vmwgfx_driver_fops, 1594 .name = VMWGFX_DRIVER_NAME, 1595 .desc = VMWGFX_DRIVER_DESC, 1596 .date = VMWGFX_DRIVER_DATE, 1597 .major = VMWGFX_DRIVER_MAJOR, 1598 .minor = VMWGFX_DRIVER_MINOR, 1599 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1600 }; 1601 1602 static struct pci_driver vmw_pci_driver = { 1603 .name = VMWGFX_DRIVER_NAME, 1604 .id_table = vmw_pci_id_list, 1605 .probe = vmw_probe, 1606 .remove = vmw_remove, 1607 .driver = { 1608 .pm = &vmw_pm_ops 1609 } 1610 }; 1611 1612 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1613 { 1614 struct vmw_private *vmw; 1615 int ret; 1616 1617 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver); 1618 if (ret) 1619 goto out_error; 1620 1621 ret = pcim_enable_device(pdev); 1622 if (ret) 1623 goto out_error; 1624 1625 vmw = devm_drm_dev_alloc(&pdev->dev, &driver, 1626 struct vmw_private, drm); 1627 if (IS_ERR(vmw)) { 1628 ret = PTR_ERR(vmw); 1629 goto out_error; 1630 } 1631 1632 pci_set_drvdata(pdev, &vmw->drm); 1633 1634 ret = vmw_driver_load(vmw, ent->device); 1635 if (ret) 1636 goto out_error; 1637 1638 ret = drm_dev_register(&vmw->drm, 0); 1639 if (ret) 1640 goto out_unload; 1641 1642 vmw_fifo_resource_inc(vmw); 1643 vmw_svga_enable(vmw); 1644 drm_fbdev_generic_setup(&vmw->drm, 0); 1645 1646 vmw_debugfs_gem_init(vmw); 1647 vmw_debugfs_resource_managers_init(vmw); 1648 1649 return 0; 1650 out_unload: 1651 vmw_driver_unload(&vmw->drm); 1652 out_error: 1653 return ret; 1654 } 1655 1656 drm_module_pci_driver(vmw_pci_driver); 1657 1658 MODULE_AUTHOR("VMware Inc. and others"); 1659 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1660 MODULE_LICENSE("GPL and additional rights"); 1661 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1662 __stringify(VMWGFX_DRIVER_MINOR) "." 1663 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1664 "0"); 1665