1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /**************************************************************************
3  *
4  * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
25  *
26  **************************************************************************/
27 
28 #include <linux/console.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/module.h>
31 #include <linux/pci.h>
32 #include <linux/mem_encrypt.h>
33 
34 #include <drm/drm_drv.h>
35 #include <drm/drm_fb_helper.h>
36 #include <drm/drm_ioctl.h>
37 #include <drm/drm_sysfs.h>
38 #include <drm/ttm/ttm_bo_driver.h>
39 #include <drm/ttm/ttm_placement.h>
40 
41 #include "ttm_object.h"
42 #include "vmwgfx_binding.h"
43 #include "vmwgfx_drv.h"
44 
45 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
46 
47 #define VMW_MIN_INITIAL_WIDTH 800
48 #define VMW_MIN_INITIAL_HEIGHT 600
49 
50 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE)
51 
52 
53 /**
54  * Fully encoded drm commands. Might move to vmw_drm.h
55  */
56 
57 #define DRM_IOCTL_VMW_GET_PARAM					\
58 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,		\
59 		 struct drm_vmw_getparam_arg)
60 #define DRM_IOCTL_VMW_ALLOC_DMABUF				\
61 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,	\
62 		union drm_vmw_alloc_dmabuf_arg)
63 #define DRM_IOCTL_VMW_UNREF_DMABUF				\
64 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,	\
65 		struct drm_vmw_unref_dmabuf_arg)
66 #define DRM_IOCTL_VMW_CURSOR_BYPASS				\
67 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,	\
68 		 struct drm_vmw_cursor_bypass_arg)
69 
70 #define DRM_IOCTL_VMW_CONTROL_STREAM				\
71 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,	\
72 		 struct drm_vmw_control_stream_arg)
73 #define DRM_IOCTL_VMW_CLAIM_STREAM				\
74 	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,	\
75 		 struct drm_vmw_stream_arg)
76 #define DRM_IOCTL_VMW_UNREF_STREAM				\
77 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,	\
78 		 struct drm_vmw_stream_arg)
79 
80 #define DRM_IOCTL_VMW_CREATE_CONTEXT				\
81 	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,	\
82 		struct drm_vmw_context_arg)
83 #define DRM_IOCTL_VMW_UNREF_CONTEXT				\
84 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,	\
85 		struct drm_vmw_context_arg)
86 #define DRM_IOCTL_VMW_CREATE_SURFACE				\
87 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,	\
88 		 union drm_vmw_surface_create_arg)
89 #define DRM_IOCTL_VMW_UNREF_SURFACE				\
90 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,	\
91 		 struct drm_vmw_surface_arg)
92 #define DRM_IOCTL_VMW_REF_SURFACE				\
93 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,	\
94 		 union drm_vmw_surface_reference_arg)
95 #define DRM_IOCTL_VMW_EXECBUF					\
96 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,		\
97 		struct drm_vmw_execbuf_arg)
98 #define DRM_IOCTL_VMW_GET_3D_CAP				\
99 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,		\
100 		 struct drm_vmw_get_3d_cap_arg)
101 #define DRM_IOCTL_VMW_FENCE_WAIT				\
102 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,		\
103 		 struct drm_vmw_fence_wait_arg)
104 #define DRM_IOCTL_VMW_FENCE_SIGNALED				\
105 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,	\
106 		 struct drm_vmw_fence_signaled_arg)
107 #define DRM_IOCTL_VMW_FENCE_UNREF				\
108 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,		\
109 		 struct drm_vmw_fence_arg)
110 #define DRM_IOCTL_VMW_FENCE_EVENT				\
111 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,		\
112 		 struct drm_vmw_fence_event_arg)
113 #define DRM_IOCTL_VMW_PRESENT					\
114 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,		\
115 		 struct drm_vmw_present_arg)
116 #define DRM_IOCTL_VMW_PRESENT_READBACK				\
117 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,	\
118 		 struct drm_vmw_present_readback_arg)
119 #define DRM_IOCTL_VMW_UPDATE_LAYOUT				\
120 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,	\
121 		 struct drm_vmw_update_layout_arg)
122 #define DRM_IOCTL_VMW_CREATE_SHADER				\
123 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER,	\
124 		 struct drm_vmw_shader_create_arg)
125 #define DRM_IOCTL_VMW_UNREF_SHADER				\
126 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER,	\
127 		 struct drm_vmw_shader_arg)
128 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE				\
129 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE,	\
130 		 union drm_vmw_gb_surface_create_arg)
131 #define DRM_IOCTL_VMW_GB_SURFACE_REF				\
132 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF,	\
133 		 union drm_vmw_gb_surface_reference_arg)
134 #define DRM_IOCTL_VMW_SYNCCPU					\
135 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU,		\
136 		 struct drm_vmw_synccpu_arg)
137 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT			\
138 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT,	\
139 		struct drm_vmw_context_arg)
140 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT				\
141 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT,	\
142 		union drm_vmw_gb_surface_create_ext_arg)
143 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT				\
144 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT,		\
145 		union drm_vmw_gb_surface_reference_ext_arg)
146 #define DRM_IOCTL_VMW_MSG						\
147 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG,			\
148 		struct drm_vmw_msg_arg)
149 
150 /*
151  * The core DRM version of this macro doesn't account for
152  * DRM_COMMAND_BASE.
153  */
154 
155 #define VMW_IOCTL_DEF(ioctl, func, flags) \
156   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func}
157 
158 /*
159  * Ioctl definitions.
160  */
161 
162 static const struct drm_ioctl_desc vmw_ioctls[] = {
163 	VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
164 		      DRM_RENDER_ALLOW),
165 	VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl,
166 		      DRM_RENDER_ALLOW),
167 	VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl,
168 		      DRM_RENDER_ALLOW),
169 	VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
170 		      vmw_kms_cursor_bypass_ioctl,
171 		      DRM_MASTER),
172 
173 	VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
174 		      DRM_MASTER),
175 	VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
176 		      DRM_MASTER),
177 	VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
178 		      DRM_MASTER),
179 
180 	VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
181 		      DRM_RENDER_ALLOW),
182 	VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
183 		      DRM_RENDER_ALLOW),
184 	VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
185 		      DRM_RENDER_ALLOW),
186 	VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
187 		      DRM_RENDER_ALLOW),
188 	VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
189 		      DRM_RENDER_ALLOW),
190 	VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
191 		      DRM_RENDER_ALLOW),
192 	VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
193 		      DRM_RENDER_ALLOW),
194 	VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
195 		      vmw_fence_obj_signaled_ioctl,
196 		      DRM_RENDER_ALLOW),
197 	VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
198 		      DRM_RENDER_ALLOW),
199 	VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl,
200 		      DRM_RENDER_ALLOW),
201 	VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
202 		      DRM_RENDER_ALLOW),
203 
204 	/* these allow direct access to the framebuffers mark as master only */
205 	VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
206 		      DRM_MASTER | DRM_AUTH),
207 	VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
208 		      vmw_present_readback_ioctl,
209 		      DRM_MASTER | DRM_AUTH),
210 	/*
211 	 * The permissions of the below ioctl are overridden in
212 	 * vmw_generic_ioctl(). We require either
213 	 * DRM_MASTER or capable(CAP_SYS_ADMIN).
214 	 */
215 	VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT,
216 		      vmw_kms_update_layout_ioctl,
217 		      DRM_RENDER_ALLOW),
218 	VMW_IOCTL_DEF(VMW_CREATE_SHADER,
219 		      vmw_shader_define_ioctl,
220 		      DRM_RENDER_ALLOW),
221 	VMW_IOCTL_DEF(VMW_UNREF_SHADER,
222 		      vmw_shader_destroy_ioctl,
223 		      DRM_RENDER_ALLOW),
224 	VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE,
225 		      vmw_gb_surface_define_ioctl,
226 		      DRM_RENDER_ALLOW),
227 	VMW_IOCTL_DEF(VMW_GB_SURFACE_REF,
228 		      vmw_gb_surface_reference_ioctl,
229 		      DRM_RENDER_ALLOW),
230 	VMW_IOCTL_DEF(VMW_SYNCCPU,
231 		      vmw_user_bo_synccpu_ioctl,
232 		      DRM_RENDER_ALLOW),
233 	VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT,
234 		      vmw_extended_context_define_ioctl,
235 		      DRM_RENDER_ALLOW),
236 	VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT,
237 		      vmw_gb_surface_define_ext_ioctl,
238 		      DRM_RENDER_ALLOW),
239 	VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT,
240 		      vmw_gb_surface_reference_ext_ioctl,
241 		      DRM_RENDER_ALLOW),
242 	VMW_IOCTL_DEF(VMW_MSG,
243 		      vmw_msg_ioctl,
244 		      DRM_RENDER_ALLOW),
245 };
246 
247 static const struct pci_device_id vmw_pci_id_list[] = {
248 	{ PCI_DEVICE(0x15ad, VMWGFX_PCI_ID_SVGA2) },
249 	{ }
250 };
251 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list);
252 
253 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON);
254 static int vmw_force_iommu;
255 static int vmw_restrict_iommu;
256 static int vmw_force_coherent;
257 static int vmw_restrict_dma_mask;
258 static int vmw_assume_16bpp;
259 
260 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
261 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
262 			      void *ptr);
263 
264 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
265 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
266 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages");
267 module_param_named(force_dma_api, vmw_force_iommu, int, 0600);
268 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages");
269 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600);
270 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages");
271 module_param_named(force_coherent, vmw_force_coherent, int, 0600);
272 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU");
273 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600);
274 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes");
275 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600);
276 
277 
278 static void vmw_print_capabilities2(uint32_t capabilities2)
279 {
280 	DRM_INFO("Capabilities2:\n");
281 	if (capabilities2 & SVGA_CAP2_GROW_OTABLE)
282 		DRM_INFO("  Grow oTable.\n");
283 	if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY)
284 		DRM_INFO("  IntraSurface copy.\n");
285 	if (capabilities2 & SVGA_CAP2_DX3)
286 		DRM_INFO("  DX3.\n");
287 }
288 
289 static void vmw_print_capabilities(uint32_t capabilities)
290 {
291 	DRM_INFO("Capabilities:\n");
292 	if (capabilities & SVGA_CAP_RECT_COPY)
293 		DRM_INFO("  Rect copy.\n");
294 	if (capabilities & SVGA_CAP_CURSOR)
295 		DRM_INFO("  Cursor.\n");
296 	if (capabilities & SVGA_CAP_CURSOR_BYPASS)
297 		DRM_INFO("  Cursor bypass.\n");
298 	if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
299 		DRM_INFO("  Cursor bypass 2.\n");
300 	if (capabilities & SVGA_CAP_8BIT_EMULATION)
301 		DRM_INFO("  8bit emulation.\n");
302 	if (capabilities & SVGA_CAP_ALPHA_CURSOR)
303 		DRM_INFO("  Alpha cursor.\n");
304 	if (capabilities & SVGA_CAP_3D)
305 		DRM_INFO("  3D.\n");
306 	if (capabilities & SVGA_CAP_EXTENDED_FIFO)
307 		DRM_INFO("  Extended Fifo.\n");
308 	if (capabilities & SVGA_CAP_MULTIMON)
309 		DRM_INFO("  Multimon.\n");
310 	if (capabilities & SVGA_CAP_PITCHLOCK)
311 		DRM_INFO("  Pitchlock.\n");
312 	if (capabilities & SVGA_CAP_IRQMASK)
313 		DRM_INFO("  Irq mask.\n");
314 	if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
315 		DRM_INFO("  Display Topology.\n");
316 	if (capabilities & SVGA_CAP_GMR)
317 		DRM_INFO("  GMR.\n");
318 	if (capabilities & SVGA_CAP_TRACES)
319 		DRM_INFO("  Traces.\n");
320 	if (capabilities & SVGA_CAP_GMR2)
321 		DRM_INFO("  GMR2.\n");
322 	if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
323 		DRM_INFO("  Screen Object 2.\n");
324 	if (capabilities & SVGA_CAP_COMMAND_BUFFERS)
325 		DRM_INFO("  Command Buffers.\n");
326 	if (capabilities & SVGA_CAP_CMD_BUFFERS_2)
327 		DRM_INFO("  Command Buffers 2.\n");
328 	if (capabilities & SVGA_CAP_GBOBJECTS)
329 		DRM_INFO("  Guest Backed Resources.\n");
330 	if (capabilities & SVGA_CAP_DX)
331 		DRM_INFO("  DX Features.\n");
332 	if (capabilities & SVGA_CAP_HP_CMD_QUEUE)
333 		DRM_INFO("  HP Command Queue.\n");
334 }
335 
336 /**
337  * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
338  *
339  * @dev_priv: A device private structure.
340  *
341  * This function creates a small buffer object that holds the query
342  * result for dummy queries emitted as query barriers.
343  * The function will then map the first page and initialize a pending
344  * occlusion query result structure, Finally it will unmap the buffer.
345  * No interruptible waits are done within this function.
346  *
347  * Returns an error if bo creation or initialization fails.
348  */
349 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
350 {
351 	int ret;
352 	struct vmw_buffer_object *vbo;
353 	struct ttm_bo_kmap_obj map;
354 	volatile SVGA3dQueryResult *result;
355 	bool dummy;
356 
357 	/*
358 	 * Create the vbo as pinned, so that a tryreserve will
359 	 * immediately succeed. This is because we're the only
360 	 * user of the bo currently.
361 	 */
362 	vbo = kzalloc(sizeof(*vbo), GFP_KERNEL);
363 	if (!vbo)
364 		return -ENOMEM;
365 
366 	ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE,
367 			  &vmw_sys_placement, false, true,
368 			  &vmw_bo_bo_free);
369 	if (unlikely(ret != 0))
370 		return ret;
371 
372 	ret = ttm_bo_reserve(&vbo->base, false, true, NULL);
373 	BUG_ON(ret != 0);
374 	vmw_bo_pin_reserved(vbo, true);
375 
376 	ret = ttm_bo_kmap(&vbo->base, 0, 1, &map);
377 	if (likely(ret == 0)) {
378 		result = ttm_kmap_obj_virtual(&map, &dummy);
379 		result->totalSize = sizeof(*result);
380 		result->state = SVGA3D_QUERYSTATE_PENDING;
381 		result->result32 = 0xff;
382 		ttm_bo_kunmap(&map);
383 	}
384 	vmw_bo_pin_reserved(vbo, false);
385 	ttm_bo_unreserve(&vbo->base);
386 
387 	if (unlikely(ret != 0)) {
388 		DRM_ERROR("Dummy query buffer map failed.\n");
389 		vmw_bo_unreference(&vbo);
390 	} else
391 		dev_priv->dummy_query_bo = vbo;
392 
393 	return ret;
394 }
395 
396 /**
397  * vmw_request_device_late - Perform late device setup
398  *
399  * @dev_priv: Pointer to device private.
400  *
401  * This function performs setup of otables and enables large command
402  * buffer submission. These tasks are split out to a separate function
403  * because it reverts vmw_release_device_early and is intended to be used
404  * by an error path in the hibernation code.
405  */
406 static int vmw_request_device_late(struct vmw_private *dev_priv)
407 {
408 	int ret;
409 
410 	if (dev_priv->has_mob) {
411 		ret = vmw_otables_setup(dev_priv);
412 		if (unlikely(ret != 0)) {
413 			DRM_ERROR("Unable to initialize "
414 				  "guest Memory OBjects.\n");
415 			return ret;
416 		}
417 	}
418 
419 	if (dev_priv->cman) {
420 		ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096);
421 		if (ret) {
422 			struct vmw_cmdbuf_man *man = dev_priv->cman;
423 
424 			dev_priv->cman = NULL;
425 			vmw_cmdbuf_man_destroy(man);
426 		}
427 	}
428 
429 	return 0;
430 }
431 
432 static int vmw_request_device(struct vmw_private *dev_priv)
433 {
434 	int ret;
435 
436 	ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
437 	if (unlikely(ret != 0)) {
438 		DRM_ERROR("Unable to initialize FIFO.\n");
439 		return ret;
440 	}
441 	vmw_fence_fifo_up(dev_priv->fman);
442 	dev_priv->cman = vmw_cmdbuf_man_create(dev_priv);
443 	if (IS_ERR(dev_priv->cman)) {
444 		dev_priv->cman = NULL;
445 		dev_priv->sm_type = VMW_SM_LEGACY;
446 	}
447 
448 	ret = vmw_request_device_late(dev_priv);
449 	if (ret)
450 		goto out_no_mob;
451 
452 	ret = vmw_dummy_query_bo_create(dev_priv);
453 	if (unlikely(ret != 0))
454 		goto out_no_query_bo;
455 
456 	return 0;
457 
458 out_no_query_bo:
459 	if (dev_priv->cman)
460 		vmw_cmdbuf_remove_pool(dev_priv->cman);
461 	if (dev_priv->has_mob) {
462 		struct ttm_resource_manager *man;
463 
464 		man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
465 		ttm_resource_manager_evict_all(&dev_priv->bdev, man);
466 		vmw_otables_takedown(dev_priv);
467 	}
468 	if (dev_priv->cman)
469 		vmw_cmdbuf_man_destroy(dev_priv->cman);
470 out_no_mob:
471 	vmw_fence_fifo_down(dev_priv->fman);
472 	vmw_fifo_release(dev_priv, &dev_priv->fifo);
473 	return ret;
474 }
475 
476 /**
477  * vmw_release_device_early - Early part of fifo takedown.
478  *
479  * @dev_priv: Pointer to device private struct.
480  *
481  * This is the first part of command submission takedown, to be called before
482  * buffer management is taken down.
483  */
484 static void vmw_release_device_early(struct vmw_private *dev_priv)
485 {
486 	/*
487 	 * Previous destructions should've released
488 	 * the pinned bo.
489 	 */
490 
491 	BUG_ON(dev_priv->pinned_bo != NULL);
492 
493 	vmw_bo_unreference(&dev_priv->dummy_query_bo);
494 	if (dev_priv->cman)
495 		vmw_cmdbuf_remove_pool(dev_priv->cman);
496 
497 	if (dev_priv->has_mob) {
498 		struct ttm_resource_manager *man;
499 
500 		man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB);
501 		ttm_resource_manager_evict_all(&dev_priv->bdev, man);
502 		vmw_otables_takedown(dev_priv);
503 	}
504 }
505 
506 /**
507  * vmw_release_device_late - Late part of fifo takedown.
508  *
509  * @dev_priv: Pointer to device private struct.
510  *
511  * This is the last part of the command submission takedown, to be called when
512  * command submission is no longer needed. It may wait on pending fences.
513  */
514 static void vmw_release_device_late(struct vmw_private *dev_priv)
515 {
516 	vmw_fence_fifo_down(dev_priv->fman);
517 	if (dev_priv->cman)
518 		vmw_cmdbuf_man_destroy(dev_priv->cman);
519 
520 	vmw_fifo_release(dev_priv, &dev_priv->fifo);
521 }
522 
523 /*
524  * Sets the initial_[width|height] fields on the given vmw_private.
525  *
526  * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then
527  * clamping the value to fb_max_[width|height] fields and the
528  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
529  * If the values appear to be invalid, set them to
530  * VMW_MIN_INITIAL_[WIDTH|HEIGHT].
531  */
532 static void vmw_get_initial_size(struct vmw_private *dev_priv)
533 {
534 	uint32_t width;
535 	uint32_t height;
536 
537 	width = vmw_read(dev_priv, SVGA_REG_WIDTH);
538 	height = vmw_read(dev_priv, SVGA_REG_HEIGHT);
539 
540 	width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH);
541 	height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT);
542 
543 	if (width > dev_priv->fb_max_width ||
544 	    height > dev_priv->fb_max_height) {
545 
546 		/*
547 		 * This is a host error and shouldn't occur.
548 		 */
549 
550 		width = VMW_MIN_INITIAL_WIDTH;
551 		height = VMW_MIN_INITIAL_HEIGHT;
552 	}
553 
554 	dev_priv->initial_width = width;
555 	dev_priv->initial_height = height;
556 }
557 
558 /**
559  * vmw_dma_select_mode - Determine how DMA mappings should be set up for this
560  * system.
561  *
562  * @dev_priv: Pointer to a struct vmw_private
563  *
564  * This functions tries to determine what actions need to be taken by the
565  * driver to make system pages visible to the device.
566  * If this function decides that DMA is not possible, it returns -EINVAL.
567  * The driver may then try to disable features of the device that require
568  * DMA.
569  */
570 static int vmw_dma_select_mode(struct vmw_private *dev_priv)
571 {
572 	static const char *names[vmw_dma_map_max] = {
573 		[vmw_dma_phys] = "Using physical TTM page addresses.",
574 		[vmw_dma_alloc_coherent] = "Using coherent TTM pages.",
575 		[vmw_dma_map_populate] = "Caching DMA mappings.",
576 		[vmw_dma_map_bind] = "Giving up DMA mappings early."};
577 
578 	/* TTM currently doesn't fully support SEV encryption. */
579 	if (mem_encrypt_active())
580 		return -EINVAL;
581 
582 	if (vmw_force_coherent)
583 		dev_priv->map_mode = vmw_dma_alloc_coherent;
584 	else if (vmw_restrict_iommu)
585 		dev_priv->map_mode = vmw_dma_map_bind;
586 	else
587 		dev_priv->map_mode = vmw_dma_map_populate;
588 
589 	DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]);
590 	return 0;
591 }
592 
593 /**
594  * vmw_dma_masks - set required page- and dma masks
595  *
596  * @dev_priv: Pointer to struct drm-device
597  *
598  * With 32-bit we can only handle 32 bit PFNs. Optionally set that
599  * restriction also for 64-bit systems.
600  */
601 static int vmw_dma_masks(struct vmw_private *dev_priv)
602 {
603 	struct drm_device *dev = &dev_priv->drm;
604 	int ret = 0;
605 
606 	ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64));
607 	if (dev_priv->map_mode != vmw_dma_phys &&
608 	    (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) {
609 		DRM_INFO("Restricting DMA addresses to 44 bits.\n");
610 		return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44));
611 	}
612 
613 	return ret;
614 }
615 
616 static int vmw_vram_manager_init(struct vmw_private *dev_priv)
617 {
618 	int ret;
619 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
620 	ret = vmw_thp_init(dev_priv);
621 #else
622 	ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false,
623 				 dev_priv->vram_size >> PAGE_SHIFT);
624 #endif
625 	ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false);
626 	return ret;
627 }
628 
629 static void vmw_vram_manager_fini(struct vmw_private *dev_priv)
630 {
631 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
632 	vmw_thp_fini(dev_priv);
633 #else
634 	ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM);
635 #endif
636 }
637 
638 static int vmw_setup_pci_resources(struct vmw_private *dev,
639 				   unsigned long pci_id)
640 {
641 	resource_size_t fifo_start;
642 	resource_size_t fifo_size;
643 	int ret;
644 	struct pci_dev *pdev = to_pci_dev(dev->drm.dev);
645 
646 	pci_set_master(pdev);
647 
648 	ret = pci_request_regions(pdev, "vmwgfx probe");
649 	if (ret)
650 		return ret;
651 
652 	dev->io_start = pci_resource_start(pdev, 0);
653 	dev->vram_start = pci_resource_start(pdev, 1);
654 	dev->vram_size = pci_resource_len(pdev, 1);
655 	fifo_start = pci_resource_start(pdev, 2);
656 	fifo_size = pci_resource_len(pdev, 2);
657 
658 	DRM_INFO("FIFO at %pa size is %llu kiB\n",
659 		 &fifo_start, (uint64_t)fifo_size / 1024);
660 	dev->fifo_mem = devm_memremap(dev->drm.dev,
661 				      fifo_start,
662 				      fifo_size,
663 				      MEMREMAP_WB);
664 
665 	if (IS_ERR(dev->fifo_mem)) {
666 		DRM_ERROR("Failed mapping FIFO memory.\n");
667 		pci_release_regions(pdev);
668 		return PTR_ERR(dev->fifo_mem);
669 	}
670 
671 	/*
672 	 * This is approximate size of the vram, the exact size will only
673 	 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource
674 	 * size will be equal to or bigger than the size reported by
675 	 * SVGA_REG_VRAM_SIZE.
676 	 */
677 	DRM_INFO("VRAM at %pa size is %llu kiB\n",
678 		 &dev->vram_start, (uint64_t)dev->vram_size / 1024);
679 
680 	return 0;
681 }
682 
683 static int vmw_detect_version(struct vmw_private *dev)
684 {
685 	uint32_t svga_id;
686 
687 	vmw_write(dev, SVGA_REG_ID, SVGA_ID_2);
688 	svga_id = vmw_read(dev, SVGA_REG_ID);
689 	if (svga_id != SVGA_ID_2) {
690 		DRM_ERROR("Unsupported SVGA ID 0x%x on chipset 0x%x\n",
691 			  svga_id, dev->vmw_chipset);
692 		return -ENOSYS;
693 	}
694 	return 0;
695 }
696 
697 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
698 {
699 	int ret;
700 	enum vmw_res_type i;
701 	bool refuse_dma = false;
702 	char host_log[100] = {0};
703 	struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
704 
705 	dev_priv->vmw_chipset = pci_id;
706 	dev_priv->last_read_seqno = (uint32_t) -100;
707 	dev_priv->drm.dev_private = dev_priv;
708 
709 	mutex_init(&dev_priv->cmdbuf_mutex);
710 	mutex_init(&dev_priv->binding_mutex);
711 	ttm_lock_init(&dev_priv->reservation_sem);
712 	spin_lock_init(&dev_priv->resource_lock);
713 	spin_lock_init(&dev_priv->hw_lock);
714 	spin_lock_init(&dev_priv->waiter_lock);
715 	spin_lock_init(&dev_priv->cap_lock);
716 	spin_lock_init(&dev_priv->cursor_lock);
717 
718 	ret = vmw_setup_pci_resources(dev_priv, pci_id);
719 	if (ret)
720 		return ret;
721 	ret = vmw_detect_version(dev_priv);
722 	if (ret)
723 		goto out_no_pci_or_version;
724 
725 
726 	for (i = vmw_res_context; i < vmw_res_max; ++i) {
727 		idr_init(&dev_priv->res_idr[i]);
728 		INIT_LIST_HEAD(&dev_priv->res_lru[i]);
729 	}
730 
731 	init_waitqueue_head(&dev_priv->fence_queue);
732 	init_waitqueue_head(&dev_priv->fifo_queue);
733 	dev_priv->fence_queue_waiters = 0;
734 	dev_priv->fifo_queue_waiters = 0;
735 
736 	dev_priv->used_memory_size = 0;
737 
738 	dev_priv->assume_16bpp = !!vmw_assume_16bpp;
739 
740 	dev_priv->enable_fb = enable_fbdev;
741 
742 
743 	dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
744 
745 	if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) {
746 		dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2);
747 	}
748 
749 
750 	ret = vmw_dma_select_mode(dev_priv);
751 	if (unlikely(ret != 0)) {
752 		DRM_INFO("Restricting capabilities since DMA not available.\n");
753 		refuse_dma = true;
754 		if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
755 			DRM_INFO("Disabling 3D acceleration.\n");
756 	}
757 
758 	dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
759 	dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
760 	dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
761 	dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
762 
763 	vmw_get_initial_size(dev_priv);
764 
765 	if (dev_priv->capabilities & SVGA_CAP_GMR2) {
766 		dev_priv->max_gmr_ids =
767 			vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
768 		dev_priv->max_gmr_pages =
769 			vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
770 		dev_priv->memory_size =
771 			vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
772 		dev_priv->memory_size -= dev_priv->vram_size;
773 	} else {
774 		/*
775 		 * An arbitrary limit of 512MiB on surface
776 		 * memory. But all HWV8 hardware supports GMR2.
777 		 */
778 		dev_priv->memory_size = 512*1024*1024;
779 	}
780 	dev_priv->max_mob_pages = 0;
781 	dev_priv->max_mob_size = 0;
782 	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
783 		uint64_t mem_size;
784 
785 		if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2)
786 			mem_size = vmw_read(dev_priv,
787 					    SVGA_REG_GBOBJECT_MEM_SIZE_KB);
788 		else
789 			mem_size =
790 				vmw_read(dev_priv,
791 					 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
792 
793 		/*
794 		 * Workaround for low memory 2D VMs to compensate for the
795 		 * allocation taken by fbdev
796 		 */
797 		if (!(dev_priv->capabilities & SVGA_CAP_3D))
798 			mem_size *= 3;
799 
800 		dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
801 		dev_priv->prim_bb_mem =
802 			vmw_read(dev_priv,
803 				 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
804 		dev_priv->max_mob_size =
805 			vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
806 		dev_priv->stdu_max_width =
807 			vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH);
808 		dev_priv->stdu_max_height =
809 			vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT);
810 
811 		vmw_write(dev_priv, SVGA_REG_DEV_CAP,
812 			  SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH);
813 		dev_priv->texture_max_width = vmw_read(dev_priv,
814 						       SVGA_REG_DEV_CAP);
815 		vmw_write(dev_priv, SVGA_REG_DEV_CAP,
816 			  SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT);
817 		dev_priv->texture_max_height = vmw_read(dev_priv,
818 							SVGA_REG_DEV_CAP);
819 	} else {
820 		dev_priv->texture_max_width = 8192;
821 		dev_priv->texture_max_height = 8192;
822 		dev_priv->prim_bb_mem = dev_priv->vram_size;
823 	}
824 
825 	vmw_print_capabilities(dev_priv->capabilities);
826 	if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER)
827 		vmw_print_capabilities2(dev_priv->capabilities2);
828 
829 	ret = vmw_dma_masks(dev_priv);
830 	if (unlikely(ret != 0))
831 		goto out_err0;
832 
833 	dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX);
834 
835 	if (dev_priv->capabilities & SVGA_CAP_GMR2) {
836 		DRM_INFO("Max GMR ids is %u\n",
837 			 (unsigned)dev_priv->max_gmr_ids);
838 		DRM_INFO("Max number of GMR pages is %u\n",
839 			 (unsigned)dev_priv->max_gmr_pages);
840 		DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
841 			 (unsigned)dev_priv->memory_size / 1024);
842 	}
843 	DRM_INFO("Maximum display memory size is %llu kiB\n",
844 		 (uint64_t)dev_priv->prim_bb_mem / 1024);
845 
846 	/* Need mmio memory to check for fifo pitchlock cap. */
847 	if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
848 	    !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
849 	    !vmw_fifo_have_pitchlock(dev_priv)) {
850 		ret = -ENOSYS;
851 		DRM_ERROR("Hardware has no pitchlock\n");
852 		goto out_err0;
853 	}
854 
855 	dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12,
856 						&vmw_prime_dmabuf_ops);
857 
858 	if (unlikely(dev_priv->tdev == NULL)) {
859 		DRM_ERROR("Unable to initialize TTM object management.\n");
860 		ret = -ENOMEM;
861 		goto out_err0;
862 	}
863 
864 	if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
865 		ret = vmw_irq_install(&dev_priv->drm, pdev->irq);
866 		if (ret != 0) {
867 			DRM_ERROR("Failed installing irq: %d\n", ret);
868 			goto out_no_irq;
869 		}
870 	}
871 
872 	dev_priv->fman = vmw_fence_manager_init(dev_priv);
873 	if (unlikely(dev_priv->fman == NULL)) {
874 		ret = -ENOMEM;
875 		goto out_no_fman;
876 	}
877 
878 	drm_vma_offset_manager_init(&dev_priv->vma_manager,
879 				    DRM_FILE_PAGE_OFFSET_START,
880 				    DRM_FILE_PAGE_OFFSET_SIZE);
881 	ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver,
882 			      dev_priv->drm.dev,
883 			      dev_priv->drm.anon_inode->i_mapping,
884 			      &dev_priv->vma_manager,
885 			      dev_priv->map_mode == vmw_dma_alloc_coherent,
886 			      false);
887 	if (unlikely(ret != 0)) {
888 		DRM_ERROR("Failed initializing TTM buffer object driver.\n");
889 		goto out_no_bdev;
890 	}
891 
892 	/*
893 	 * Enable VRAM, but initially don't use it until SVGA is enabled and
894 	 * unhidden.
895 	 */
896 
897 	ret = vmw_vram_manager_init(dev_priv);
898 	if (unlikely(ret != 0)) {
899 		DRM_ERROR("Failed initializing memory manager for VRAM.\n");
900 		goto out_no_vram;
901 	}
902 
903 	/*
904 	 * "Guest Memory Regions" is an aperture like feature with
905 	 *  one slot per bo. There is an upper limit of the number of
906 	 *  slots as well as the bo size.
907 	 */
908 	dev_priv->has_gmr = true;
909 	/* TODO: This is most likely not correct */
910 	if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) ||
911 	    refuse_dma ||
912 	    vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) {
913 		DRM_INFO("No GMR memory available. "
914 			 "Graphics memory resources are very limited.\n");
915 		dev_priv->has_gmr = false;
916 	}
917 
918 	if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) {
919 		dev_priv->has_mob = true;
920 
921 		if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) {
922 			DRM_INFO("No MOB memory available. "
923 				 "3D will be disabled.\n");
924 			dev_priv->has_mob = false;
925 		}
926 	}
927 
928 	if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) {
929 		spin_lock(&dev_priv->cap_lock);
930 		vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT);
931 		if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
932 			dev_priv->sm_type = VMW_SM_4;
933 		spin_unlock(&dev_priv->cap_lock);
934 	}
935 
936 	vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN);
937 
938 	/* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */
939 	if (has_sm4_context(dev_priv) &&
940 	    (dev_priv->capabilities2 & SVGA_CAP2_DX2)) {
941 		vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM41);
942 
943 		if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
944 			dev_priv->sm_type = VMW_SM_4_1;
945 
946 		if (has_sm4_1_context(dev_priv) &&
947 		    (dev_priv->capabilities2 & SVGA_CAP2_DX3)) {
948 			vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM5);
949 			if (vmw_read(dev_priv, SVGA_REG_DEV_CAP))
950 				dev_priv->sm_type = VMW_SM_5;
951 		}
952 	}
953 
954 	ret = vmw_kms_init(dev_priv);
955 	if (unlikely(ret != 0))
956 		goto out_no_kms;
957 	vmw_overlay_init(dev_priv);
958 
959 	ret = vmw_request_device(dev_priv);
960 	if (ret)
961 		goto out_no_fifo;
962 
963 	if (dev_priv->sm_type == VMW_SM_5)
964 		DRM_INFO("SM5 support available.\n");
965 	if (dev_priv->sm_type == VMW_SM_4_1)
966 		DRM_INFO("SM4_1 support available.\n");
967 	if (dev_priv->sm_type == VMW_SM_4)
968 		DRM_INFO("SM4 support available.\n");
969 
970 	snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d",
971 		VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR,
972 		VMWGFX_DRIVER_PATCHLEVEL);
973 	vmw_host_log(host_log);
974 
975 	if (dev_priv->enable_fb) {
976 		vmw_fifo_resource_inc(dev_priv);
977 		vmw_svga_enable(dev_priv);
978 		vmw_fb_init(dev_priv);
979 	}
980 
981 	dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
982 	register_pm_notifier(&dev_priv->pm_nb);
983 
984 	return 0;
985 
986 out_no_fifo:
987 	vmw_overlay_close(dev_priv);
988 	vmw_kms_close(dev_priv);
989 out_no_kms:
990 	if (dev_priv->has_mob)
991 		vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
992 	if (dev_priv->has_gmr)
993 		vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
994 	vmw_vram_manager_fini(dev_priv);
995 out_no_vram:
996 	ttm_device_fini(&dev_priv->bdev);
997 out_no_bdev:
998 	vmw_fence_manager_takedown(dev_priv->fman);
999 out_no_fman:
1000 	if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1001 		vmw_irq_uninstall(&dev_priv->drm);
1002 out_no_irq:
1003 	ttm_object_device_release(&dev_priv->tdev);
1004 out_err0:
1005 	for (i = vmw_res_context; i < vmw_res_max; ++i)
1006 		idr_destroy(&dev_priv->res_idr[i]);
1007 
1008 	if (dev_priv->ctx.staged_bindings)
1009 		vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1010 out_no_pci_or_version:
1011 	pci_release_regions(pdev);
1012 	return ret;
1013 }
1014 
1015 static void vmw_driver_unload(struct drm_device *dev)
1016 {
1017 	struct vmw_private *dev_priv = vmw_priv(dev);
1018 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1019 	enum vmw_res_type i;
1020 
1021 	unregister_pm_notifier(&dev_priv->pm_nb);
1022 
1023 	if (dev_priv->ctx.res_ht_initialized)
1024 		drm_ht_remove(&dev_priv->ctx.res_ht);
1025 	vfree(dev_priv->ctx.cmd_bounce);
1026 	if (dev_priv->enable_fb) {
1027 		vmw_fb_off(dev_priv);
1028 		vmw_fb_close(dev_priv);
1029 		vmw_fifo_resource_dec(dev_priv);
1030 		vmw_svga_disable(dev_priv);
1031 	}
1032 
1033 	vmw_kms_close(dev_priv);
1034 	vmw_overlay_close(dev_priv);
1035 
1036 	if (dev_priv->has_gmr)
1037 		vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR);
1038 
1039 	vmw_release_device_early(dev_priv);
1040 	if (dev_priv->has_mob)
1041 		vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB);
1042 	vmw_vram_manager_fini(dev_priv);
1043 	ttm_device_fini(&dev_priv->bdev);
1044 	drm_vma_offset_manager_destroy(&dev_priv->vma_manager);
1045 	vmw_release_device_late(dev_priv);
1046 	vmw_fence_manager_takedown(dev_priv->fman);
1047 	if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
1048 		vmw_irq_uninstall(&dev_priv->drm);
1049 
1050 	ttm_object_device_release(&dev_priv->tdev);
1051 	if (dev_priv->ctx.staged_bindings)
1052 		vmw_binding_state_free(dev_priv->ctx.staged_bindings);
1053 
1054 	for (i = vmw_res_context; i < vmw_res_max; ++i)
1055 		idr_destroy(&dev_priv->res_idr[i]);
1056 
1057 	pci_release_regions(pdev);
1058 }
1059 
1060 static void vmw_postclose(struct drm_device *dev,
1061 			 struct drm_file *file_priv)
1062 {
1063 	struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
1064 
1065 	ttm_object_file_release(&vmw_fp->tfile);
1066 	kfree(vmw_fp);
1067 }
1068 
1069 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
1070 {
1071 	struct vmw_private *dev_priv = vmw_priv(dev);
1072 	struct vmw_fpriv *vmw_fp;
1073 	int ret = -ENOMEM;
1074 
1075 	vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
1076 	if (unlikely(!vmw_fp))
1077 		return ret;
1078 
1079 	vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
1080 	if (unlikely(vmw_fp->tfile == NULL))
1081 		goto out_no_tfile;
1082 
1083 	file_priv->driver_priv = vmw_fp;
1084 
1085 	return 0;
1086 
1087 out_no_tfile:
1088 	kfree(vmw_fp);
1089 	return ret;
1090 }
1091 
1092 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd,
1093 			      unsigned long arg,
1094 			      long (*ioctl_func)(struct file *, unsigned int,
1095 						 unsigned long))
1096 {
1097 	struct drm_file *file_priv = filp->private_data;
1098 	struct drm_device *dev = file_priv->minor->dev;
1099 	unsigned int nr = DRM_IOCTL_NR(cmd);
1100 	unsigned int flags;
1101 
1102 	/*
1103 	 * Do extra checking on driver private ioctls.
1104 	 */
1105 
1106 	if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
1107 	    && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
1108 		const struct drm_ioctl_desc *ioctl =
1109 			&vmw_ioctls[nr - DRM_COMMAND_BASE];
1110 
1111 		if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) {
1112 			return ioctl_func(filp, cmd, arg);
1113 		} else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) {
1114 			if (!drm_is_current_master(file_priv) &&
1115 			    !capable(CAP_SYS_ADMIN))
1116 				return -EACCES;
1117 		}
1118 
1119 		if (unlikely(ioctl->cmd != cmd))
1120 			goto out_io_encoding;
1121 
1122 		flags = ioctl->flags;
1123 	} else if (!drm_ioctl_flags(nr, &flags))
1124 		return -EINVAL;
1125 
1126 	return ioctl_func(filp, cmd, arg);
1127 
1128 out_io_encoding:
1129 	DRM_ERROR("Invalid command format, ioctl %d\n",
1130 		  nr - DRM_COMMAND_BASE);
1131 
1132 	return -EINVAL;
1133 }
1134 
1135 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
1136 			       unsigned long arg)
1137 {
1138 	return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl);
1139 }
1140 
1141 #ifdef CONFIG_COMPAT
1142 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd,
1143 			     unsigned long arg)
1144 {
1145 	return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl);
1146 }
1147 #endif
1148 
1149 static void vmw_master_set(struct drm_device *dev,
1150 			   struct drm_file *file_priv,
1151 			   bool from_open)
1152 {
1153 	/*
1154 	 * Inform a new master that the layout may have changed while
1155 	 * it was gone.
1156 	 */
1157 	if (!from_open)
1158 		drm_sysfs_hotplug_event(dev);
1159 }
1160 
1161 static void vmw_master_drop(struct drm_device *dev,
1162 			    struct drm_file *file_priv)
1163 {
1164 	struct vmw_private *dev_priv = vmw_priv(dev);
1165 
1166 	vmw_kms_legacy_hotspot_clear(dev_priv);
1167 	if (!dev_priv->enable_fb)
1168 		vmw_svga_disable(dev_priv);
1169 }
1170 
1171 /**
1172  * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1173  *
1174  * @dev_priv: Pointer to device private struct.
1175  * Needs the reservation sem to be held in non-exclusive mode.
1176  */
1177 static void __vmw_svga_enable(struct vmw_private *dev_priv)
1178 {
1179 	struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1180 
1181 	if (!ttm_resource_manager_used(man)) {
1182 		vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE);
1183 		ttm_resource_manager_set_used(man, true);
1184 	}
1185 }
1186 
1187 /**
1188  * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM.
1189  *
1190  * @dev_priv: Pointer to device private struct.
1191  */
1192 void vmw_svga_enable(struct vmw_private *dev_priv)
1193 {
1194 	(void) ttm_read_lock(&dev_priv->reservation_sem, false);
1195 	__vmw_svga_enable(dev_priv);
1196 	ttm_read_unlock(&dev_priv->reservation_sem);
1197 }
1198 
1199 /**
1200  * __vmw_svga_disable - Disable SVGA mode and use of VRAM.
1201  *
1202  * @dev_priv: Pointer to device private struct.
1203  * Needs the reservation sem to be held in exclusive mode.
1204  * Will not empty VRAM. VRAM must be emptied by caller.
1205  */
1206 static void __vmw_svga_disable(struct vmw_private *dev_priv)
1207 {
1208 	struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1209 
1210 	if (ttm_resource_manager_used(man)) {
1211 		ttm_resource_manager_set_used(man, false);
1212 		vmw_write(dev_priv, SVGA_REG_ENABLE,
1213 			  SVGA_REG_ENABLE_HIDE |
1214 			  SVGA_REG_ENABLE_ENABLE);
1215 	}
1216 }
1217 
1218 /**
1219  * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo
1220  * running.
1221  *
1222  * @dev_priv: Pointer to device private struct.
1223  * Will empty VRAM.
1224  */
1225 void vmw_svga_disable(struct vmw_private *dev_priv)
1226 {
1227 	struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM);
1228 	/*
1229 	 * Disabling SVGA will turn off device modesetting capabilities, so
1230 	 * notify KMS about that so that it doesn't cache atomic state that
1231 	 * isn't valid anymore, for example crtcs turned on.
1232 	 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex),
1233 	 * but vmw_kms_lost_device() takes the reservation sem and thus we'll
1234 	 * end up with lock order reversal. Thus, a master may actually perform
1235 	 * a new modeset just after we call vmw_kms_lost_device() and race with
1236 	 * vmw_svga_disable(), but that should at worst cause atomic KMS state
1237 	 * to be inconsistent with the device, causing modesetting problems.
1238 	 *
1239 	 */
1240 	vmw_kms_lost_device(&dev_priv->drm);
1241 	ttm_write_lock(&dev_priv->reservation_sem, false);
1242 	if (ttm_resource_manager_used(man)) {
1243 		if (ttm_resource_manager_evict_all(&dev_priv->bdev, man))
1244 			DRM_ERROR("Failed evicting VRAM buffers.\n");
1245 		ttm_resource_manager_set_used(man, false);
1246 		vmw_write(dev_priv, SVGA_REG_ENABLE,
1247 			  SVGA_REG_ENABLE_HIDE |
1248 			  SVGA_REG_ENABLE_ENABLE);
1249 	}
1250 	ttm_write_unlock(&dev_priv->reservation_sem);
1251 }
1252 
1253 static void vmw_remove(struct pci_dev *pdev)
1254 {
1255 	struct drm_device *dev = pci_get_drvdata(pdev);
1256 
1257 	ttm_mem_global_release(&ttm_mem_glob);
1258 	drm_dev_unregister(dev);
1259 	vmw_driver_unload(dev);
1260 }
1261 
1262 static unsigned long
1263 vmw_get_unmapped_area(struct file *file, unsigned long uaddr,
1264 		      unsigned long len, unsigned long pgoff,
1265 		      unsigned long flags)
1266 {
1267 	struct drm_file *file_priv = file->private_data;
1268 	struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev);
1269 
1270 	return drm_get_unmapped_area(file, uaddr, len, pgoff, flags,
1271 				     &dev_priv->vma_manager);
1272 }
1273 
1274 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
1275 			      void *ptr)
1276 {
1277 	struct vmw_private *dev_priv =
1278 		container_of(nb, struct vmw_private, pm_nb);
1279 
1280 	switch (val) {
1281 	case PM_HIBERNATION_PREPARE:
1282 		/*
1283 		 * Take the reservation sem in write mode, which will make sure
1284 		 * there are no other processes holding a buffer object
1285 		 * reservation, meaning we should be able to evict all buffer
1286 		 * objects if needed.
1287 		 * Once user-space processes have been frozen, we can release
1288 		 * the lock again.
1289 		 */
1290 		ttm_suspend_lock(&dev_priv->reservation_sem);
1291 		dev_priv->suspend_locked = true;
1292 		break;
1293 	case PM_POST_HIBERNATION:
1294 	case PM_POST_RESTORE:
1295 		if (READ_ONCE(dev_priv->suspend_locked)) {
1296 			dev_priv->suspend_locked = false;
1297 			ttm_suspend_unlock(&dev_priv->reservation_sem);
1298 		}
1299 		break;
1300 	default:
1301 		break;
1302 	}
1303 	return 0;
1304 }
1305 
1306 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1307 {
1308 	struct drm_device *dev = pci_get_drvdata(pdev);
1309 	struct vmw_private *dev_priv = vmw_priv(dev);
1310 
1311 	if (dev_priv->refuse_hibernation)
1312 		return -EBUSY;
1313 
1314 	pci_save_state(pdev);
1315 	pci_disable_device(pdev);
1316 	pci_set_power_state(pdev, PCI_D3hot);
1317 	return 0;
1318 }
1319 
1320 static int vmw_pci_resume(struct pci_dev *pdev)
1321 {
1322 	pci_set_power_state(pdev, PCI_D0);
1323 	pci_restore_state(pdev);
1324 	return pci_enable_device(pdev);
1325 }
1326 
1327 static int vmw_pm_suspend(struct device *kdev)
1328 {
1329 	struct pci_dev *pdev = to_pci_dev(kdev);
1330 	struct pm_message dummy;
1331 
1332 	dummy.event = 0;
1333 
1334 	return vmw_pci_suspend(pdev, dummy);
1335 }
1336 
1337 static int vmw_pm_resume(struct device *kdev)
1338 {
1339 	struct pci_dev *pdev = to_pci_dev(kdev);
1340 
1341 	return vmw_pci_resume(pdev);
1342 }
1343 
1344 static int vmw_pm_freeze(struct device *kdev)
1345 {
1346 	struct pci_dev *pdev = to_pci_dev(kdev);
1347 	struct drm_device *dev = pci_get_drvdata(pdev);
1348 	struct vmw_private *dev_priv = vmw_priv(dev);
1349 	struct ttm_operation_ctx ctx = {
1350 		.interruptible = false,
1351 		.no_wait_gpu = false
1352 	};
1353 	int ret;
1354 
1355 	/*
1356 	 * Unlock for vmw_kms_suspend.
1357 	 * No user-space processes should be running now.
1358 	 */
1359 	ttm_suspend_unlock(&dev_priv->reservation_sem);
1360 	ret = vmw_kms_suspend(&dev_priv->drm);
1361 	if (ret) {
1362 		ttm_suspend_lock(&dev_priv->reservation_sem);
1363 		DRM_ERROR("Failed to freeze modesetting.\n");
1364 		return ret;
1365 	}
1366 	if (dev_priv->enable_fb)
1367 		vmw_fb_off(dev_priv);
1368 
1369 	ttm_suspend_lock(&dev_priv->reservation_sem);
1370 	vmw_execbuf_release_pinned_bo(dev_priv);
1371 	vmw_resource_evict_all(dev_priv);
1372 	vmw_release_device_early(dev_priv);
1373 	while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0);
1374 	if (dev_priv->enable_fb)
1375 		vmw_fifo_resource_dec(dev_priv);
1376 	if (atomic_read(&dev_priv->num_fifo_resources) != 0) {
1377 		DRM_ERROR("Can't hibernate while 3D resources are active.\n");
1378 		if (dev_priv->enable_fb)
1379 			vmw_fifo_resource_inc(dev_priv);
1380 		WARN_ON(vmw_request_device_late(dev_priv));
1381 		dev_priv->suspend_locked = false;
1382 		ttm_suspend_unlock(&dev_priv->reservation_sem);
1383 		if (dev_priv->suspend_state)
1384 			vmw_kms_resume(dev);
1385 		if (dev_priv->enable_fb)
1386 			vmw_fb_on(dev_priv);
1387 		return -EBUSY;
1388 	}
1389 
1390 	vmw_fence_fifo_down(dev_priv->fman);
1391 	__vmw_svga_disable(dev_priv);
1392 
1393 	vmw_release_device_late(dev_priv);
1394 	return 0;
1395 }
1396 
1397 static int vmw_pm_restore(struct device *kdev)
1398 {
1399 	struct pci_dev *pdev = to_pci_dev(kdev);
1400 	struct drm_device *dev = pci_get_drvdata(pdev);
1401 	struct vmw_private *dev_priv = vmw_priv(dev);
1402 	int ret;
1403 
1404 	vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
1405 	(void) vmw_read(dev_priv, SVGA_REG_ID);
1406 
1407 	if (dev_priv->enable_fb)
1408 		vmw_fifo_resource_inc(dev_priv);
1409 
1410 	ret = vmw_request_device(dev_priv);
1411 	if (ret)
1412 		return ret;
1413 
1414 	if (dev_priv->enable_fb)
1415 		__vmw_svga_enable(dev_priv);
1416 
1417 	vmw_fence_fifo_up(dev_priv->fman);
1418 	dev_priv->suspend_locked = false;
1419 	ttm_suspend_unlock(&dev_priv->reservation_sem);
1420 	if (dev_priv->suspend_state)
1421 		vmw_kms_resume(&dev_priv->drm);
1422 
1423 	if (dev_priv->enable_fb)
1424 		vmw_fb_on(dev_priv);
1425 
1426 	return 0;
1427 }
1428 
1429 static const struct dev_pm_ops vmw_pm_ops = {
1430 	.freeze = vmw_pm_freeze,
1431 	.thaw = vmw_pm_restore,
1432 	.restore = vmw_pm_restore,
1433 	.suspend = vmw_pm_suspend,
1434 	.resume = vmw_pm_resume,
1435 };
1436 
1437 static const struct file_operations vmwgfx_driver_fops = {
1438 	.owner = THIS_MODULE,
1439 	.open = drm_open,
1440 	.release = drm_release,
1441 	.unlocked_ioctl = vmw_unlocked_ioctl,
1442 	.mmap = vmw_mmap,
1443 	.poll = vmw_fops_poll,
1444 	.read = vmw_fops_read,
1445 #if defined(CONFIG_COMPAT)
1446 	.compat_ioctl = vmw_compat_ioctl,
1447 #endif
1448 	.llseek = noop_llseek,
1449 	.get_unmapped_area = vmw_get_unmapped_area,
1450 };
1451 
1452 static const struct drm_driver driver = {
1453 	.driver_features =
1454 	DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC,
1455 	.ioctls = vmw_ioctls,
1456 	.num_ioctls = ARRAY_SIZE(vmw_ioctls),
1457 	.master_set = vmw_master_set,
1458 	.master_drop = vmw_master_drop,
1459 	.open = vmw_driver_open,
1460 	.postclose = vmw_postclose,
1461 
1462 	.dumb_create = vmw_dumb_create,
1463 	.dumb_map_offset = vmw_dumb_map_offset,
1464 	.dumb_destroy = vmw_dumb_destroy,
1465 
1466 	.prime_fd_to_handle = vmw_prime_fd_to_handle,
1467 	.prime_handle_to_fd = vmw_prime_handle_to_fd,
1468 
1469 	.fops = &vmwgfx_driver_fops,
1470 	.name = VMWGFX_DRIVER_NAME,
1471 	.desc = VMWGFX_DRIVER_DESC,
1472 	.date = VMWGFX_DRIVER_DATE,
1473 	.major = VMWGFX_DRIVER_MAJOR,
1474 	.minor = VMWGFX_DRIVER_MINOR,
1475 	.patchlevel = VMWGFX_DRIVER_PATCHLEVEL
1476 };
1477 
1478 static struct pci_driver vmw_pci_driver = {
1479 	.name = VMWGFX_DRIVER_NAME,
1480 	.id_table = vmw_pci_id_list,
1481 	.probe = vmw_probe,
1482 	.remove = vmw_remove,
1483 	.driver = {
1484 		.pm = &vmw_pm_ops
1485 	}
1486 };
1487 
1488 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1489 {
1490 	struct vmw_private *vmw;
1491 	int ret;
1492 
1493 	ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "svgadrmfb");
1494 	if (ret)
1495 		return ret;
1496 
1497 	ret = pcim_enable_device(pdev);
1498 	if (ret)
1499 		return ret;
1500 
1501 	vmw = devm_drm_dev_alloc(&pdev->dev, &driver,
1502 				 struct vmw_private, drm);
1503 	if (IS_ERR(vmw))
1504 		return PTR_ERR(vmw);
1505 
1506 	pci_set_drvdata(pdev, &vmw->drm);
1507 
1508 	ret = ttm_mem_global_init(&ttm_mem_glob, &pdev->dev);
1509 	if (ret)
1510 		return ret;
1511 
1512 	ret = vmw_driver_load(vmw, ent->device);
1513 	if (ret)
1514 		return ret;
1515 
1516 	ret = drm_dev_register(&vmw->drm, 0);
1517 	if (ret) {
1518 		vmw_driver_unload(&vmw->drm);
1519 		return ret;
1520 	}
1521 
1522 	return 0;
1523 }
1524 
1525 static int __init vmwgfx_init(void)
1526 {
1527 	int ret;
1528 
1529 	if (vgacon_text_force())
1530 		return -EINVAL;
1531 
1532 	ret = pci_register_driver(&vmw_pci_driver);
1533 	if (ret)
1534 		DRM_ERROR("Failed initializing DRM.\n");
1535 	return ret;
1536 }
1537 
1538 static void __exit vmwgfx_exit(void)
1539 {
1540 	pci_unregister_driver(&vmw_pci_driver);
1541 }
1542 
1543 module_init(vmwgfx_init);
1544 module_exit(vmwgfx_exit);
1545 
1546 MODULE_AUTHOR("VMware Inc. and others");
1547 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
1548 MODULE_LICENSE("GPL and additional rights");
1549 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
1550 	       __stringify(VMWGFX_DRIVER_MINOR) "."
1551 	       __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
1552 	       "0");
1553