1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include <linux/console.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/mem_encrypt.h> 33 34 #include <drm/drm_drv.h> 35 #include <drm/drm_ioctl.h> 36 #include <drm/drm_sysfs.h> 37 #include <drm/ttm/ttm_bo_driver.h> 38 #include <drm/ttm/ttm_module.h> 39 #include <drm/ttm/ttm_placement.h> 40 41 #include "ttm_object.h" 42 #include "vmwgfx_binding.h" 43 #include "vmwgfx_drv.h" 44 45 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 46 #define VMWGFX_CHIP_SVGAII 0 47 #define VMW_FB_RESERVATION 0 48 49 #define VMW_MIN_INITIAL_WIDTH 800 50 #define VMW_MIN_INITIAL_HEIGHT 600 51 52 #ifndef VMWGFX_GIT_VERSION 53 #define VMWGFX_GIT_VERSION "Unknown" 54 #endif 55 56 #define VMWGFX_REPO "In Tree" 57 58 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 59 60 61 /** 62 * Fully encoded drm commands. Might move to vmw_drm.h 63 */ 64 65 #define DRM_IOCTL_VMW_GET_PARAM \ 66 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 67 struct drm_vmw_getparam_arg) 68 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 69 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 70 union drm_vmw_alloc_dmabuf_arg) 71 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 72 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 73 struct drm_vmw_unref_dmabuf_arg) 74 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 75 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 76 struct drm_vmw_cursor_bypass_arg) 77 78 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 80 struct drm_vmw_control_stream_arg) 81 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 82 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 83 struct drm_vmw_stream_arg) 84 #define DRM_IOCTL_VMW_UNREF_STREAM \ 85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 86 struct drm_vmw_stream_arg) 87 88 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 89 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 90 struct drm_vmw_context_arg) 91 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 93 struct drm_vmw_context_arg) 94 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 96 union drm_vmw_surface_create_arg) 97 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 99 struct drm_vmw_surface_arg) 100 #define DRM_IOCTL_VMW_REF_SURFACE \ 101 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 102 union drm_vmw_surface_reference_arg) 103 #define DRM_IOCTL_VMW_EXECBUF \ 104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 105 struct drm_vmw_execbuf_arg) 106 #define DRM_IOCTL_VMW_GET_3D_CAP \ 107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 108 struct drm_vmw_get_3d_cap_arg) 109 #define DRM_IOCTL_VMW_FENCE_WAIT \ 110 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 111 struct drm_vmw_fence_wait_arg) 112 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 113 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 114 struct drm_vmw_fence_signaled_arg) 115 #define DRM_IOCTL_VMW_FENCE_UNREF \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 117 struct drm_vmw_fence_arg) 118 #define DRM_IOCTL_VMW_FENCE_EVENT \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 120 struct drm_vmw_fence_event_arg) 121 #define DRM_IOCTL_VMW_PRESENT \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 123 struct drm_vmw_present_arg) 124 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 125 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 126 struct drm_vmw_present_readback_arg) 127 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 129 struct drm_vmw_update_layout_arg) 130 #define DRM_IOCTL_VMW_CREATE_SHADER \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 132 struct drm_vmw_shader_create_arg) 133 #define DRM_IOCTL_VMW_UNREF_SHADER \ 134 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 135 struct drm_vmw_shader_arg) 136 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 137 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 138 union drm_vmw_gb_surface_create_arg) 139 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 141 union drm_vmw_gb_surface_reference_arg) 142 #define DRM_IOCTL_VMW_SYNCCPU \ 143 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 144 struct drm_vmw_synccpu_arg) 145 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 147 struct drm_vmw_context_arg) 148 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 149 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 150 union drm_vmw_gb_surface_create_ext_arg) 151 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 152 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 153 union drm_vmw_gb_surface_reference_ext_arg) 154 #define DRM_IOCTL_VMW_MSG \ 155 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 156 struct drm_vmw_msg_arg) 157 158 /** 159 * The core DRM version of this macro doesn't account for 160 * DRM_COMMAND_BASE. 161 */ 162 163 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 164 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 165 166 /** 167 * Ioctl definitions. 168 */ 169 170 static const struct drm_ioctl_desc vmw_ioctls[] = { 171 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 172 DRM_RENDER_ALLOW), 173 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 174 DRM_RENDER_ALLOW), 175 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 176 DRM_RENDER_ALLOW), 177 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 178 vmw_kms_cursor_bypass_ioctl, 179 DRM_MASTER), 180 181 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 182 DRM_MASTER), 183 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 184 DRM_MASTER), 185 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 186 DRM_MASTER), 187 188 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 189 DRM_RENDER_ALLOW), 190 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 191 DRM_RENDER_ALLOW), 192 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 193 DRM_RENDER_ALLOW), 194 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 197 DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, 199 DRM_RENDER_ALLOW), 200 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 201 DRM_RENDER_ALLOW), 202 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 203 vmw_fence_obj_signaled_ioctl, 204 DRM_RENDER_ALLOW), 205 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 206 DRM_RENDER_ALLOW), 207 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 208 DRM_RENDER_ALLOW), 209 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 210 DRM_RENDER_ALLOW), 211 212 /* these allow direct access to the framebuffers mark as master only */ 213 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 214 DRM_MASTER | DRM_AUTH), 215 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 216 vmw_present_readback_ioctl, 217 DRM_MASTER | DRM_AUTH), 218 /* 219 * The permissions of the below ioctl are overridden in 220 * vmw_generic_ioctl(). We require either 221 * DRM_MASTER or capable(CAP_SYS_ADMIN). 222 */ 223 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 224 vmw_kms_update_layout_ioctl, 225 DRM_RENDER_ALLOW), 226 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 227 vmw_shader_define_ioctl, 228 DRM_RENDER_ALLOW), 229 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 230 vmw_shader_destroy_ioctl, 231 DRM_RENDER_ALLOW), 232 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 233 vmw_gb_surface_define_ioctl, 234 DRM_RENDER_ALLOW), 235 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 236 vmw_gb_surface_reference_ioctl, 237 DRM_RENDER_ALLOW), 238 VMW_IOCTL_DEF(VMW_SYNCCPU, 239 vmw_user_bo_synccpu_ioctl, 240 DRM_RENDER_ALLOW), 241 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 242 vmw_extended_context_define_ioctl, 243 DRM_RENDER_ALLOW), 244 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 245 vmw_gb_surface_define_ext_ioctl, 246 DRM_RENDER_ALLOW), 247 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 248 vmw_gb_surface_reference_ext_ioctl, 249 DRM_RENDER_ALLOW), 250 VMW_IOCTL_DEF(VMW_MSG, 251 vmw_msg_ioctl, 252 DRM_RENDER_ALLOW), 253 }; 254 255 static const struct pci_device_id vmw_pci_id_list[] = { 256 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 257 {0, 0, 0} 258 }; 259 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 260 261 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 262 static int vmw_force_iommu; 263 static int vmw_restrict_iommu; 264 static int vmw_force_coherent; 265 static int vmw_restrict_dma_mask; 266 static int vmw_assume_16bpp; 267 268 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 269 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 270 void *ptr); 271 272 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 273 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 274 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 275 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 276 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 277 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 278 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 279 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 280 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 281 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 282 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 283 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 284 285 286 static void vmw_print_capabilities2(uint32_t capabilities2) 287 { 288 DRM_INFO("Capabilities2:\n"); 289 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 290 DRM_INFO(" Grow oTable.\n"); 291 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 292 DRM_INFO(" IntraSurface copy.\n"); 293 if (capabilities2 & SVGA_CAP2_DX3) 294 DRM_INFO(" DX3.\n"); 295 } 296 297 static void vmw_print_capabilities(uint32_t capabilities) 298 { 299 DRM_INFO("Capabilities:\n"); 300 if (capabilities & SVGA_CAP_RECT_COPY) 301 DRM_INFO(" Rect copy.\n"); 302 if (capabilities & SVGA_CAP_CURSOR) 303 DRM_INFO(" Cursor.\n"); 304 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 305 DRM_INFO(" Cursor bypass.\n"); 306 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 307 DRM_INFO(" Cursor bypass 2.\n"); 308 if (capabilities & SVGA_CAP_8BIT_EMULATION) 309 DRM_INFO(" 8bit emulation.\n"); 310 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 311 DRM_INFO(" Alpha cursor.\n"); 312 if (capabilities & SVGA_CAP_3D) 313 DRM_INFO(" 3D.\n"); 314 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 315 DRM_INFO(" Extended Fifo.\n"); 316 if (capabilities & SVGA_CAP_MULTIMON) 317 DRM_INFO(" Multimon.\n"); 318 if (capabilities & SVGA_CAP_PITCHLOCK) 319 DRM_INFO(" Pitchlock.\n"); 320 if (capabilities & SVGA_CAP_IRQMASK) 321 DRM_INFO(" Irq mask.\n"); 322 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 323 DRM_INFO(" Display Topology.\n"); 324 if (capabilities & SVGA_CAP_GMR) 325 DRM_INFO(" GMR.\n"); 326 if (capabilities & SVGA_CAP_TRACES) 327 DRM_INFO(" Traces.\n"); 328 if (capabilities & SVGA_CAP_GMR2) 329 DRM_INFO(" GMR2.\n"); 330 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 331 DRM_INFO(" Screen Object 2.\n"); 332 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 333 DRM_INFO(" Command Buffers.\n"); 334 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 335 DRM_INFO(" Command Buffers 2.\n"); 336 if (capabilities & SVGA_CAP_GBOBJECTS) 337 DRM_INFO(" Guest Backed Resources.\n"); 338 if (capabilities & SVGA_CAP_DX) 339 DRM_INFO(" DX Features.\n"); 340 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 341 DRM_INFO(" HP Command Queue.\n"); 342 } 343 344 /** 345 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 346 * 347 * @dev_priv: A device private structure. 348 * 349 * This function creates a small buffer object that holds the query 350 * result for dummy queries emitted as query barriers. 351 * The function will then map the first page and initialize a pending 352 * occlusion query result structure, Finally it will unmap the buffer. 353 * No interruptible waits are done within this function. 354 * 355 * Returns an error if bo creation or initialization fails. 356 */ 357 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 358 { 359 int ret; 360 struct vmw_buffer_object *vbo; 361 struct ttm_bo_kmap_obj map; 362 volatile SVGA3dQueryResult *result; 363 bool dummy; 364 365 /* 366 * Create the vbo as pinned, so that a tryreserve will 367 * immediately succeed. This is because we're the only 368 * user of the bo currently. 369 */ 370 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 371 if (!vbo) 372 return -ENOMEM; 373 374 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 375 &vmw_sys_placement, false, true, 376 &vmw_bo_bo_free); 377 if (unlikely(ret != 0)) 378 return ret; 379 380 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 381 BUG_ON(ret != 0); 382 vmw_bo_pin_reserved(vbo, true); 383 384 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 385 if (likely(ret == 0)) { 386 result = ttm_kmap_obj_virtual(&map, &dummy); 387 result->totalSize = sizeof(*result); 388 result->state = SVGA3D_QUERYSTATE_PENDING; 389 result->result32 = 0xff; 390 ttm_bo_kunmap(&map); 391 } 392 vmw_bo_pin_reserved(vbo, false); 393 ttm_bo_unreserve(&vbo->base); 394 395 if (unlikely(ret != 0)) { 396 DRM_ERROR("Dummy query buffer map failed.\n"); 397 vmw_bo_unreference(&vbo); 398 } else 399 dev_priv->dummy_query_bo = vbo; 400 401 return ret; 402 } 403 404 /** 405 * vmw_request_device_late - Perform late device setup 406 * 407 * @dev_priv: Pointer to device private. 408 * 409 * This function performs setup of otables and enables large command 410 * buffer submission. These tasks are split out to a separate function 411 * because it reverts vmw_release_device_early and is intended to be used 412 * by an error path in the hibernation code. 413 */ 414 static int vmw_request_device_late(struct vmw_private *dev_priv) 415 { 416 int ret; 417 418 if (dev_priv->has_mob) { 419 ret = vmw_otables_setup(dev_priv); 420 if (unlikely(ret != 0)) { 421 DRM_ERROR("Unable to initialize " 422 "guest Memory OBjects.\n"); 423 return ret; 424 } 425 } 426 427 if (dev_priv->cman) { 428 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 429 256*4096, 2*4096); 430 if (ret) { 431 struct vmw_cmdbuf_man *man = dev_priv->cman; 432 433 dev_priv->cman = NULL; 434 vmw_cmdbuf_man_destroy(man); 435 } 436 } 437 438 return 0; 439 } 440 441 static int vmw_request_device(struct vmw_private *dev_priv) 442 { 443 int ret; 444 445 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 446 if (unlikely(ret != 0)) { 447 DRM_ERROR("Unable to initialize FIFO.\n"); 448 return ret; 449 } 450 vmw_fence_fifo_up(dev_priv->fman); 451 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 452 if (IS_ERR(dev_priv->cman)) { 453 dev_priv->cman = NULL; 454 dev_priv->sm_type = VMW_SM_LEGACY; 455 } 456 457 ret = vmw_request_device_late(dev_priv); 458 if (ret) 459 goto out_no_mob; 460 461 ret = vmw_dummy_query_bo_create(dev_priv); 462 if (unlikely(ret != 0)) 463 goto out_no_query_bo; 464 465 return 0; 466 467 out_no_query_bo: 468 if (dev_priv->cman) 469 vmw_cmdbuf_remove_pool(dev_priv->cman); 470 if (dev_priv->has_mob) { 471 struct ttm_resource_manager *man; 472 473 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 474 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 475 vmw_otables_takedown(dev_priv); 476 } 477 if (dev_priv->cman) 478 vmw_cmdbuf_man_destroy(dev_priv->cman); 479 out_no_mob: 480 vmw_fence_fifo_down(dev_priv->fman); 481 vmw_fifo_release(dev_priv, &dev_priv->fifo); 482 return ret; 483 } 484 485 /** 486 * vmw_release_device_early - Early part of fifo takedown. 487 * 488 * @dev_priv: Pointer to device private struct. 489 * 490 * This is the first part of command submission takedown, to be called before 491 * buffer management is taken down. 492 */ 493 static void vmw_release_device_early(struct vmw_private *dev_priv) 494 { 495 /* 496 * Previous destructions should've released 497 * the pinned bo. 498 */ 499 500 BUG_ON(dev_priv->pinned_bo != NULL); 501 502 vmw_bo_unreference(&dev_priv->dummy_query_bo); 503 if (dev_priv->cman) 504 vmw_cmdbuf_remove_pool(dev_priv->cman); 505 506 if (dev_priv->has_mob) { 507 struct ttm_resource_manager *man; 508 509 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 510 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 511 vmw_otables_takedown(dev_priv); 512 } 513 } 514 515 /** 516 * vmw_release_device_late - Late part of fifo takedown. 517 * 518 * @dev_priv: Pointer to device private struct. 519 * 520 * This is the last part of the command submission takedown, to be called when 521 * command submission is no longer needed. It may wait on pending fences. 522 */ 523 static void vmw_release_device_late(struct vmw_private *dev_priv) 524 { 525 vmw_fence_fifo_down(dev_priv->fman); 526 if (dev_priv->cman) 527 vmw_cmdbuf_man_destroy(dev_priv->cman); 528 529 vmw_fifo_release(dev_priv, &dev_priv->fifo); 530 } 531 532 /** 533 * Sets the initial_[width|height] fields on the given vmw_private. 534 * 535 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 536 * clamping the value to fb_max_[width|height] fields and the 537 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 538 * If the values appear to be invalid, set them to 539 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 540 */ 541 static void vmw_get_initial_size(struct vmw_private *dev_priv) 542 { 543 uint32_t width; 544 uint32_t height; 545 546 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 547 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 548 549 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 550 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 551 552 if (width > dev_priv->fb_max_width || 553 height > dev_priv->fb_max_height) { 554 555 /* 556 * This is a host error and shouldn't occur. 557 */ 558 559 width = VMW_MIN_INITIAL_WIDTH; 560 height = VMW_MIN_INITIAL_HEIGHT; 561 } 562 563 dev_priv->initial_width = width; 564 dev_priv->initial_height = height; 565 } 566 567 /** 568 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 569 * system. 570 * 571 * @dev_priv: Pointer to a struct vmw_private 572 * 573 * This functions tries to determine what actions need to be taken by the 574 * driver to make system pages visible to the device. 575 * If this function decides that DMA is not possible, it returns -EINVAL. 576 * The driver may then try to disable features of the device that require 577 * DMA. 578 */ 579 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 580 { 581 static const char *names[vmw_dma_map_max] = { 582 [vmw_dma_phys] = "Using physical TTM page addresses.", 583 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 584 [vmw_dma_map_populate] = "Caching DMA mappings.", 585 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 586 587 /* TTM currently doesn't fully support SEV encryption. */ 588 if (mem_encrypt_active()) 589 return -EINVAL; 590 591 if (vmw_force_coherent) 592 dev_priv->map_mode = vmw_dma_alloc_coherent; 593 else if (vmw_restrict_iommu) 594 dev_priv->map_mode = vmw_dma_map_bind; 595 else 596 dev_priv->map_mode = vmw_dma_map_populate; 597 598 if (!IS_ENABLED(CONFIG_DRM_TTM_DMA_PAGE_POOL) && 599 (dev_priv->map_mode == vmw_dma_alloc_coherent)) 600 return -EINVAL; 601 602 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 603 return 0; 604 } 605 606 /** 607 * vmw_dma_masks - set required page- and dma masks 608 * 609 * @dev: Pointer to struct drm-device 610 * 611 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 612 * restriction also for 64-bit systems. 613 */ 614 static int vmw_dma_masks(struct vmw_private *dev_priv) 615 { 616 struct drm_device *dev = dev_priv->dev; 617 int ret = 0; 618 619 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 620 if (dev_priv->map_mode != vmw_dma_phys && 621 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 622 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 623 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 624 } 625 626 return ret; 627 } 628 629 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 630 { 631 int ret; 632 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 633 ret = vmw_thp_init(dev_priv); 634 #else 635 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 636 dev_priv->vram_size >> PAGE_SHIFT); 637 #endif 638 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 639 return ret; 640 } 641 642 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 643 { 644 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 645 vmw_thp_fini(dev_priv); 646 #else 647 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 648 #endif 649 } 650 651 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 652 { 653 struct vmw_private *dev_priv; 654 int ret; 655 uint32_t svga_id; 656 enum vmw_res_type i; 657 bool refuse_dma = false; 658 char host_log[100] = {0}; 659 660 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 661 if (unlikely(!dev_priv)) { 662 DRM_ERROR("Failed allocating a device private struct.\n"); 663 return -ENOMEM; 664 } 665 666 pci_set_master(dev->pdev); 667 668 dev_priv->dev = dev; 669 dev_priv->vmw_chipset = chipset; 670 dev_priv->last_read_seqno = (uint32_t) -100; 671 mutex_init(&dev_priv->cmdbuf_mutex); 672 mutex_init(&dev_priv->release_mutex); 673 mutex_init(&dev_priv->binding_mutex); 674 mutex_init(&dev_priv->global_kms_state_mutex); 675 ttm_lock_init(&dev_priv->reservation_sem); 676 spin_lock_init(&dev_priv->resource_lock); 677 spin_lock_init(&dev_priv->hw_lock); 678 spin_lock_init(&dev_priv->waiter_lock); 679 spin_lock_init(&dev_priv->cap_lock); 680 spin_lock_init(&dev_priv->svga_lock); 681 spin_lock_init(&dev_priv->cursor_lock); 682 683 for (i = vmw_res_context; i < vmw_res_max; ++i) { 684 idr_init(&dev_priv->res_idr[i]); 685 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 686 } 687 688 init_waitqueue_head(&dev_priv->fence_queue); 689 init_waitqueue_head(&dev_priv->fifo_queue); 690 dev_priv->fence_queue_waiters = 0; 691 dev_priv->fifo_queue_waiters = 0; 692 693 dev_priv->used_memory_size = 0; 694 695 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 696 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 697 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 698 699 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 700 701 dev_priv->enable_fb = enable_fbdev; 702 703 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 704 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 705 if (svga_id != SVGA_ID_2) { 706 ret = -ENOSYS; 707 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 708 goto out_err0; 709 } 710 711 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 712 713 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 714 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 715 } 716 717 718 ret = vmw_dma_select_mode(dev_priv); 719 if (unlikely(ret != 0)) { 720 DRM_INFO("Restricting capabilities since DMA not available.\n"); 721 refuse_dma = true; 722 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 723 DRM_INFO("Disabling 3D acceleration.\n"); 724 } 725 726 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 727 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 728 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 729 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 730 731 vmw_get_initial_size(dev_priv); 732 733 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 734 dev_priv->max_gmr_ids = 735 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 736 dev_priv->max_gmr_pages = 737 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 738 dev_priv->memory_size = 739 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 740 dev_priv->memory_size -= dev_priv->vram_size; 741 } else { 742 /* 743 * An arbitrary limit of 512MiB on surface 744 * memory. But all HWV8 hardware supports GMR2. 745 */ 746 dev_priv->memory_size = 512*1024*1024; 747 } 748 dev_priv->max_mob_pages = 0; 749 dev_priv->max_mob_size = 0; 750 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 751 uint64_t mem_size; 752 753 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 754 mem_size = vmw_read(dev_priv, 755 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 756 else 757 mem_size = 758 vmw_read(dev_priv, 759 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 760 761 /* 762 * Workaround for low memory 2D VMs to compensate for the 763 * allocation taken by fbdev 764 */ 765 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 766 mem_size *= 3; 767 768 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 769 dev_priv->prim_bb_mem = 770 vmw_read(dev_priv, 771 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 772 dev_priv->max_mob_size = 773 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 774 dev_priv->stdu_max_width = 775 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 776 dev_priv->stdu_max_height = 777 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 778 779 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 780 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 781 dev_priv->texture_max_width = vmw_read(dev_priv, 782 SVGA_REG_DEV_CAP); 783 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 784 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 785 dev_priv->texture_max_height = vmw_read(dev_priv, 786 SVGA_REG_DEV_CAP); 787 } else { 788 dev_priv->texture_max_width = 8192; 789 dev_priv->texture_max_height = 8192; 790 dev_priv->prim_bb_mem = dev_priv->vram_size; 791 } 792 793 vmw_print_capabilities(dev_priv->capabilities); 794 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 795 vmw_print_capabilities2(dev_priv->capabilities2); 796 797 ret = vmw_dma_masks(dev_priv); 798 if (unlikely(ret != 0)) 799 goto out_err0; 800 801 dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK, 802 SCATTERLIST_MAX_SEGMENT)); 803 804 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 805 DRM_INFO("Max GMR ids is %u\n", 806 (unsigned)dev_priv->max_gmr_ids); 807 DRM_INFO("Max number of GMR pages is %u\n", 808 (unsigned)dev_priv->max_gmr_pages); 809 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 810 (unsigned)dev_priv->memory_size / 1024); 811 } 812 DRM_INFO("Maximum display memory size is %u kiB\n", 813 dev_priv->prim_bb_mem / 1024); 814 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 815 dev_priv->vram_start, dev_priv->vram_size / 1024); 816 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 817 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 818 819 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 820 dev_priv->mmio_size, MEMREMAP_WB); 821 822 if (unlikely(dev_priv->mmio_virt == NULL)) { 823 ret = -ENOMEM; 824 DRM_ERROR("Failed mapping MMIO.\n"); 825 goto out_err0; 826 } 827 828 /* Need mmio memory to check for fifo pitchlock cap. */ 829 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 830 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 831 !vmw_fifo_have_pitchlock(dev_priv)) { 832 ret = -ENOSYS; 833 DRM_ERROR("Hardware has no pitchlock\n"); 834 goto out_err4; 835 } 836 837 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 838 &vmw_prime_dmabuf_ops); 839 840 if (unlikely(dev_priv->tdev == NULL)) { 841 DRM_ERROR("Unable to initialize TTM object management.\n"); 842 ret = -ENOMEM; 843 goto out_err4; 844 } 845 846 dev->dev_private = dev_priv; 847 848 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 849 dev_priv->stealth = (ret != 0); 850 if (dev_priv->stealth) { 851 /** 852 * Request at least the mmio PCI resource. 853 */ 854 855 DRM_INFO("It appears like vesafb is loaded. " 856 "Ignore above error if any.\n"); 857 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 858 if (unlikely(ret != 0)) { 859 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 860 goto out_no_device; 861 } 862 } 863 864 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 865 ret = vmw_irq_install(dev, dev->pdev->irq); 866 if (ret != 0) { 867 DRM_ERROR("Failed installing irq: %d\n", ret); 868 goto out_no_irq; 869 } 870 } 871 872 dev_priv->fman = vmw_fence_manager_init(dev_priv); 873 if (unlikely(dev_priv->fman == NULL)) { 874 ret = -ENOMEM; 875 goto out_no_fman; 876 } 877 878 drm_vma_offset_manager_init(&dev_priv->vma_manager, 879 DRM_FILE_PAGE_OFFSET_START, 880 DRM_FILE_PAGE_OFFSET_SIZE); 881 ret = ttm_bo_device_init(&dev_priv->bdev, 882 &vmw_bo_driver, 883 dev->anon_inode->i_mapping, 884 &dev_priv->vma_manager, 885 false); 886 if (unlikely(ret != 0)) { 887 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 888 goto out_no_bdev; 889 } 890 891 /* 892 * Enable VRAM, but initially don't use it until SVGA is enabled and 893 * unhidden. 894 */ 895 896 ret = vmw_vram_manager_init(dev_priv); 897 if (unlikely(ret != 0)) { 898 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 899 goto out_no_vram; 900 } 901 902 /* 903 * "Guest Memory Regions" is an aperture like feature with 904 * one slot per bo. There is an upper limit of the number of 905 * slots as well as the bo size. 906 */ 907 dev_priv->has_gmr = true; 908 /* TODO: This is most likely not correct */ 909 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 910 refuse_dma || 911 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 912 DRM_INFO("No GMR memory available. " 913 "Graphics memory resources are very limited.\n"); 914 dev_priv->has_gmr = false; 915 } 916 917 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 918 dev_priv->has_mob = true; 919 920 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 921 DRM_INFO("No MOB memory available. " 922 "3D will be disabled.\n"); 923 dev_priv->has_mob = false; 924 } 925 } 926 927 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 928 spin_lock(&dev_priv->cap_lock); 929 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 930 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 931 dev_priv->sm_type = VMW_SM_4; 932 spin_unlock(&dev_priv->cap_lock); 933 } 934 935 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 936 937 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 938 if (has_sm4_context(dev_priv) && 939 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 940 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM41); 941 942 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 943 dev_priv->sm_type = VMW_SM_4_1; 944 945 if (has_sm4_1_context(dev_priv) && 946 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 947 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM5); 948 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 949 dev_priv->sm_type = VMW_SM_5; 950 } 951 } 952 953 ret = vmw_kms_init(dev_priv); 954 if (unlikely(ret != 0)) 955 goto out_no_kms; 956 vmw_overlay_init(dev_priv); 957 958 ret = vmw_request_device(dev_priv); 959 if (ret) 960 goto out_no_fifo; 961 962 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 963 ? "yes." : "no."); 964 if (dev_priv->sm_type == VMW_SM_5) 965 DRM_INFO("SM5 support available.\n"); 966 if (dev_priv->sm_type == VMW_SM_4_1) 967 DRM_INFO("SM4_1 support available.\n"); 968 if (dev_priv->sm_type == VMW_SM_4) 969 DRM_INFO("SM4 support available.\n"); 970 971 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 972 VMWGFX_REPO, VMWGFX_GIT_VERSION); 973 vmw_host_log(host_log); 974 975 memset(host_log, 0, sizeof(host_log)); 976 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 977 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 978 VMWGFX_DRIVER_PATCHLEVEL); 979 vmw_host_log(host_log); 980 981 if (dev_priv->enable_fb) { 982 vmw_fifo_resource_inc(dev_priv); 983 vmw_svga_enable(dev_priv); 984 vmw_fb_init(dev_priv); 985 } 986 987 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 988 register_pm_notifier(&dev_priv->pm_nb); 989 990 return 0; 991 992 out_no_fifo: 993 vmw_overlay_close(dev_priv); 994 vmw_kms_close(dev_priv); 995 out_no_kms: 996 if (dev_priv->has_mob) 997 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 998 if (dev_priv->has_gmr) 999 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1000 vmw_vram_manager_fini(dev_priv); 1001 out_no_vram: 1002 (void)ttm_bo_device_release(&dev_priv->bdev); 1003 out_no_bdev: 1004 vmw_fence_manager_takedown(dev_priv->fman); 1005 out_no_fman: 1006 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1007 vmw_irq_uninstall(dev_priv->dev); 1008 out_no_irq: 1009 if (dev_priv->stealth) 1010 pci_release_region(dev->pdev, 2); 1011 else 1012 pci_release_regions(dev->pdev); 1013 out_no_device: 1014 ttm_object_device_release(&dev_priv->tdev); 1015 out_err4: 1016 memunmap(dev_priv->mmio_virt); 1017 out_err0: 1018 for (i = vmw_res_context; i < vmw_res_max; ++i) 1019 idr_destroy(&dev_priv->res_idr[i]); 1020 1021 if (dev_priv->ctx.staged_bindings) 1022 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1023 kfree(dev_priv); 1024 return ret; 1025 } 1026 1027 static void vmw_driver_unload(struct drm_device *dev) 1028 { 1029 struct vmw_private *dev_priv = vmw_priv(dev); 1030 enum vmw_res_type i; 1031 1032 unregister_pm_notifier(&dev_priv->pm_nb); 1033 1034 if (dev_priv->ctx.res_ht_initialized) 1035 drm_ht_remove(&dev_priv->ctx.res_ht); 1036 vfree(dev_priv->ctx.cmd_bounce); 1037 if (dev_priv->enable_fb) { 1038 vmw_fb_off(dev_priv); 1039 vmw_fb_close(dev_priv); 1040 vmw_fifo_resource_dec(dev_priv); 1041 vmw_svga_disable(dev_priv); 1042 } 1043 1044 vmw_kms_close(dev_priv); 1045 vmw_overlay_close(dev_priv); 1046 1047 if (dev_priv->has_gmr) 1048 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1049 1050 vmw_release_device_early(dev_priv); 1051 if (dev_priv->has_mob) 1052 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1053 vmw_vram_manager_fini(dev_priv); 1054 (void) ttm_bo_device_release(&dev_priv->bdev); 1055 drm_vma_offset_manager_destroy(&dev_priv->vma_manager); 1056 vmw_release_device_late(dev_priv); 1057 vmw_fence_manager_takedown(dev_priv->fman); 1058 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1059 vmw_irq_uninstall(dev_priv->dev); 1060 if (dev_priv->stealth) 1061 pci_release_region(dev->pdev, 2); 1062 else 1063 pci_release_regions(dev->pdev); 1064 1065 ttm_object_device_release(&dev_priv->tdev); 1066 memunmap(dev_priv->mmio_virt); 1067 if (dev_priv->ctx.staged_bindings) 1068 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1069 1070 for (i = vmw_res_context; i < vmw_res_max; ++i) 1071 idr_destroy(&dev_priv->res_idr[i]); 1072 1073 kfree(dev_priv); 1074 } 1075 1076 static void vmw_postclose(struct drm_device *dev, 1077 struct drm_file *file_priv) 1078 { 1079 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1080 1081 ttm_object_file_release(&vmw_fp->tfile); 1082 kfree(vmw_fp); 1083 } 1084 1085 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1086 { 1087 struct vmw_private *dev_priv = vmw_priv(dev); 1088 struct vmw_fpriv *vmw_fp; 1089 int ret = -ENOMEM; 1090 1091 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1092 if (unlikely(!vmw_fp)) 1093 return ret; 1094 1095 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1096 if (unlikely(vmw_fp->tfile == NULL)) 1097 goto out_no_tfile; 1098 1099 file_priv->driver_priv = vmw_fp; 1100 1101 return 0; 1102 1103 out_no_tfile: 1104 kfree(vmw_fp); 1105 return ret; 1106 } 1107 1108 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1109 unsigned long arg, 1110 long (*ioctl_func)(struct file *, unsigned int, 1111 unsigned long)) 1112 { 1113 struct drm_file *file_priv = filp->private_data; 1114 struct drm_device *dev = file_priv->minor->dev; 1115 unsigned int nr = DRM_IOCTL_NR(cmd); 1116 unsigned int flags; 1117 1118 /* 1119 * Do extra checking on driver private ioctls. 1120 */ 1121 1122 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1123 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1124 const struct drm_ioctl_desc *ioctl = 1125 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1126 1127 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1128 return ioctl_func(filp, cmd, arg); 1129 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1130 if (!drm_is_current_master(file_priv) && 1131 !capable(CAP_SYS_ADMIN)) 1132 return -EACCES; 1133 } 1134 1135 if (unlikely(ioctl->cmd != cmd)) 1136 goto out_io_encoding; 1137 1138 flags = ioctl->flags; 1139 } else if (!drm_ioctl_flags(nr, &flags)) 1140 return -EINVAL; 1141 1142 return ioctl_func(filp, cmd, arg); 1143 1144 out_io_encoding: 1145 DRM_ERROR("Invalid command format, ioctl %d\n", 1146 nr - DRM_COMMAND_BASE); 1147 1148 return -EINVAL; 1149 } 1150 1151 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1152 unsigned long arg) 1153 { 1154 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1155 } 1156 1157 #ifdef CONFIG_COMPAT 1158 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1159 unsigned long arg) 1160 { 1161 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1162 } 1163 #endif 1164 1165 static void vmw_master_set(struct drm_device *dev, 1166 struct drm_file *file_priv, 1167 bool from_open) 1168 { 1169 /* 1170 * Inform a new master that the layout may have changed while 1171 * it was gone. 1172 */ 1173 if (!from_open) 1174 drm_sysfs_hotplug_event(dev); 1175 } 1176 1177 static void vmw_master_drop(struct drm_device *dev, 1178 struct drm_file *file_priv) 1179 { 1180 struct vmw_private *dev_priv = vmw_priv(dev); 1181 1182 vmw_kms_legacy_hotspot_clear(dev_priv); 1183 if (!dev_priv->enable_fb) 1184 vmw_svga_disable(dev_priv); 1185 } 1186 1187 /** 1188 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1189 * 1190 * @dev_priv: Pointer to device private struct. 1191 * Needs the reservation sem to be held in non-exclusive mode. 1192 */ 1193 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1194 { 1195 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1196 1197 spin_lock(&dev_priv->svga_lock); 1198 if (!ttm_resource_manager_used(man)) { 1199 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1200 ttm_resource_manager_set_used(man, true); 1201 } 1202 spin_unlock(&dev_priv->svga_lock); 1203 } 1204 1205 /** 1206 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1207 * 1208 * @dev_priv: Pointer to device private struct. 1209 */ 1210 void vmw_svga_enable(struct vmw_private *dev_priv) 1211 { 1212 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1213 __vmw_svga_enable(dev_priv); 1214 ttm_read_unlock(&dev_priv->reservation_sem); 1215 } 1216 1217 /** 1218 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1219 * 1220 * @dev_priv: Pointer to device private struct. 1221 * Needs the reservation sem to be held in exclusive mode. 1222 * Will not empty VRAM. VRAM must be emptied by caller. 1223 */ 1224 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1225 { 1226 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1227 1228 spin_lock(&dev_priv->svga_lock); 1229 if (ttm_resource_manager_used(man)) { 1230 ttm_resource_manager_set_used(man, false); 1231 vmw_write(dev_priv, SVGA_REG_ENABLE, 1232 SVGA_REG_ENABLE_HIDE | 1233 SVGA_REG_ENABLE_ENABLE); 1234 } 1235 spin_unlock(&dev_priv->svga_lock); 1236 } 1237 1238 /** 1239 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1240 * running. 1241 * 1242 * @dev_priv: Pointer to device private struct. 1243 * Will empty VRAM. 1244 */ 1245 void vmw_svga_disable(struct vmw_private *dev_priv) 1246 { 1247 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1248 /* 1249 * Disabling SVGA will turn off device modesetting capabilities, so 1250 * notify KMS about that so that it doesn't cache atomic state that 1251 * isn't valid anymore, for example crtcs turned on. 1252 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1253 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1254 * end up with lock order reversal. Thus, a master may actually perform 1255 * a new modeset just after we call vmw_kms_lost_device() and race with 1256 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1257 * to be inconsistent with the device, causing modesetting problems. 1258 * 1259 */ 1260 vmw_kms_lost_device(dev_priv->dev); 1261 ttm_write_lock(&dev_priv->reservation_sem, false); 1262 spin_lock(&dev_priv->svga_lock); 1263 if (ttm_resource_manager_used(man)) { 1264 ttm_resource_manager_set_used(man, false); 1265 spin_unlock(&dev_priv->svga_lock); 1266 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1267 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1268 vmw_write(dev_priv, SVGA_REG_ENABLE, 1269 SVGA_REG_ENABLE_HIDE | 1270 SVGA_REG_ENABLE_ENABLE); 1271 } else 1272 spin_unlock(&dev_priv->svga_lock); 1273 ttm_write_unlock(&dev_priv->reservation_sem); 1274 } 1275 1276 static void vmw_remove(struct pci_dev *pdev) 1277 { 1278 struct drm_device *dev = pci_get_drvdata(pdev); 1279 1280 drm_dev_unregister(dev); 1281 vmw_driver_unload(dev); 1282 drm_dev_put(dev); 1283 pci_disable_device(pdev); 1284 } 1285 1286 static unsigned long 1287 vmw_get_unmapped_area(struct file *file, unsigned long uaddr, 1288 unsigned long len, unsigned long pgoff, 1289 unsigned long flags) 1290 { 1291 struct drm_file *file_priv = file->private_data; 1292 struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev); 1293 1294 return drm_get_unmapped_area(file, uaddr, len, pgoff, flags, 1295 &dev_priv->vma_manager); 1296 } 1297 1298 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1299 void *ptr) 1300 { 1301 struct vmw_private *dev_priv = 1302 container_of(nb, struct vmw_private, pm_nb); 1303 1304 switch (val) { 1305 case PM_HIBERNATION_PREPARE: 1306 /* 1307 * Take the reservation sem in write mode, which will make sure 1308 * there are no other processes holding a buffer object 1309 * reservation, meaning we should be able to evict all buffer 1310 * objects if needed. 1311 * Once user-space processes have been frozen, we can release 1312 * the lock again. 1313 */ 1314 ttm_suspend_lock(&dev_priv->reservation_sem); 1315 dev_priv->suspend_locked = true; 1316 break; 1317 case PM_POST_HIBERNATION: 1318 case PM_POST_RESTORE: 1319 if (READ_ONCE(dev_priv->suspend_locked)) { 1320 dev_priv->suspend_locked = false; 1321 ttm_suspend_unlock(&dev_priv->reservation_sem); 1322 } 1323 break; 1324 default: 1325 break; 1326 } 1327 return 0; 1328 } 1329 1330 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1331 { 1332 struct drm_device *dev = pci_get_drvdata(pdev); 1333 struct vmw_private *dev_priv = vmw_priv(dev); 1334 1335 if (dev_priv->refuse_hibernation) 1336 return -EBUSY; 1337 1338 pci_save_state(pdev); 1339 pci_disable_device(pdev); 1340 pci_set_power_state(pdev, PCI_D3hot); 1341 return 0; 1342 } 1343 1344 static int vmw_pci_resume(struct pci_dev *pdev) 1345 { 1346 pci_set_power_state(pdev, PCI_D0); 1347 pci_restore_state(pdev); 1348 return pci_enable_device(pdev); 1349 } 1350 1351 static int vmw_pm_suspend(struct device *kdev) 1352 { 1353 struct pci_dev *pdev = to_pci_dev(kdev); 1354 struct pm_message dummy; 1355 1356 dummy.event = 0; 1357 1358 return vmw_pci_suspend(pdev, dummy); 1359 } 1360 1361 static int vmw_pm_resume(struct device *kdev) 1362 { 1363 struct pci_dev *pdev = to_pci_dev(kdev); 1364 1365 return vmw_pci_resume(pdev); 1366 } 1367 1368 static int vmw_pm_freeze(struct device *kdev) 1369 { 1370 struct pci_dev *pdev = to_pci_dev(kdev); 1371 struct drm_device *dev = pci_get_drvdata(pdev); 1372 struct vmw_private *dev_priv = vmw_priv(dev); 1373 struct ttm_operation_ctx ctx = { 1374 .interruptible = false, 1375 .no_wait_gpu = false 1376 }; 1377 int ret; 1378 1379 /* 1380 * Unlock for vmw_kms_suspend. 1381 * No user-space processes should be running now. 1382 */ 1383 ttm_suspend_unlock(&dev_priv->reservation_sem); 1384 ret = vmw_kms_suspend(dev_priv->dev); 1385 if (ret) { 1386 ttm_suspend_lock(&dev_priv->reservation_sem); 1387 DRM_ERROR("Failed to freeze modesetting.\n"); 1388 return ret; 1389 } 1390 if (dev_priv->enable_fb) 1391 vmw_fb_off(dev_priv); 1392 1393 ttm_suspend_lock(&dev_priv->reservation_sem); 1394 vmw_execbuf_release_pinned_bo(dev_priv); 1395 vmw_resource_evict_all(dev_priv); 1396 vmw_release_device_early(dev_priv); 1397 while (ttm_bo_swapout(&ctx) == 0); 1398 if (dev_priv->enable_fb) 1399 vmw_fifo_resource_dec(dev_priv); 1400 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1401 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1402 if (dev_priv->enable_fb) 1403 vmw_fifo_resource_inc(dev_priv); 1404 WARN_ON(vmw_request_device_late(dev_priv)); 1405 dev_priv->suspend_locked = false; 1406 ttm_suspend_unlock(&dev_priv->reservation_sem); 1407 if (dev_priv->suspend_state) 1408 vmw_kms_resume(dev); 1409 if (dev_priv->enable_fb) 1410 vmw_fb_on(dev_priv); 1411 return -EBUSY; 1412 } 1413 1414 vmw_fence_fifo_down(dev_priv->fman); 1415 __vmw_svga_disable(dev_priv); 1416 1417 vmw_release_device_late(dev_priv); 1418 return 0; 1419 } 1420 1421 static int vmw_pm_restore(struct device *kdev) 1422 { 1423 struct pci_dev *pdev = to_pci_dev(kdev); 1424 struct drm_device *dev = pci_get_drvdata(pdev); 1425 struct vmw_private *dev_priv = vmw_priv(dev); 1426 int ret; 1427 1428 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1429 (void) vmw_read(dev_priv, SVGA_REG_ID); 1430 1431 if (dev_priv->enable_fb) 1432 vmw_fifo_resource_inc(dev_priv); 1433 1434 ret = vmw_request_device(dev_priv); 1435 if (ret) 1436 return ret; 1437 1438 if (dev_priv->enable_fb) 1439 __vmw_svga_enable(dev_priv); 1440 1441 vmw_fence_fifo_up(dev_priv->fman); 1442 dev_priv->suspend_locked = false; 1443 ttm_suspend_unlock(&dev_priv->reservation_sem); 1444 if (dev_priv->suspend_state) 1445 vmw_kms_resume(dev_priv->dev); 1446 1447 if (dev_priv->enable_fb) 1448 vmw_fb_on(dev_priv); 1449 1450 return 0; 1451 } 1452 1453 static const struct dev_pm_ops vmw_pm_ops = { 1454 .freeze = vmw_pm_freeze, 1455 .thaw = vmw_pm_restore, 1456 .restore = vmw_pm_restore, 1457 .suspend = vmw_pm_suspend, 1458 .resume = vmw_pm_resume, 1459 }; 1460 1461 static const struct file_operations vmwgfx_driver_fops = { 1462 .owner = THIS_MODULE, 1463 .open = drm_open, 1464 .release = drm_release, 1465 .unlocked_ioctl = vmw_unlocked_ioctl, 1466 .mmap = vmw_mmap, 1467 .poll = vmw_fops_poll, 1468 .read = vmw_fops_read, 1469 #if defined(CONFIG_COMPAT) 1470 .compat_ioctl = vmw_compat_ioctl, 1471 #endif 1472 .llseek = noop_llseek, 1473 .get_unmapped_area = vmw_get_unmapped_area, 1474 }; 1475 1476 static struct drm_driver driver = { 1477 .driver_features = 1478 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC, 1479 .ioctls = vmw_ioctls, 1480 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1481 .master_set = vmw_master_set, 1482 .master_drop = vmw_master_drop, 1483 .open = vmw_driver_open, 1484 .postclose = vmw_postclose, 1485 1486 .dumb_create = vmw_dumb_create, 1487 .dumb_map_offset = vmw_dumb_map_offset, 1488 .dumb_destroy = vmw_dumb_destroy, 1489 1490 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1491 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1492 1493 .fops = &vmwgfx_driver_fops, 1494 .name = VMWGFX_DRIVER_NAME, 1495 .desc = VMWGFX_DRIVER_DESC, 1496 .date = VMWGFX_DRIVER_DATE, 1497 .major = VMWGFX_DRIVER_MAJOR, 1498 .minor = VMWGFX_DRIVER_MINOR, 1499 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1500 }; 1501 1502 static struct pci_driver vmw_pci_driver = { 1503 .name = VMWGFX_DRIVER_NAME, 1504 .id_table = vmw_pci_id_list, 1505 .probe = vmw_probe, 1506 .remove = vmw_remove, 1507 .driver = { 1508 .pm = &vmw_pm_ops 1509 } 1510 }; 1511 1512 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1513 { 1514 struct drm_device *dev; 1515 int ret; 1516 1517 ret = pci_enable_device(pdev); 1518 if (ret) 1519 return ret; 1520 1521 dev = drm_dev_alloc(&driver, &pdev->dev); 1522 if (IS_ERR(dev)) { 1523 ret = PTR_ERR(dev); 1524 goto err_pci_disable_device; 1525 } 1526 1527 dev->pdev = pdev; 1528 pci_set_drvdata(pdev, dev); 1529 1530 ret = vmw_driver_load(dev, ent->driver_data); 1531 if (ret) 1532 goto err_drm_dev_put; 1533 1534 ret = drm_dev_register(dev, ent->driver_data); 1535 if (ret) 1536 goto err_vmw_driver_unload; 1537 1538 return 0; 1539 1540 err_vmw_driver_unload: 1541 vmw_driver_unload(dev); 1542 err_drm_dev_put: 1543 drm_dev_put(dev); 1544 err_pci_disable_device: 1545 pci_disable_device(pdev); 1546 return ret; 1547 } 1548 1549 static int __init vmwgfx_init(void) 1550 { 1551 int ret; 1552 1553 if (vgacon_text_force()) 1554 return -EINVAL; 1555 1556 ret = pci_register_driver(&vmw_pci_driver); 1557 if (ret) 1558 DRM_ERROR("Failed initializing DRM.\n"); 1559 return ret; 1560 } 1561 1562 static void __exit vmwgfx_exit(void) 1563 { 1564 pci_unregister_driver(&vmw_pci_driver); 1565 } 1566 1567 module_init(vmwgfx_init); 1568 module_exit(vmwgfx_exit); 1569 1570 MODULE_AUTHOR("VMware Inc. and others"); 1571 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1572 MODULE_LICENSE("GPL and additional rights"); 1573 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1574 __stringify(VMWGFX_DRIVER_MINOR) "." 1575 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1576 "0"); 1577