1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2023 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29 #include "vmwgfx_drv.h" 30 31 #include "vmwgfx_bo.h" 32 #include "vmwgfx_binding.h" 33 #include "vmwgfx_devcaps.h" 34 #include "vmwgfx_mksstat.h" 35 #include "ttm_object.h" 36 37 #include <drm/drm_aperture.h> 38 #include <drm/drm_drv.h> 39 #include <drm/drm_fbdev_generic.h> 40 #include <drm/drm_gem_ttm_helper.h> 41 #include <drm/drm_ioctl.h> 42 #include <drm/drm_module.h> 43 #include <drm/drm_sysfs.h> 44 #include <drm/ttm/ttm_range_manager.h> 45 #include <drm/ttm/ttm_placement.h> 46 #include <generated/utsrelease.h> 47 48 #ifdef CONFIG_X86 49 #include <asm/hypervisor.h> 50 #endif 51 #include <linux/cc_platform.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/module.h> 54 #include <linux/pci.h> 55 #include <linux/version.h> 56 57 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 58 59 /* 60 * Fully encoded drm commands. Might move to vmw_drm.h 61 */ 62 63 #define DRM_IOCTL_VMW_GET_PARAM \ 64 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 65 struct drm_vmw_getparam_arg) 66 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 67 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 68 union drm_vmw_alloc_dmabuf_arg) 69 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 71 struct drm_vmw_unref_dmabuf_arg) 72 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 73 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 74 struct drm_vmw_cursor_bypass_arg) 75 76 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 78 struct drm_vmw_control_stream_arg) 79 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 80 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 81 struct drm_vmw_stream_arg) 82 #define DRM_IOCTL_VMW_UNREF_STREAM \ 83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 84 struct drm_vmw_stream_arg) 85 86 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 87 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 88 struct drm_vmw_context_arg) 89 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 90 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 91 struct drm_vmw_context_arg) 92 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 93 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 94 union drm_vmw_surface_create_arg) 95 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 96 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 97 struct drm_vmw_surface_arg) 98 #define DRM_IOCTL_VMW_REF_SURFACE \ 99 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 100 union drm_vmw_surface_reference_arg) 101 #define DRM_IOCTL_VMW_EXECBUF \ 102 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 103 struct drm_vmw_execbuf_arg) 104 #define DRM_IOCTL_VMW_GET_3D_CAP \ 105 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 106 struct drm_vmw_get_3d_cap_arg) 107 #define DRM_IOCTL_VMW_FENCE_WAIT \ 108 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 109 struct drm_vmw_fence_wait_arg) 110 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 111 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 112 struct drm_vmw_fence_signaled_arg) 113 #define DRM_IOCTL_VMW_FENCE_UNREF \ 114 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 115 struct drm_vmw_fence_arg) 116 #define DRM_IOCTL_VMW_FENCE_EVENT \ 117 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 118 struct drm_vmw_fence_event_arg) 119 #define DRM_IOCTL_VMW_PRESENT \ 120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 121 struct drm_vmw_present_arg) 122 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 123 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 124 struct drm_vmw_present_readback_arg) 125 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 126 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 127 struct drm_vmw_update_layout_arg) 128 #define DRM_IOCTL_VMW_CREATE_SHADER \ 129 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 130 struct drm_vmw_shader_create_arg) 131 #define DRM_IOCTL_VMW_UNREF_SHADER \ 132 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 133 struct drm_vmw_shader_arg) 134 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 135 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 136 union drm_vmw_gb_surface_create_arg) 137 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 138 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 139 union drm_vmw_gb_surface_reference_arg) 140 #define DRM_IOCTL_VMW_SYNCCPU \ 141 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 142 struct drm_vmw_synccpu_arg) 143 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 144 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 145 struct drm_vmw_context_arg) 146 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 147 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 148 union drm_vmw_gb_surface_create_ext_arg) 149 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 150 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 151 union drm_vmw_gb_surface_reference_ext_arg) 152 #define DRM_IOCTL_VMW_MSG \ 153 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 154 struct drm_vmw_msg_arg) 155 #define DRM_IOCTL_VMW_MKSSTAT_RESET \ 156 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) 157 #define DRM_IOCTL_VMW_MKSSTAT_ADD \ 158 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ 159 struct drm_vmw_mksstat_add_arg) 160 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ 161 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ 162 struct drm_vmw_mksstat_remove_arg) 163 164 /* 165 * Ioctl definitions. 166 */ 167 168 static const struct drm_ioctl_desc vmw_ioctls[] = { 169 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, 170 DRM_RENDER_ALLOW), 171 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, 172 DRM_RENDER_ALLOW), 173 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 174 DRM_RENDER_ALLOW), 175 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, 176 vmw_kms_cursor_bypass_ioctl, 177 DRM_MASTER), 178 179 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 180 DRM_MASTER), 181 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 182 DRM_MASTER), 183 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 184 DRM_MASTER), 185 186 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 187 DRM_RENDER_ALLOW), 188 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 189 DRM_RENDER_ALLOW), 190 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 191 DRM_RENDER_ALLOW), 192 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 193 DRM_RENDER_ALLOW), 194 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 195 DRM_RENDER_ALLOW), 196 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, 197 DRM_RENDER_ALLOW), 198 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 199 DRM_RENDER_ALLOW), 200 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, 201 vmw_fence_obj_signaled_ioctl, 202 DRM_RENDER_ALLOW), 203 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 204 DRM_RENDER_ALLOW), 205 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 206 DRM_RENDER_ALLOW), 207 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 208 DRM_RENDER_ALLOW), 209 210 /* these allow direct access to the framebuffers mark as master only */ 211 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, 212 DRM_MASTER | DRM_AUTH), 213 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, 214 vmw_present_readback_ioctl, 215 DRM_MASTER | DRM_AUTH), 216 /* 217 * The permissions of the below ioctl are overridden in 218 * vmw_generic_ioctl(). We require either 219 * DRM_MASTER or capable(CAP_SYS_ADMIN). 220 */ 221 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, 222 vmw_kms_update_layout_ioctl, 223 DRM_RENDER_ALLOW), 224 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, 225 vmw_shader_define_ioctl, 226 DRM_RENDER_ALLOW), 227 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, 228 vmw_shader_destroy_ioctl, 229 DRM_RENDER_ALLOW), 230 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, 231 vmw_gb_surface_define_ioctl, 232 DRM_RENDER_ALLOW), 233 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, 234 vmw_gb_surface_reference_ioctl, 235 DRM_RENDER_ALLOW), 236 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, 237 vmw_user_bo_synccpu_ioctl, 238 DRM_RENDER_ALLOW), 239 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, 240 vmw_extended_context_define_ioctl, 241 DRM_RENDER_ALLOW), 242 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, 243 vmw_gb_surface_define_ext_ioctl, 244 DRM_RENDER_ALLOW), 245 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, 246 vmw_gb_surface_reference_ext_ioctl, 247 DRM_RENDER_ALLOW), 248 DRM_IOCTL_DEF_DRV(VMW_MSG, 249 vmw_msg_ioctl, 250 DRM_RENDER_ALLOW), 251 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, 252 vmw_mksstat_reset_ioctl, 253 DRM_RENDER_ALLOW), 254 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, 255 vmw_mksstat_add_ioctl, 256 DRM_RENDER_ALLOW), 257 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, 258 vmw_mksstat_remove_ioctl, 259 DRM_RENDER_ALLOW), 260 }; 261 262 static const struct pci_device_id vmw_pci_id_list[] = { 263 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, 264 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, 265 { } 266 }; 267 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 268 269 static int vmw_restrict_iommu; 270 static int vmw_force_coherent; 271 static int vmw_restrict_dma_mask; 272 static int vmw_assume_16bpp; 273 274 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 275 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 276 void *ptr); 277 278 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 279 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 280 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 281 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 282 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 283 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 284 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 285 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 286 287 288 struct bitmap_name { 289 uint32 value; 290 const char *name; 291 }; 292 293 static const struct bitmap_name cap1_names[] = { 294 { SVGA_CAP_RECT_COPY, "rect copy" }, 295 { SVGA_CAP_CURSOR, "cursor" }, 296 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, 297 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, 298 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, 299 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, 300 { SVGA_CAP_3D, "3D" }, 301 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, 302 { SVGA_CAP_MULTIMON, "multimon" }, 303 { SVGA_CAP_PITCHLOCK, "pitchlock" }, 304 { SVGA_CAP_IRQMASK, "irq mask" }, 305 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, 306 { SVGA_CAP_GMR, "gmr" }, 307 { SVGA_CAP_TRACES, "traces" }, 308 { SVGA_CAP_GMR2, "gmr2" }, 309 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, 310 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, 311 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, 312 { SVGA_CAP_GBOBJECTS, "gbobject" }, 313 { SVGA_CAP_DX, "dx" }, 314 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, 315 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, 316 { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, 317 }; 318 319 320 static const struct bitmap_name cap2_names[] = { 321 { SVGA_CAP2_GROW_OTABLE, "grow otable" }, 322 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, 323 { SVGA_CAP2_DX2, "dx2" }, 324 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, 325 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, 326 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, 327 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, 328 { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, 329 { SVGA_CAP2_MSHINT, "mshint" }, 330 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, 331 { SVGA_CAP2_DX3, "dx3" }, 332 { SVGA_CAP2_FRAME_TYPE, "frame type" }, 333 { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, 334 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, 335 { SVGA_CAP2_EXTRA_REGS, "extra regs" }, 336 { SVGA_CAP2_LO_STAGING, "lo staging" }, 337 }; 338 339 static void vmw_print_bitmap(struct drm_device *drm, 340 const char *prefix, uint32_t bitmap, 341 const struct bitmap_name *bnames, 342 uint32_t num_names) 343 { 344 char buf[512]; 345 uint32_t i; 346 uint32_t offset = 0; 347 for (i = 0; i < num_names; ++i) { 348 if ((bitmap & bnames[i].value) != 0) { 349 offset += snprintf(buf + offset, 350 ARRAY_SIZE(buf) - offset, 351 "%s, ", bnames[i].name); 352 bitmap &= ~bnames[i].value; 353 } 354 } 355 356 drm_info(drm, "%s: %s\n", prefix, buf); 357 if (bitmap != 0) 358 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap); 359 } 360 361 362 static void vmw_print_sm_type(struct vmw_private *dev_priv) 363 { 364 static const char *names[] = { 365 [VMW_SM_LEGACY] = "Legacy", 366 [VMW_SM_4] = "SM4", 367 [VMW_SM_4_1] = "SM4_1", 368 [VMW_SM_5] = "SM_5", 369 [VMW_SM_5_1X] = "SM_5_1X", 370 [VMW_SM_MAX] = "Invalid" 371 }; 372 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); 373 drm_info(&dev_priv->drm, "Available shader model: %s.\n", 374 names[dev_priv->sm_type]); 375 } 376 377 /** 378 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 379 * 380 * @dev_priv: A device private structure. 381 * 382 * This function creates a small buffer object that holds the query 383 * result for dummy queries emitted as query barriers. 384 * The function will then map the first page and initialize a pending 385 * occlusion query result structure, Finally it will unmap the buffer. 386 * No interruptible waits are done within this function. 387 * 388 * Returns an error if bo creation or initialization fails. 389 */ 390 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 391 { 392 int ret; 393 struct vmw_bo *vbo; 394 struct ttm_bo_kmap_obj map; 395 volatile SVGA3dQueryResult *result; 396 bool dummy; 397 struct vmw_bo_params bo_params = { 398 .domain = VMW_BO_DOMAIN_SYS, 399 .busy_domain = VMW_BO_DOMAIN_SYS, 400 .bo_type = ttm_bo_type_kernel, 401 .size = PAGE_SIZE, 402 .pin = true 403 }; 404 405 /* 406 * Create the vbo as pinned, so that a tryreserve will 407 * immediately succeed. This is because we're the only 408 * user of the bo currently. 409 */ 410 ret = vmw_bo_create(dev_priv, &bo_params, &vbo); 411 if (unlikely(ret != 0)) 412 return ret; 413 414 ret = ttm_bo_reserve(&vbo->tbo, false, true, NULL); 415 BUG_ON(ret != 0); 416 vmw_bo_pin_reserved(vbo, true); 417 418 ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map); 419 if (likely(ret == 0)) { 420 result = ttm_kmap_obj_virtual(&map, &dummy); 421 result->totalSize = sizeof(*result); 422 result->state = SVGA3D_QUERYSTATE_PENDING; 423 result->result32 = 0xff; 424 ttm_bo_kunmap(&map); 425 } 426 vmw_bo_pin_reserved(vbo, false); 427 ttm_bo_unreserve(&vbo->tbo); 428 429 if (unlikely(ret != 0)) { 430 DRM_ERROR("Dummy query buffer map failed.\n"); 431 vmw_bo_unreference(&vbo); 432 } else 433 dev_priv->dummy_query_bo = vbo; 434 435 return ret; 436 } 437 438 static int vmw_device_init(struct vmw_private *dev_priv) 439 { 440 bool uses_fb_traces = false; 441 442 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 443 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 444 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 445 446 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | 447 SVGA_REG_ENABLE_HIDE); 448 449 uses_fb_traces = !vmw_cmd_supported(dev_priv) && 450 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; 451 452 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); 453 dev_priv->fifo = vmw_fifo_create(dev_priv); 454 if (IS_ERR(dev_priv->fifo)) { 455 int err = PTR_ERR(dev_priv->fifo); 456 dev_priv->fifo = NULL; 457 return err; 458 } else if (!dev_priv->fifo) { 459 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); 460 } 461 462 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); 463 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); 464 return 0; 465 } 466 467 static void vmw_device_fini(struct vmw_private *vmw) 468 { 469 /* 470 * Legacy sync 471 */ 472 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 473 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) 474 ; 475 476 vmw->last_read_seqno = vmw_fence_read(vmw); 477 478 vmw_write(vmw, SVGA_REG_CONFIG_DONE, 479 vmw->config_done_state); 480 vmw_write(vmw, SVGA_REG_ENABLE, 481 vmw->enable_state); 482 vmw_write(vmw, SVGA_REG_TRACES, 483 vmw->traces_state); 484 485 vmw_fifo_destroy(vmw); 486 } 487 488 /** 489 * vmw_request_device_late - Perform late device setup 490 * 491 * @dev_priv: Pointer to device private. 492 * 493 * This function performs setup of otables and enables large command 494 * buffer submission. These tasks are split out to a separate function 495 * because it reverts vmw_release_device_early and is intended to be used 496 * by an error path in the hibernation code. 497 */ 498 static int vmw_request_device_late(struct vmw_private *dev_priv) 499 { 500 int ret; 501 502 if (dev_priv->has_mob) { 503 ret = vmw_otables_setup(dev_priv); 504 if (unlikely(ret != 0)) { 505 DRM_ERROR("Unable to initialize " 506 "guest Memory OBjects.\n"); 507 return ret; 508 } 509 } 510 511 if (dev_priv->cman) { 512 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096); 513 if (ret) { 514 struct vmw_cmdbuf_man *man = dev_priv->cman; 515 516 dev_priv->cman = NULL; 517 vmw_cmdbuf_man_destroy(man); 518 } 519 } 520 521 return 0; 522 } 523 524 static int vmw_request_device(struct vmw_private *dev_priv) 525 { 526 int ret; 527 528 ret = vmw_device_init(dev_priv); 529 if (unlikely(ret != 0)) { 530 DRM_ERROR("Unable to initialize the device.\n"); 531 return ret; 532 } 533 vmw_fence_fifo_up(dev_priv->fman); 534 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 535 if (IS_ERR(dev_priv->cman)) { 536 dev_priv->cman = NULL; 537 dev_priv->sm_type = VMW_SM_LEGACY; 538 } 539 540 ret = vmw_request_device_late(dev_priv); 541 if (ret) 542 goto out_no_mob; 543 544 ret = vmw_dummy_query_bo_create(dev_priv); 545 if (unlikely(ret != 0)) 546 goto out_no_query_bo; 547 548 return 0; 549 550 out_no_query_bo: 551 if (dev_priv->cman) 552 vmw_cmdbuf_remove_pool(dev_priv->cman); 553 if (dev_priv->has_mob) { 554 struct ttm_resource_manager *man; 555 556 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 557 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 558 vmw_otables_takedown(dev_priv); 559 } 560 if (dev_priv->cman) 561 vmw_cmdbuf_man_destroy(dev_priv->cman); 562 out_no_mob: 563 vmw_fence_fifo_down(dev_priv->fman); 564 vmw_device_fini(dev_priv); 565 return ret; 566 } 567 568 /** 569 * vmw_release_device_early - Early part of fifo takedown. 570 * 571 * @dev_priv: Pointer to device private struct. 572 * 573 * This is the first part of command submission takedown, to be called before 574 * buffer management is taken down. 575 */ 576 static void vmw_release_device_early(struct vmw_private *dev_priv) 577 { 578 /* 579 * Previous destructions should've released 580 * the pinned bo. 581 */ 582 583 BUG_ON(dev_priv->pinned_bo != NULL); 584 585 vmw_bo_unreference(&dev_priv->dummy_query_bo); 586 if (dev_priv->cman) 587 vmw_cmdbuf_remove_pool(dev_priv->cman); 588 589 if (dev_priv->has_mob) { 590 struct ttm_resource_manager *man; 591 592 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 593 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 594 vmw_otables_takedown(dev_priv); 595 } 596 } 597 598 /** 599 * vmw_release_device_late - Late part of fifo takedown. 600 * 601 * @dev_priv: Pointer to device private struct. 602 * 603 * This is the last part of the command submission takedown, to be called when 604 * command submission is no longer needed. It may wait on pending fences. 605 */ 606 static void vmw_release_device_late(struct vmw_private *dev_priv) 607 { 608 vmw_fence_fifo_down(dev_priv->fman); 609 if (dev_priv->cman) 610 vmw_cmdbuf_man_destroy(dev_priv->cman); 611 612 vmw_device_fini(dev_priv); 613 } 614 615 /* 616 * Sets the initial_[width|height] fields on the given vmw_private. 617 * 618 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 619 * clamping the value to fb_max_[width|height] fields and the 620 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 621 * If the values appear to be invalid, set them to 622 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 623 */ 624 static void vmw_get_initial_size(struct vmw_private *dev_priv) 625 { 626 uint32_t width; 627 uint32_t height; 628 629 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 630 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 631 632 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH); 633 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT); 634 635 if (width > dev_priv->fb_max_width || 636 height > dev_priv->fb_max_height) { 637 638 /* 639 * This is a host error and shouldn't occur. 640 */ 641 642 width = VMWGFX_MIN_INITIAL_WIDTH; 643 height = VMWGFX_MIN_INITIAL_HEIGHT; 644 } 645 646 dev_priv->initial_width = width; 647 dev_priv->initial_height = height; 648 } 649 650 /** 651 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 652 * system. 653 * 654 * @dev_priv: Pointer to a struct vmw_private 655 * 656 * This functions tries to determine what actions need to be taken by the 657 * driver to make system pages visible to the device. 658 * If this function decides that DMA is not possible, it returns -EINVAL. 659 * The driver may then try to disable features of the device that require 660 * DMA. 661 */ 662 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 663 { 664 static const char *names[vmw_dma_map_max] = { 665 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 666 [vmw_dma_map_populate] = "Caching DMA mappings.", 667 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 668 669 /* 670 * When running with SEV we always want dma mappings, because 671 * otherwise ttm tt pool pages will bounce through swiotlb running 672 * out of available space. 673 */ 674 if (vmw_force_coherent || cc_platform_has(CC_ATTR_MEM_ENCRYPT)) 675 dev_priv->map_mode = vmw_dma_alloc_coherent; 676 else if (vmw_restrict_iommu) 677 dev_priv->map_mode = vmw_dma_map_bind; 678 else 679 dev_priv->map_mode = vmw_dma_map_populate; 680 681 drm_info(&dev_priv->drm, 682 "DMA map mode: %s\n", names[dev_priv->map_mode]); 683 return 0; 684 } 685 686 /** 687 * vmw_dma_masks - set required page- and dma masks 688 * 689 * @dev_priv: Pointer to struct drm-device 690 * 691 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 692 * restriction also for 64-bit systems. 693 */ 694 static int vmw_dma_masks(struct vmw_private *dev_priv) 695 { 696 struct drm_device *dev = &dev_priv->drm; 697 int ret = 0; 698 699 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 700 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { 701 drm_info(&dev_priv->drm, 702 "Restricting DMA addresses to 44 bits.\n"); 703 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 704 } 705 706 return ret; 707 } 708 709 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 710 { 711 int ret; 712 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 713 dev_priv->vram_size >> PAGE_SHIFT); 714 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 715 return ret; 716 } 717 718 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 719 { 720 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 721 } 722 723 static int vmw_setup_pci_resources(struct vmw_private *dev, 724 u32 pci_id) 725 { 726 resource_size_t rmmio_start; 727 resource_size_t rmmio_size; 728 resource_size_t fifo_start; 729 resource_size_t fifo_size; 730 int ret; 731 struct pci_dev *pdev = to_pci_dev(dev->drm.dev); 732 733 pci_set_master(pdev); 734 735 ret = pci_request_regions(pdev, "vmwgfx probe"); 736 if (ret) 737 return ret; 738 739 dev->pci_id = pci_id; 740 if (pci_id == VMWGFX_PCI_ID_SVGA3) { 741 rmmio_start = pci_resource_start(pdev, 0); 742 rmmio_size = pci_resource_len(pdev, 0); 743 dev->vram_start = pci_resource_start(pdev, 2); 744 dev->vram_size = pci_resource_len(pdev, 2); 745 746 drm_info(&dev->drm, 747 "Register MMIO at 0x%pa size is %llu kiB\n", 748 &rmmio_start, (uint64_t)rmmio_size / 1024); 749 dev->rmmio = devm_ioremap(dev->drm.dev, 750 rmmio_start, 751 rmmio_size); 752 if (!dev->rmmio) { 753 drm_err(&dev->drm, 754 "Failed mapping registers mmio memory.\n"); 755 pci_release_regions(pdev); 756 return -ENOMEM; 757 } 758 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { 759 dev->io_start = pci_resource_start(pdev, 0); 760 dev->vram_start = pci_resource_start(pdev, 1); 761 dev->vram_size = pci_resource_len(pdev, 1); 762 fifo_start = pci_resource_start(pdev, 2); 763 fifo_size = pci_resource_len(pdev, 2); 764 765 drm_info(&dev->drm, 766 "FIFO at %pa size is %llu kiB\n", 767 &fifo_start, (uint64_t)fifo_size / 1024); 768 dev->fifo_mem = devm_memremap(dev->drm.dev, 769 fifo_start, 770 fifo_size, 771 MEMREMAP_WB); 772 773 if (IS_ERR(dev->fifo_mem)) { 774 drm_err(&dev->drm, 775 "Failed mapping FIFO memory.\n"); 776 pci_release_regions(pdev); 777 return PTR_ERR(dev->fifo_mem); 778 } 779 } else { 780 pci_release_regions(pdev); 781 return -EINVAL; 782 } 783 784 /* 785 * This is approximate size of the vram, the exact size will only 786 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource 787 * size will be equal to or bigger than the size reported by 788 * SVGA_REG_VRAM_SIZE. 789 */ 790 drm_info(&dev->drm, 791 "VRAM at %pa size is %llu kiB\n", 792 &dev->vram_start, (uint64_t)dev->vram_size / 1024); 793 794 return 0; 795 } 796 797 static int vmw_detect_version(struct vmw_private *dev) 798 { 799 uint32_t svga_id; 800 801 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? 802 SVGA_ID_3 : SVGA_ID_2); 803 svga_id = vmw_read(dev, SVGA_REG_ID); 804 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { 805 drm_err(&dev->drm, 806 "Unsupported SVGA ID 0x%x on chipset 0x%x\n", 807 svga_id, dev->pci_id); 808 return -ENOSYS; 809 } 810 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); 811 drm_info(&dev->drm, 812 "Running on SVGA version %d.\n", (svga_id & 0xff)); 813 return 0; 814 } 815 816 static void vmw_write_driver_id(struct vmw_private *dev) 817 { 818 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) { 819 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 820 SVGA_REG_GUEST_DRIVER_ID_LINUX); 821 822 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1, 823 LINUX_VERSION_MAJOR << 24 | 824 LINUX_VERSION_PATCHLEVEL << 16 | 825 LINUX_VERSION_SUBLEVEL); 826 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2, 827 VMWGFX_DRIVER_MAJOR << 24 | 828 VMWGFX_DRIVER_MINOR << 16 | 829 VMWGFX_DRIVER_PATCHLEVEL); 830 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0); 831 832 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 833 SVGA_REG_GUEST_DRIVER_ID_SUBMIT); 834 } 835 } 836 837 static void vmw_sw_context_init(struct vmw_private *dev_priv) 838 { 839 struct vmw_sw_context *sw_context = &dev_priv->ctx; 840 841 hash_init(sw_context->res_ht); 842 } 843 844 static void vmw_sw_context_fini(struct vmw_private *dev_priv) 845 { 846 struct vmw_sw_context *sw_context = &dev_priv->ctx; 847 848 vfree(sw_context->cmd_bounce); 849 if (sw_context->staged_bindings) 850 vmw_binding_state_free(sw_context->staged_bindings); 851 } 852 853 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 854 { 855 int ret; 856 enum vmw_res_type i; 857 bool refuse_dma = false; 858 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 859 860 dev_priv->drm.dev_private = dev_priv; 861 862 vmw_sw_context_init(dev_priv); 863 864 mutex_init(&dev_priv->cmdbuf_mutex); 865 mutex_init(&dev_priv->binding_mutex); 866 spin_lock_init(&dev_priv->resource_lock); 867 spin_lock_init(&dev_priv->hw_lock); 868 spin_lock_init(&dev_priv->waiter_lock); 869 spin_lock_init(&dev_priv->cursor_lock); 870 871 ret = vmw_setup_pci_resources(dev_priv, pci_id); 872 if (ret) 873 return ret; 874 ret = vmw_detect_version(dev_priv); 875 if (ret) 876 goto out_no_pci_or_version; 877 878 879 for (i = vmw_res_context; i < vmw_res_max; ++i) { 880 idr_init_base(&dev_priv->res_idr[i], 1); 881 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 882 } 883 884 init_waitqueue_head(&dev_priv->fence_queue); 885 init_waitqueue_head(&dev_priv->fifo_queue); 886 dev_priv->fence_queue_waiters = 0; 887 dev_priv->fifo_queue_waiters = 0; 888 889 dev_priv->used_memory_size = 0; 890 891 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 892 893 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 894 vmw_print_bitmap(&dev_priv->drm, "Capabilities", 895 dev_priv->capabilities, 896 cap1_names, ARRAY_SIZE(cap1_names)); 897 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 898 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 899 vmw_print_bitmap(&dev_priv->drm, "Capabilities2", 900 dev_priv->capabilities2, 901 cap2_names, ARRAY_SIZE(cap2_names)); 902 } 903 904 if (!vmwgfx_supported(dev_priv)) { 905 vmw_disable_backdoor(); 906 drm_err_once(&dev_priv->drm, 907 "vmwgfx seems to be running on an unsupported hypervisor."); 908 drm_err_once(&dev_priv->drm, 909 "This configuration is likely broken."); 910 drm_err_once(&dev_priv->drm, 911 "Please switch to a supported graphics device to avoid problems."); 912 } 913 914 ret = vmw_dma_select_mode(dev_priv); 915 if (unlikely(ret != 0)) { 916 drm_info(&dev_priv->drm, 917 "Restricting capabilities since DMA not available.\n"); 918 refuse_dma = true; 919 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 920 drm_info(&dev_priv->drm, 921 "Disabling 3D acceleration.\n"); 922 } 923 924 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 925 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 926 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 927 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 928 929 vmw_get_initial_size(dev_priv); 930 931 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 932 dev_priv->max_gmr_ids = 933 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 934 dev_priv->max_gmr_pages = 935 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 936 dev_priv->memory_size = 937 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 938 dev_priv->memory_size -= dev_priv->vram_size; 939 } else { 940 /* 941 * An arbitrary limit of 512MiB on surface 942 * memory. But all HWV8 hardware supports GMR2. 943 */ 944 dev_priv->memory_size = 512*1024*1024; 945 } 946 dev_priv->max_mob_pages = 0; 947 dev_priv->max_mob_size = 0; 948 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 949 uint64_t mem_size; 950 951 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 952 mem_size = vmw_read(dev_priv, 953 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 954 else 955 mem_size = 956 vmw_read(dev_priv, 957 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 958 959 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 960 dev_priv->max_primary_mem = 961 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM); 962 dev_priv->max_mob_size = 963 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 964 dev_priv->stdu_max_width = 965 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 966 dev_priv->stdu_max_height = 967 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 968 969 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 970 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 971 dev_priv->texture_max_width = vmw_read(dev_priv, 972 SVGA_REG_DEV_CAP); 973 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 974 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 975 dev_priv->texture_max_height = vmw_read(dev_priv, 976 SVGA_REG_DEV_CAP); 977 } else { 978 dev_priv->texture_max_width = 8192; 979 dev_priv->texture_max_height = 8192; 980 dev_priv->max_primary_mem = dev_priv->vram_size; 981 } 982 drm_info(&dev_priv->drm, 983 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n", 984 (u64)dev_priv->vram_size / 1024, 985 (u64)dev_priv->fifo_mem_size / 1024, 986 dev_priv->memory_size / 1024); 987 988 drm_info(&dev_priv->drm, 989 "MOB limits: max mob size = %u kB, max mob pages = %u\n", 990 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); 991 992 ret = vmw_dma_masks(dev_priv); 993 if (unlikely(ret != 0)) 994 goto out_err0; 995 996 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX); 997 998 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 999 drm_info(&dev_priv->drm, 1000 "Max GMR ids is %u\n", 1001 (unsigned)dev_priv->max_gmr_ids); 1002 drm_info(&dev_priv->drm, 1003 "Max number of GMR pages is %u\n", 1004 (unsigned)dev_priv->max_gmr_pages); 1005 } 1006 drm_info(&dev_priv->drm, 1007 "Maximum display memory size is %llu kiB\n", 1008 (uint64_t)dev_priv->max_primary_mem / 1024); 1009 1010 /* Need mmio memory to check for fifo pitchlock cap. */ 1011 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 1012 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 1013 !vmw_fifo_have_pitchlock(dev_priv)) { 1014 ret = -ENOSYS; 1015 DRM_ERROR("Hardware has no pitchlock\n"); 1016 goto out_err0; 1017 } 1018 1019 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops); 1020 1021 if (unlikely(dev_priv->tdev == NULL)) { 1022 drm_err(&dev_priv->drm, 1023 "Unable to initialize TTM object management.\n"); 1024 ret = -ENOMEM; 1025 goto out_err0; 1026 } 1027 1028 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 1029 ret = vmw_irq_install(dev_priv); 1030 if (ret != 0) { 1031 drm_err(&dev_priv->drm, 1032 "Failed installing irq: %d\n", ret); 1033 goto out_no_irq; 1034 } 1035 } 1036 1037 dev_priv->fman = vmw_fence_manager_init(dev_priv); 1038 if (unlikely(dev_priv->fman == NULL)) { 1039 ret = -ENOMEM; 1040 goto out_no_fman; 1041 } 1042 1043 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver, 1044 dev_priv->drm.dev, 1045 dev_priv->drm.anon_inode->i_mapping, 1046 dev_priv->drm.vma_offset_manager, 1047 dev_priv->map_mode == vmw_dma_alloc_coherent, 1048 false); 1049 if (unlikely(ret != 0)) { 1050 drm_err(&dev_priv->drm, 1051 "Failed initializing TTM buffer object driver.\n"); 1052 goto out_no_bdev; 1053 } 1054 1055 /* 1056 * Enable VRAM, but initially don't use it until SVGA is enabled and 1057 * unhidden. 1058 */ 1059 1060 ret = vmw_vram_manager_init(dev_priv); 1061 if (unlikely(ret != 0)) { 1062 drm_err(&dev_priv->drm, 1063 "Failed initializing memory manager for VRAM.\n"); 1064 goto out_no_vram; 1065 } 1066 1067 ret = vmw_devcaps_create(dev_priv); 1068 if (unlikely(ret != 0)) { 1069 drm_err(&dev_priv->drm, 1070 "Failed initializing device caps.\n"); 1071 goto out_no_vram; 1072 } 1073 1074 /* 1075 * "Guest Memory Regions" is an aperture like feature with 1076 * one slot per bo. There is an upper limit of the number of 1077 * slots as well as the bo size. 1078 */ 1079 dev_priv->has_gmr = true; 1080 /* TODO: This is most likely not correct */ 1081 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 1082 refuse_dma || 1083 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 1084 drm_info(&dev_priv->drm, 1085 "No GMR memory available. " 1086 "Graphics memory resources are very limited.\n"); 1087 dev_priv->has_gmr = false; 1088 } 1089 1090 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 1091 dev_priv->has_mob = true; 1092 1093 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 1094 drm_info(&dev_priv->drm, 1095 "No MOB memory available. " 1096 "3D will be disabled.\n"); 1097 dev_priv->has_mob = false; 1098 } 1099 if (vmw_sys_man_init(dev_priv) != 0) { 1100 drm_info(&dev_priv->drm, 1101 "No MOB page table memory available. " 1102 "3D will be disabled.\n"); 1103 dev_priv->has_mob = false; 1104 } 1105 } 1106 1107 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 1108 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) 1109 dev_priv->sm_type = VMW_SM_4; 1110 } 1111 1112 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 1113 if (has_sm4_context(dev_priv) && 1114 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 1115 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41)) 1116 dev_priv->sm_type = VMW_SM_4_1; 1117 if (has_sm4_1_context(dev_priv) && 1118 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 1119 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) { 1120 dev_priv->sm_type = VMW_SM_5; 1121 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43)) 1122 dev_priv->sm_type = VMW_SM_5_1X; 1123 } 1124 } 1125 } 1126 1127 ret = vmw_kms_init(dev_priv); 1128 if (unlikely(ret != 0)) 1129 goto out_no_kms; 1130 vmw_overlay_init(dev_priv); 1131 1132 ret = vmw_request_device(dev_priv); 1133 if (ret) 1134 goto out_no_fifo; 1135 1136 vmw_print_sm_type(dev_priv); 1137 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)", 1138 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 1139 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); 1140 vmw_write_driver_id(dev_priv); 1141 1142 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 1143 register_pm_notifier(&dev_priv->pm_nb); 1144 1145 return 0; 1146 1147 out_no_fifo: 1148 vmw_overlay_close(dev_priv); 1149 vmw_kms_close(dev_priv); 1150 out_no_kms: 1151 if (dev_priv->has_mob) { 1152 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1153 vmw_sys_man_fini(dev_priv); 1154 } 1155 if (dev_priv->has_gmr) 1156 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1157 vmw_devcaps_destroy(dev_priv); 1158 vmw_vram_manager_fini(dev_priv); 1159 out_no_vram: 1160 ttm_device_fini(&dev_priv->bdev); 1161 out_no_bdev: 1162 vmw_fence_manager_takedown(dev_priv->fman); 1163 out_no_fman: 1164 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1165 vmw_irq_uninstall(&dev_priv->drm); 1166 out_no_irq: 1167 ttm_object_device_release(&dev_priv->tdev); 1168 out_err0: 1169 for (i = vmw_res_context; i < vmw_res_max; ++i) 1170 idr_destroy(&dev_priv->res_idr[i]); 1171 1172 if (dev_priv->ctx.staged_bindings) 1173 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1174 out_no_pci_or_version: 1175 pci_release_regions(pdev); 1176 return ret; 1177 } 1178 1179 static void vmw_driver_unload(struct drm_device *dev) 1180 { 1181 struct vmw_private *dev_priv = vmw_priv(dev); 1182 struct pci_dev *pdev = to_pci_dev(dev->dev); 1183 enum vmw_res_type i; 1184 1185 unregister_pm_notifier(&dev_priv->pm_nb); 1186 1187 vmw_sw_context_fini(dev_priv); 1188 vmw_fifo_resource_dec(dev_priv); 1189 1190 vmw_svga_disable(dev_priv); 1191 1192 vmw_kms_close(dev_priv); 1193 vmw_overlay_close(dev_priv); 1194 1195 if (dev_priv->has_gmr) 1196 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1197 1198 vmw_release_device_early(dev_priv); 1199 if (dev_priv->has_mob) { 1200 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1201 vmw_sys_man_fini(dev_priv); 1202 } 1203 vmw_devcaps_destroy(dev_priv); 1204 vmw_vram_manager_fini(dev_priv); 1205 ttm_device_fini(&dev_priv->bdev); 1206 vmw_release_device_late(dev_priv); 1207 vmw_fence_manager_takedown(dev_priv->fman); 1208 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1209 vmw_irq_uninstall(&dev_priv->drm); 1210 1211 ttm_object_device_release(&dev_priv->tdev); 1212 1213 for (i = vmw_res_context; i < vmw_res_max; ++i) 1214 idr_destroy(&dev_priv->res_idr[i]); 1215 1216 vmw_mksstat_remove_all(dev_priv); 1217 1218 pci_release_regions(pdev); 1219 } 1220 1221 static void vmw_postclose(struct drm_device *dev, 1222 struct drm_file *file_priv) 1223 { 1224 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1225 1226 ttm_object_file_release(&vmw_fp->tfile); 1227 kfree(vmw_fp); 1228 } 1229 1230 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1231 { 1232 struct vmw_private *dev_priv = vmw_priv(dev); 1233 struct vmw_fpriv *vmw_fp; 1234 int ret = -ENOMEM; 1235 1236 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1237 if (unlikely(!vmw_fp)) 1238 return ret; 1239 1240 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev); 1241 if (unlikely(vmw_fp->tfile == NULL)) 1242 goto out_no_tfile; 1243 1244 file_priv->driver_priv = vmw_fp; 1245 1246 return 0; 1247 1248 out_no_tfile: 1249 kfree(vmw_fp); 1250 return ret; 1251 } 1252 1253 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1254 unsigned long arg, 1255 long (*ioctl_func)(struct file *, unsigned int, 1256 unsigned long)) 1257 { 1258 struct drm_file *file_priv = filp->private_data; 1259 struct drm_device *dev = file_priv->minor->dev; 1260 unsigned int nr = DRM_IOCTL_NR(cmd); 1261 unsigned int flags; 1262 1263 /* 1264 * Do extra checking on driver private ioctls. 1265 */ 1266 1267 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1268 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1269 const struct drm_ioctl_desc *ioctl = 1270 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1271 1272 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1273 return ioctl_func(filp, cmd, arg); 1274 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1275 if (!drm_is_current_master(file_priv) && 1276 !capable(CAP_SYS_ADMIN)) 1277 return -EACCES; 1278 } 1279 1280 if (unlikely(ioctl->cmd != cmd)) 1281 goto out_io_encoding; 1282 1283 flags = ioctl->flags; 1284 } else if (!drm_ioctl_flags(nr, &flags)) 1285 return -EINVAL; 1286 1287 return ioctl_func(filp, cmd, arg); 1288 1289 out_io_encoding: 1290 DRM_ERROR("Invalid command format, ioctl %d\n", 1291 nr - DRM_COMMAND_BASE); 1292 1293 return -EINVAL; 1294 } 1295 1296 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1297 unsigned long arg) 1298 { 1299 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1300 } 1301 1302 #ifdef CONFIG_COMPAT 1303 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1304 unsigned long arg) 1305 { 1306 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1307 } 1308 #endif 1309 1310 static void vmw_master_set(struct drm_device *dev, 1311 struct drm_file *file_priv, 1312 bool from_open) 1313 { 1314 /* 1315 * Inform a new master that the layout may have changed while 1316 * it was gone. 1317 */ 1318 if (!from_open) 1319 drm_sysfs_hotplug_event(dev); 1320 } 1321 1322 static void vmw_master_drop(struct drm_device *dev, 1323 struct drm_file *file_priv) 1324 { 1325 struct vmw_private *dev_priv = vmw_priv(dev); 1326 1327 vmw_kms_legacy_hotspot_clear(dev_priv); 1328 } 1329 1330 bool vmwgfx_supported(struct vmw_private *vmw) 1331 { 1332 #if defined(CONFIG_X86) 1333 return hypervisor_is_type(X86_HYPER_VMWARE); 1334 #elif defined(CONFIG_ARM64) 1335 /* 1336 * On aarch64 only svga3 is supported 1337 */ 1338 return vmw->pci_id == VMWGFX_PCI_ID_SVGA3; 1339 #else 1340 drm_warn_once(&vmw->drm, 1341 "vmwgfx is running on an unknown architecture."); 1342 return false; 1343 #endif 1344 } 1345 1346 /** 1347 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1348 * 1349 * @dev_priv: Pointer to device private struct. 1350 * Needs the reservation sem to be held in non-exclusive mode. 1351 */ 1352 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1353 { 1354 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1355 1356 if (!ttm_resource_manager_used(man)) { 1357 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE); 1358 ttm_resource_manager_set_used(man, true); 1359 } 1360 } 1361 1362 /** 1363 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1364 * 1365 * @dev_priv: Pointer to device private struct. 1366 */ 1367 void vmw_svga_enable(struct vmw_private *dev_priv) 1368 { 1369 __vmw_svga_enable(dev_priv); 1370 } 1371 1372 /** 1373 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1374 * 1375 * @dev_priv: Pointer to device private struct. 1376 * Needs the reservation sem to be held in exclusive mode. 1377 * Will not empty VRAM. VRAM must be emptied by caller. 1378 */ 1379 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1380 { 1381 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1382 1383 if (ttm_resource_manager_used(man)) { 1384 ttm_resource_manager_set_used(man, false); 1385 vmw_write(dev_priv, SVGA_REG_ENABLE, 1386 SVGA_REG_ENABLE_HIDE | 1387 SVGA_REG_ENABLE_ENABLE); 1388 } 1389 } 1390 1391 /** 1392 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1393 * running. 1394 * 1395 * @dev_priv: Pointer to device private struct. 1396 * Will empty VRAM. 1397 */ 1398 void vmw_svga_disable(struct vmw_private *dev_priv) 1399 { 1400 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1401 /* 1402 * Disabling SVGA will turn off device modesetting capabilities, so 1403 * notify KMS about that so that it doesn't cache atomic state that 1404 * isn't valid anymore, for example crtcs turned on. 1405 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1406 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1407 * end up with lock order reversal. Thus, a master may actually perform 1408 * a new modeset just after we call vmw_kms_lost_device() and race with 1409 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1410 * to be inconsistent with the device, causing modesetting problems. 1411 * 1412 */ 1413 vmw_kms_lost_device(&dev_priv->drm); 1414 if (ttm_resource_manager_used(man)) { 1415 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1416 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1417 ttm_resource_manager_set_used(man, false); 1418 vmw_write(dev_priv, SVGA_REG_ENABLE, 1419 SVGA_REG_ENABLE_HIDE | 1420 SVGA_REG_ENABLE_ENABLE); 1421 } 1422 } 1423 1424 static void vmw_remove(struct pci_dev *pdev) 1425 { 1426 struct drm_device *dev = pci_get_drvdata(pdev); 1427 1428 drm_dev_unregister(dev); 1429 vmw_driver_unload(dev); 1430 } 1431 1432 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw) 1433 { 1434 struct drm_minor *minor = vmw->drm.primary; 1435 struct dentry *root = minor->debugfs_root; 1436 1437 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM), 1438 root, "system_ttm"); 1439 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM), 1440 root, "vram_ttm"); 1441 if (vmw->has_gmr) 1442 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR), 1443 root, "gmr_ttm"); 1444 if (vmw->has_mob) { 1445 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB), 1446 root, "mob_ttm"); 1447 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM), 1448 root, "system_mob_ttm"); 1449 } 1450 } 1451 1452 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1453 void *ptr) 1454 { 1455 struct vmw_private *dev_priv = 1456 container_of(nb, struct vmw_private, pm_nb); 1457 1458 switch (val) { 1459 case PM_HIBERNATION_PREPARE: 1460 /* 1461 * Take the reservation sem in write mode, which will make sure 1462 * there are no other processes holding a buffer object 1463 * reservation, meaning we should be able to evict all buffer 1464 * objects if needed. 1465 * Once user-space processes have been frozen, we can release 1466 * the lock again. 1467 */ 1468 dev_priv->suspend_locked = true; 1469 break; 1470 case PM_POST_HIBERNATION: 1471 case PM_POST_RESTORE: 1472 if (READ_ONCE(dev_priv->suspend_locked)) { 1473 dev_priv->suspend_locked = false; 1474 } 1475 break; 1476 default: 1477 break; 1478 } 1479 return 0; 1480 } 1481 1482 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1483 { 1484 struct drm_device *dev = pci_get_drvdata(pdev); 1485 struct vmw_private *dev_priv = vmw_priv(dev); 1486 1487 if (dev_priv->refuse_hibernation) 1488 return -EBUSY; 1489 1490 pci_save_state(pdev); 1491 pci_disable_device(pdev); 1492 pci_set_power_state(pdev, PCI_D3hot); 1493 return 0; 1494 } 1495 1496 static int vmw_pci_resume(struct pci_dev *pdev) 1497 { 1498 pci_set_power_state(pdev, PCI_D0); 1499 pci_restore_state(pdev); 1500 return pci_enable_device(pdev); 1501 } 1502 1503 static int vmw_pm_suspend(struct device *kdev) 1504 { 1505 struct pci_dev *pdev = to_pci_dev(kdev); 1506 struct pm_message dummy; 1507 1508 dummy.event = 0; 1509 1510 return vmw_pci_suspend(pdev, dummy); 1511 } 1512 1513 static int vmw_pm_resume(struct device *kdev) 1514 { 1515 struct pci_dev *pdev = to_pci_dev(kdev); 1516 1517 return vmw_pci_resume(pdev); 1518 } 1519 1520 static int vmw_pm_freeze(struct device *kdev) 1521 { 1522 struct pci_dev *pdev = to_pci_dev(kdev); 1523 struct drm_device *dev = pci_get_drvdata(pdev); 1524 struct vmw_private *dev_priv = vmw_priv(dev); 1525 struct ttm_operation_ctx ctx = { 1526 .interruptible = false, 1527 .no_wait_gpu = false 1528 }; 1529 int ret; 1530 1531 /* 1532 * No user-space processes should be running now. 1533 */ 1534 ret = vmw_kms_suspend(&dev_priv->drm); 1535 if (ret) { 1536 DRM_ERROR("Failed to freeze modesetting.\n"); 1537 return ret; 1538 } 1539 1540 vmw_execbuf_release_pinned_bo(dev_priv); 1541 vmw_resource_evict_all(dev_priv); 1542 vmw_release_device_early(dev_priv); 1543 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0); 1544 vmw_fifo_resource_dec(dev_priv); 1545 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1546 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1547 vmw_fifo_resource_inc(dev_priv); 1548 WARN_ON(vmw_request_device_late(dev_priv)); 1549 dev_priv->suspend_locked = false; 1550 if (dev_priv->suspend_state) 1551 vmw_kms_resume(dev); 1552 return -EBUSY; 1553 } 1554 1555 vmw_fence_fifo_down(dev_priv->fman); 1556 __vmw_svga_disable(dev_priv); 1557 1558 vmw_release_device_late(dev_priv); 1559 return 0; 1560 } 1561 1562 static int vmw_pm_restore(struct device *kdev) 1563 { 1564 struct pci_dev *pdev = to_pci_dev(kdev); 1565 struct drm_device *dev = pci_get_drvdata(pdev); 1566 struct vmw_private *dev_priv = vmw_priv(dev); 1567 int ret; 1568 1569 vmw_detect_version(dev_priv); 1570 1571 vmw_fifo_resource_inc(dev_priv); 1572 1573 ret = vmw_request_device(dev_priv); 1574 if (ret) 1575 return ret; 1576 1577 __vmw_svga_enable(dev_priv); 1578 1579 vmw_fence_fifo_up(dev_priv->fman); 1580 dev_priv->suspend_locked = false; 1581 if (dev_priv->suspend_state) 1582 vmw_kms_resume(&dev_priv->drm); 1583 1584 return 0; 1585 } 1586 1587 static const struct dev_pm_ops vmw_pm_ops = { 1588 .freeze = vmw_pm_freeze, 1589 .thaw = vmw_pm_restore, 1590 .restore = vmw_pm_restore, 1591 .suspend = vmw_pm_suspend, 1592 .resume = vmw_pm_resume, 1593 }; 1594 1595 static const struct file_operations vmwgfx_driver_fops = { 1596 .owner = THIS_MODULE, 1597 .open = drm_open, 1598 .release = drm_release, 1599 .unlocked_ioctl = vmw_unlocked_ioctl, 1600 .mmap = drm_gem_mmap, 1601 .poll = drm_poll, 1602 .read = drm_read, 1603 #if defined(CONFIG_COMPAT) 1604 .compat_ioctl = vmw_compat_ioctl, 1605 #endif 1606 .llseek = noop_llseek, 1607 }; 1608 1609 static const struct drm_driver driver = { 1610 .driver_features = 1611 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM | DRIVER_CURSOR_HOTSPOT, 1612 .ioctls = vmw_ioctls, 1613 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1614 .master_set = vmw_master_set, 1615 .master_drop = vmw_master_drop, 1616 .open = vmw_driver_open, 1617 .postclose = vmw_postclose, 1618 1619 .dumb_create = vmw_dumb_create, 1620 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1621 1622 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1623 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1624 .gem_prime_import_sg_table = vmw_prime_import_sg_table, 1625 1626 .fops = &vmwgfx_driver_fops, 1627 .name = VMWGFX_DRIVER_NAME, 1628 .desc = VMWGFX_DRIVER_DESC, 1629 .date = VMWGFX_DRIVER_DATE, 1630 .major = VMWGFX_DRIVER_MAJOR, 1631 .minor = VMWGFX_DRIVER_MINOR, 1632 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1633 }; 1634 1635 static struct pci_driver vmw_pci_driver = { 1636 .name = VMWGFX_DRIVER_NAME, 1637 .id_table = vmw_pci_id_list, 1638 .probe = vmw_probe, 1639 .remove = vmw_remove, 1640 .driver = { 1641 .pm = &vmw_pm_ops 1642 } 1643 }; 1644 1645 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1646 { 1647 struct vmw_private *vmw; 1648 int ret; 1649 1650 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver); 1651 if (ret) 1652 goto out_error; 1653 1654 ret = pcim_enable_device(pdev); 1655 if (ret) 1656 goto out_error; 1657 1658 vmw = devm_drm_dev_alloc(&pdev->dev, &driver, 1659 struct vmw_private, drm); 1660 if (IS_ERR(vmw)) { 1661 ret = PTR_ERR(vmw); 1662 goto out_error; 1663 } 1664 1665 pci_set_drvdata(pdev, &vmw->drm); 1666 1667 ret = vmw_driver_load(vmw, ent->device); 1668 if (ret) 1669 goto out_error; 1670 1671 ret = drm_dev_register(&vmw->drm, 0); 1672 if (ret) 1673 goto out_unload; 1674 1675 vmw_fifo_resource_inc(vmw); 1676 vmw_svga_enable(vmw); 1677 drm_fbdev_generic_setup(&vmw->drm, 0); 1678 1679 vmw_debugfs_gem_init(vmw); 1680 vmw_debugfs_resource_managers_init(vmw); 1681 1682 return 0; 1683 out_unload: 1684 vmw_driver_unload(&vmw->drm); 1685 out_error: 1686 return ret; 1687 } 1688 1689 drm_module_pci_driver(vmw_pci_driver); 1690 1691 MODULE_AUTHOR("VMware Inc. and others"); 1692 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1693 MODULE_LICENSE("GPL and additional rights"); 1694 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1695 __stringify(VMWGFX_DRIVER_MINOR) "." 1696 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1697 "0"); 1698