1 /************************************************************************** 2 * 3 * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 #include <linux/module.h> 28 29 #include <drm/drmP.h> 30 #include "vmwgfx_drv.h" 31 #include <drm/ttm/ttm_placement.h> 32 #include <drm/ttm/ttm_bo_driver.h> 33 #include <drm/ttm/ttm_object.h> 34 #include <drm/ttm/ttm_module.h> 35 #include <linux/dma_remapping.h> 36 37 #define VMWGFX_DRIVER_NAME "vmwgfx" 38 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 39 #define VMWGFX_CHIP_SVGAII 0 40 #define VMW_FB_RESERVATION 0 41 42 #define VMW_MIN_INITIAL_WIDTH 800 43 #define VMW_MIN_INITIAL_HEIGHT 600 44 45 46 /** 47 * Fully encoded drm commands. Might move to vmw_drm.h 48 */ 49 50 #define DRM_IOCTL_VMW_GET_PARAM \ 51 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 52 struct drm_vmw_getparam_arg) 53 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 54 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 55 union drm_vmw_alloc_dmabuf_arg) 56 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 57 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 58 struct drm_vmw_unref_dmabuf_arg) 59 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 60 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 61 struct drm_vmw_cursor_bypass_arg) 62 63 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 64 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 65 struct drm_vmw_control_stream_arg) 66 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 67 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 68 struct drm_vmw_stream_arg) 69 #define DRM_IOCTL_VMW_UNREF_STREAM \ 70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 71 struct drm_vmw_stream_arg) 72 73 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 74 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 75 struct drm_vmw_context_arg) 76 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 77 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 78 struct drm_vmw_context_arg) 79 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 80 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 81 union drm_vmw_surface_create_arg) 82 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 83 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 84 struct drm_vmw_surface_arg) 85 #define DRM_IOCTL_VMW_REF_SURFACE \ 86 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 87 union drm_vmw_surface_reference_arg) 88 #define DRM_IOCTL_VMW_EXECBUF \ 89 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 90 struct drm_vmw_execbuf_arg) 91 #define DRM_IOCTL_VMW_GET_3D_CAP \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 93 struct drm_vmw_get_3d_cap_arg) 94 #define DRM_IOCTL_VMW_FENCE_WAIT \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 96 struct drm_vmw_fence_wait_arg) 97 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 98 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 99 struct drm_vmw_fence_signaled_arg) 100 #define DRM_IOCTL_VMW_FENCE_UNREF \ 101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 102 struct drm_vmw_fence_arg) 103 #define DRM_IOCTL_VMW_FENCE_EVENT \ 104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 105 struct drm_vmw_fence_event_arg) 106 #define DRM_IOCTL_VMW_PRESENT \ 107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 108 struct drm_vmw_present_arg) 109 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 111 struct drm_vmw_present_readback_arg) 112 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 114 struct drm_vmw_update_layout_arg) 115 #define DRM_IOCTL_VMW_CREATE_SHADER \ 116 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 117 struct drm_vmw_shader_create_arg) 118 #define DRM_IOCTL_VMW_UNREF_SHADER \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 120 struct drm_vmw_shader_arg) 121 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 122 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 123 union drm_vmw_gb_surface_create_arg) 124 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 126 union drm_vmw_gb_surface_reference_arg) 127 #define DRM_IOCTL_VMW_SYNCCPU \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 129 struct drm_vmw_synccpu_arg) 130 131 /** 132 * The core DRM version of this macro doesn't account for 133 * DRM_COMMAND_BASE. 134 */ 135 136 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 137 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl} 138 139 /** 140 * Ioctl definitions. 141 */ 142 143 static const struct drm_ioctl_desc vmw_ioctls[] = { 144 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 145 DRM_AUTH | DRM_UNLOCKED), 146 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl, 147 DRM_AUTH | DRM_UNLOCKED), 148 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl, 149 DRM_AUTH | DRM_UNLOCKED), 150 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 151 vmw_kms_cursor_bypass_ioctl, 152 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 153 154 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 155 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 156 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 157 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 158 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 159 DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED), 160 161 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 162 DRM_AUTH | DRM_UNLOCKED), 163 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 164 DRM_AUTH | DRM_UNLOCKED), 165 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 166 DRM_AUTH | DRM_UNLOCKED), 167 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 168 DRM_AUTH | DRM_UNLOCKED), 169 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 170 DRM_AUTH | DRM_UNLOCKED), 171 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, 172 DRM_AUTH | DRM_UNLOCKED), 173 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 174 DRM_AUTH | DRM_UNLOCKED), 175 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 176 vmw_fence_obj_signaled_ioctl, 177 DRM_AUTH | DRM_UNLOCKED), 178 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 179 DRM_AUTH | DRM_UNLOCKED), 180 VMW_IOCTL_DEF(VMW_FENCE_EVENT, 181 vmw_fence_event_ioctl, 182 DRM_AUTH | DRM_UNLOCKED), 183 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 184 DRM_AUTH | DRM_UNLOCKED), 185 186 /* these allow direct access to the framebuffers mark as master only */ 187 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 188 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), 189 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 190 vmw_present_readback_ioctl, 191 DRM_MASTER | DRM_AUTH | DRM_UNLOCKED), 192 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 193 vmw_kms_update_layout_ioctl, 194 DRM_MASTER | DRM_UNLOCKED), 195 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 196 vmw_shader_define_ioctl, 197 DRM_AUTH | DRM_UNLOCKED), 198 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 199 vmw_shader_destroy_ioctl, 200 DRM_AUTH | DRM_UNLOCKED), 201 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 202 vmw_gb_surface_define_ioctl, 203 DRM_AUTH | DRM_UNLOCKED), 204 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 205 vmw_gb_surface_reference_ioctl, 206 DRM_AUTH | DRM_UNLOCKED), 207 VMW_IOCTL_DEF(VMW_SYNCCPU, 208 vmw_user_dmabuf_synccpu_ioctl, 209 DRM_AUTH | DRM_UNLOCKED), 210 }; 211 212 static struct pci_device_id vmw_pci_id_list[] = { 213 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 214 {0, 0, 0} 215 }; 216 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 217 218 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 219 static int vmw_force_iommu; 220 static int vmw_restrict_iommu; 221 static int vmw_force_coherent; 222 static int vmw_restrict_dma_mask; 223 224 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 225 static void vmw_master_init(struct vmw_master *); 226 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 227 void *ptr); 228 229 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 230 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 231 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 232 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 233 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 234 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 235 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 236 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 237 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 238 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 239 240 241 static void vmw_print_capabilities(uint32_t capabilities) 242 { 243 DRM_INFO("Capabilities:\n"); 244 if (capabilities & SVGA_CAP_RECT_COPY) 245 DRM_INFO(" Rect copy.\n"); 246 if (capabilities & SVGA_CAP_CURSOR) 247 DRM_INFO(" Cursor.\n"); 248 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 249 DRM_INFO(" Cursor bypass.\n"); 250 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 251 DRM_INFO(" Cursor bypass 2.\n"); 252 if (capabilities & SVGA_CAP_8BIT_EMULATION) 253 DRM_INFO(" 8bit emulation.\n"); 254 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 255 DRM_INFO(" Alpha cursor.\n"); 256 if (capabilities & SVGA_CAP_3D) 257 DRM_INFO(" 3D.\n"); 258 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 259 DRM_INFO(" Extended Fifo.\n"); 260 if (capabilities & SVGA_CAP_MULTIMON) 261 DRM_INFO(" Multimon.\n"); 262 if (capabilities & SVGA_CAP_PITCHLOCK) 263 DRM_INFO(" Pitchlock.\n"); 264 if (capabilities & SVGA_CAP_IRQMASK) 265 DRM_INFO(" Irq mask.\n"); 266 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 267 DRM_INFO(" Display Topology.\n"); 268 if (capabilities & SVGA_CAP_GMR) 269 DRM_INFO(" GMR.\n"); 270 if (capabilities & SVGA_CAP_TRACES) 271 DRM_INFO(" Traces.\n"); 272 if (capabilities & SVGA_CAP_GMR2) 273 DRM_INFO(" GMR2.\n"); 274 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 275 DRM_INFO(" Screen Object 2.\n"); 276 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 277 DRM_INFO(" Command Buffers.\n"); 278 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 279 DRM_INFO(" Command Buffers 2.\n"); 280 if (capabilities & SVGA_CAP_GBOBJECTS) 281 DRM_INFO(" Guest Backed Resources.\n"); 282 } 283 284 /** 285 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 286 * 287 * @dev_priv: A device private structure. 288 * 289 * This function creates a small buffer object that holds the query 290 * result for dummy queries emitted as query barriers. 291 * The function will then map the first page and initialize a pending 292 * occlusion query result structure, Finally it will unmap the buffer. 293 * No interruptible waits are done within this function. 294 * 295 * Returns an error if bo creation or initialization fails. 296 */ 297 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 298 { 299 int ret; 300 struct ttm_buffer_object *bo; 301 struct ttm_bo_kmap_obj map; 302 volatile SVGA3dQueryResult *result; 303 bool dummy; 304 305 /* 306 * Create the bo as pinned, so that a tryreserve will 307 * immediately succeed. This is because we're the only 308 * user of the bo currently. 309 */ 310 ret = ttm_bo_create(&dev_priv->bdev, 311 PAGE_SIZE, 312 ttm_bo_type_device, 313 &vmw_sys_ne_placement, 314 0, false, NULL, 315 &bo); 316 317 if (unlikely(ret != 0)) 318 return ret; 319 320 ret = ttm_bo_reserve(bo, false, true, false, 0); 321 BUG_ON(ret != 0); 322 323 ret = ttm_bo_kmap(bo, 0, 1, &map); 324 if (likely(ret == 0)) { 325 result = ttm_kmap_obj_virtual(&map, &dummy); 326 result->totalSize = sizeof(*result); 327 result->state = SVGA3D_QUERYSTATE_PENDING; 328 result->result32 = 0xff; 329 ttm_bo_kunmap(&map); 330 } 331 vmw_bo_pin(bo, false); 332 ttm_bo_unreserve(bo); 333 334 if (unlikely(ret != 0)) { 335 DRM_ERROR("Dummy query buffer map failed.\n"); 336 ttm_bo_unref(&bo); 337 } else 338 dev_priv->dummy_query_bo = bo; 339 340 return ret; 341 } 342 343 static int vmw_request_device(struct vmw_private *dev_priv) 344 { 345 int ret; 346 347 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 348 if (unlikely(ret != 0)) { 349 DRM_ERROR("Unable to initialize FIFO.\n"); 350 return ret; 351 } 352 vmw_fence_fifo_up(dev_priv->fman); 353 if (dev_priv->has_mob) { 354 ret = vmw_otables_setup(dev_priv); 355 if (unlikely(ret != 0)) { 356 DRM_ERROR("Unable to initialize " 357 "guest Memory OBjects.\n"); 358 goto out_no_mob; 359 } 360 } 361 ret = vmw_dummy_query_bo_create(dev_priv); 362 if (unlikely(ret != 0)) 363 goto out_no_query_bo; 364 365 return 0; 366 367 out_no_query_bo: 368 if (dev_priv->has_mob) 369 vmw_otables_takedown(dev_priv); 370 out_no_mob: 371 vmw_fence_fifo_down(dev_priv->fman); 372 vmw_fifo_release(dev_priv, &dev_priv->fifo); 373 return ret; 374 } 375 376 static void vmw_release_device(struct vmw_private *dev_priv) 377 { 378 /* 379 * Previous destructions should've released 380 * the pinned bo. 381 */ 382 383 BUG_ON(dev_priv->pinned_bo != NULL); 384 385 ttm_bo_unref(&dev_priv->dummy_query_bo); 386 if (dev_priv->has_mob) 387 vmw_otables_takedown(dev_priv); 388 vmw_fence_fifo_down(dev_priv->fman); 389 vmw_fifo_release(dev_priv, &dev_priv->fifo); 390 } 391 392 393 /** 394 * Increase the 3d resource refcount. 395 * If the count was prevously zero, initialize the fifo, switching to svga 396 * mode. Note that the master holds a ref as well, and may request an 397 * explicit switch to svga mode if fb is not running, using @unhide_svga. 398 */ 399 int vmw_3d_resource_inc(struct vmw_private *dev_priv, 400 bool unhide_svga) 401 { 402 int ret = 0; 403 404 mutex_lock(&dev_priv->release_mutex); 405 if (unlikely(dev_priv->num_3d_resources++ == 0)) { 406 ret = vmw_request_device(dev_priv); 407 if (unlikely(ret != 0)) 408 --dev_priv->num_3d_resources; 409 } else if (unhide_svga) { 410 mutex_lock(&dev_priv->hw_mutex); 411 vmw_write(dev_priv, SVGA_REG_ENABLE, 412 vmw_read(dev_priv, SVGA_REG_ENABLE) & 413 ~SVGA_REG_ENABLE_HIDE); 414 mutex_unlock(&dev_priv->hw_mutex); 415 } 416 417 mutex_unlock(&dev_priv->release_mutex); 418 return ret; 419 } 420 421 /** 422 * Decrease the 3d resource refcount. 423 * If the count reaches zero, disable the fifo, switching to vga mode. 424 * Note that the master holds a refcount as well, and may request an 425 * explicit switch to vga mode when it releases its refcount to account 426 * for the situation of an X server vt switch to VGA with 3d resources 427 * active. 428 */ 429 void vmw_3d_resource_dec(struct vmw_private *dev_priv, 430 bool hide_svga) 431 { 432 int32_t n3d; 433 434 mutex_lock(&dev_priv->release_mutex); 435 if (unlikely(--dev_priv->num_3d_resources == 0)) 436 vmw_release_device(dev_priv); 437 else if (hide_svga) { 438 mutex_lock(&dev_priv->hw_mutex); 439 vmw_write(dev_priv, SVGA_REG_ENABLE, 440 vmw_read(dev_priv, SVGA_REG_ENABLE) | 441 SVGA_REG_ENABLE_HIDE); 442 mutex_unlock(&dev_priv->hw_mutex); 443 } 444 445 n3d = (int32_t) dev_priv->num_3d_resources; 446 mutex_unlock(&dev_priv->release_mutex); 447 448 BUG_ON(n3d < 0); 449 } 450 451 /** 452 * Sets the initial_[width|height] fields on the given vmw_private. 453 * 454 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 455 * clamping the value to fb_max_[width|height] fields and the 456 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 457 * If the values appear to be invalid, set them to 458 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 459 */ 460 static void vmw_get_initial_size(struct vmw_private *dev_priv) 461 { 462 uint32_t width; 463 uint32_t height; 464 465 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 466 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 467 468 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 469 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 470 471 if (width > dev_priv->fb_max_width || 472 height > dev_priv->fb_max_height) { 473 474 /* 475 * This is a host error and shouldn't occur. 476 */ 477 478 width = VMW_MIN_INITIAL_WIDTH; 479 height = VMW_MIN_INITIAL_HEIGHT; 480 } 481 482 dev_priv->initial_width = width; 483 dev_priv->initial_height = height; 484 } 485 486 /** 487 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 488 * system. 489 * 490 * @dev_priv: Pointer to a struct vmw_private 491 * 492 * This functions tries to determine the IOMMU setup and what actions 493 * need to be taken by the driver to make system pages visible to the 494 * device. 495 * If this function decides that DMA is not possible, it returns -EINVAL. 496 * The driver may then try to disable features of the device that require 497 * DMA. 498 */ 499 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 500 { 501 static const char *names[vmw_dma_map_max] = { 502 [vmw_dma_phys] = "Using physical TTM page addresses.", 503 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 504 [vmw_dma_map_populate] = "Keeping DMA mappings.", 505 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 506 #ifdef CONFIG_X86 507 const struct dma_map_ops *dma_ops = get_dma_ops(dev_priv->dev->dev); 508 509 #ifdef CONFIG_INTEL_IOMMU 510 if (intel_iommu_enabled) { 511 dev_priv->map_mode = vmw_dma_map_populate; 512 goto out_fixup; 513 } 514 #endif 515 516 if (!(vmw_force_iommu || vmw_force_coherent)) { 517 dev_priv->map_mode = vmw_dma_phys; 518 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 519 return 0; 520 } 521 522 dev_priv->map_mode = vmw_dma_map_populate; 523 524 if (dma_ops->sync_single_for_cpu) 525 dev_priv->map_mode = vmw_dma_alloc_coherent; 526 #ifdef CONFIG_SWIOTLB 527 if (swiotlb_nr_tbl() == 0) 528 dev_priv->map_mode = vmw_dma_map_populate; 529 #endif 530 531 #ifdef CONFIG_INTEL_IOMMU 532 out_fixup: 533 #endif 534 if (dev_priv->map_mode == vmw_dma_map_populate && 535 vmw_restrict_iommu) 536 dev_priv->map_mode = vmw_dma_map_bind; 537 538 if (vmw_force_coherent) 539 dev_priv->map_mode = vmw_dma_alloc_coherent; 540 541 #if !defined(CONFIG_SWIOTLB) && !defined(CONFIG_INTEL_IOMMU) 542 /* 543 * No coherent page pool 544 */ 545 if (dev_priv->map_mode == vmw_dma_alloc_coherent) 546 return -EINVAL; 547 #endif 548 549 #else /* CONFIG_X86 */ 550 dev_priv->map_mode = vmw_dma_map_populate; 551 #endif /* CONFIG_X86 */ 552 553 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 554 555 return 0; 556 } 557 558 /** 559 * vmw_dma_masks - set required page- and dma masks 560 * 561 * @dev: Pointer to struct drm-device 562 * 563 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 564 * restriction also for 64-bit systems. 565 */ 566 #ifdef CONFIG_INTEL_IOMMU 567 static int vmw_dma_masks(struct vmw_private *dev_priv) 568 { 569 struct drm_device *dev = dev_priv->dev; 570 571 if (intel_iommu_enabled && 572 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 573 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 574 return dma_set_mask(dev->dev, DMA_BIT_MASK(44)); 575 } 576 return 0; 577 } 578 #else 579 static int vmw_dma_masks(struct vmw_private *dev_priv) 580 { 581 return 0; 582 } 583 #endif 584 585 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 586 { 587 struct vmw_private *dev_priv; 588 int ret; 589 uint32_t svga_id; 590 enum vmw_res_type i; 591 bool refuse_dma = false; 592 593 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 594 if (unlikely(dev_priv == NULL)) { 595 DRM_ERROR("Failed allocating a device private struct.\n"); 596 return -ENOMEM; 597 } 598 599 pci_set_master(dev->pdev); 600 601 dev_priv->dev = dev; 602 dev_priv->vmw_chipset = chipset; 603 dev_priv->last_read_seqno = (uint32_t) -100; 604 mutex_init(&dev_priv->hw_mutex); 605 mutex_init(&dev_priv->cmdbuf_mutex); 606 mutex_init(&dev_priv->release_mutex); 607 mutex_init(&dev_priv->binding_mutex); 608 rwlock_init(&dev_priv->resource_lock); 609 610 for (i = vmw_res_context; i < vmw_res_max; ++i) { 611 idr_init(&dev_priv->res_idr[i]); 612 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 613 } 614 615 mutex_init(&dev_priv->init_mutex); 616 init_waitqueue_head(&dev_priv->fence_queue); 617 init_waitqueue_head(&dev_priv->fifo_queue); 618 dev_priv->fence_queue_waiters = 0; 619 atomic_set(&dev_priv->fifo_queue_waiters, 0); 620 621 dev_priv->used_memory_size = 0; 622 623 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 624 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 625 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 626 627 dev_priv->enable_fb = enable_fbdev; 628 629 mutex_lock(&dev_priv->hw_mutex); 630 631 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 632 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 633 if (svga_id != SVGA_ID_2) { 634 ret = -ENOSYS; 635 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 636 mutex_unlock(&dev_priv->hw_mutex); 637 goto out_err0; 638 } 639 640 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 641 ret = vmw_dma_select_mode(dev_priv); 642 if (unlikely(ret != 0)) { 643 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 644 refuse_dma = true; 645 } 646 647 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 648 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 649 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 650 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 651 652 vmw_get_initial_size(dev_priv); 653 654 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 655 dev_priv->max_gmr_ids = 656 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 657 dev_priv->max_gmr_pages = 658 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 659 dev_priv->memory_size = 660 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 661 dev_priv->memory_size -= dev_priv->vram_size; 662 } else { 663 /* 664 * An arbitrary limit of 512MiB on surface 665 * memory. But all HWV8 hardware supports GMR2. 666 */ 667 dev_priv->memory_size = 512*1024*1024; 668 } 669 dev_priv->max_mob_pages = 0; 670 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 671 uint64_t mem_size = 672 vmw_read(dev_priv, 673 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 674 675 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 676 dev_priv->prim_bb_mem = 677 vmw_read(dev_priv, 678 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 679 } else 680 dev_priv->prim_bb_mem = dev_priv->vram_size; 681 682 ret = vmw_dma_masks(dev_priv); 683 if (unlikely(ret != 0)) { 684 mutex_unlock(&dev_priv->hw_mutex); 685 goto out_err0; 686 } 687 688 if (unlikely(dev_priv->prim_bb_mem < dev_priv->vram_size)) 689 dev_priv->prim_bb_mem = dev_priv->vram_size; 690 691 mutex_unlock(&dev_priv->hw_mutex); 692 693 vmw_print_capabilities(dev_priv->capabilities); 694 695 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 696 DRM_INFO("Max GMR ids is %u\n", 697 (unsigned)dev_priv->max_gmr_ids); 698 DRM_INFO("Max number of GMR pages is %u\n", 699 (unsigned)dev_priv->max_gmr_pages); 700 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 701 (unsigned)dev_priv->memory_size / 1024); 702 } 703 DRM_INFO("Maximum display memory size is %u kiB\n", 704 dev_priv->prim_bb_mem / 1024); 705 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 706 dev_priv->vram_start, dev_priv->vram_size / 1024); 707 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 708 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 709 710 ret = vmw_ttm_global_init(dev_priv); 711 if (unlikely(ret != 0)) 712 goto out_err0; 713 714 715 vmw_master_init(&dev_priv->fbdev_master); 716 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 717 dev_priv->active_master = &dev_priv->fbdev_master; 718 719 720 ret = ttm_bo_device_init(&dev_priv->bdev, 721 dev_priv->bo_global_ref.ref.object, 722 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET, 723 false); 724 if (unlikely(ret != 0)) { 725 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 726 goto out_err1; 727 } 728 729 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 730 (dev_priv->vram_size >> PAGE_SHIFT)); 731 if (unlikely(ret != 0)) { 732 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 733 goto out_err2; 734 } 735 736 dev_priv->has_gmr = true; 737 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 738 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 739 VMW_PL_GMR) != 0) { 740 DRM_INFO("No GMR memory available. " 741 "Graphics memory resources are very limited.\n"); 742 dev_priv->has_gmr = false; 743 } 744 745 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 746 dev_priv->has_mob = true; 747 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 748 VMW_PL_MOB) != 0) { 749 DRM_INFO("No MOB memory available. " 750 "3D will be disabled.\n"); 751 dev_priv->has_mob = false; 752 } 753 } 754 755 dev_priv->mmio_mtrr = arch_phys_wc_add(dev_priv->mmio_start, 756 dev_priv->mmio_size); 757 758 dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start, 759 dev_priv->mmio_size); 760 761 if (unlikely(dev_priv->mmio_virt == NULL)) { 762 ret = -ENOMEM; 763 DRM_ERROR("Failed mapping MMIO.\n"); 764 goto out_err3; 765 } 766 767 /* Need mmio memory to check for fifo pitchlock cap. */ 768 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 769 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 770 !vmw_fifo_have_pitchlock(dev_priv)) { 771 ret = -ENOSYS; 772 DRM_ERROR("Hardware has no pitchlock\n"); 773 goto out_err4; 774 } 775 776 dev_priv->tdev = ttm_object_device_init 777 (dev_priv->mem_global_ref.object, 12, &vmw_prime_dmabuf_ops); 778 779 if (unlikely(dev_priv->tdev == NULL)) { 780 DRM_ERROR("Unable to initialize TTM object management.\n"); 781 ret = -ENOMEM; 782 goto out_err4; 783 } 784 785 dev->dev_private = dev_priv; 786 787 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 788 dev_priv->stealth = (ret != 0); 789 if (dev_priv->stealth) { 790 /** 791 * Request at least the mmio PCI resource. 792 */ 793 794 DRM_INFO("It appears like vesafb is loaded. " 795 "Ignore above error if any.\n"); 796 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 797 if (unlikely(ret != 0)) { 798 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 799 goto out_no_device; 800 } 801 } 802 803 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 804 ret = drm_irq_install(dev); 805 if (ret != 0) { 806 DRM_ERROR("Failed installing irq: %d\n", ret); 807 goto out_no_irq; 808 } 809 } 810 811 dev_priv->fman = vmw_fence_manager_init(dev_priv); 812 if (unlikely(dev_priv->fman == NULL)) { 813 ret = -ENOMEM; 814 goto out_no_fman; 815 } 816 817 vmw_kms_save_vga(dev_priv); 818 819 /* Start kms and overlay systems, needs fifo. */ 820 ret = vmw_kms_init(dev_priv); 821 if (unlikely(ret != 0)) 822 goto out_no_kms; 823 vmw_overlay_init(dev_priv); 824 825 if (dev_priv->enable_fb) { 826 ret = vmw_3d_resource_inc(dev_priv, true); 827 if (unlikely(ret != 0)) 828 goto out_no_fifo; 829 vmw_fb_init(dev_priv); 830 } 831 832 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 833 register_pm_notifier(&dev_priv->pm_nb); 834 835 return 0; 836 837 out_no_fifo: 838 vmw_overlay_close(dev_priv); 839 vmw_kms_close(dev_priv); 840 out_no_kms: 841 vmw_kms_restore_vga(dev_priv); 842 vmw_fence_manager_takedown(dev_priv->fman); 843 out_no_fman: 844 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 845 drm_irq_uninstall(dev_priv->dev); 846 out_no_irq: 847 if (dev_priv->stealth) 848 pci_release_region(dev->pdev, 2); 849 else 850 pci_release_regions(dev->pdev); 851 out_no_device: 852 ttm_object_device_release(&dev_priv->tdev); 853 out_err4: 854 iounmap(dev_priv->mmio_virt); 855 out_err3: 856 arch_phys_wc_del(dev_priv->mmio_mtrr); 857 if (dev_priv->has_mob) 858 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 859 if (dev_priv->has_gmr) 860 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 861 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 862 out_err2: 863 (void)ttm_bo_device_release(&dev_priv->bdev); 864 out_err1: 865 vmw_ttm_global_release(dev_priv); 866 out_err0: 867 for (i = vmw_res_context; i < vmw_res_max; ++i) 868 idr_destroy(&dev_priv->res_idr[i]); 869 870 kfree(dev_priv); 871 return ret; 872 } 873 874 static int vmw_driver_unload(struct drm_device *dev) 875 { 876 struct vmw_private *dev_priv = vmw_priv(dev); 877 enum vmw_res_type i; 878 879 unregister_pm_notifier(&dev_priv->pm_nb); 880 881 if (dev_priv->ctx.res_ht_initialized) 882 drm_ht_remove(&dev_priv->ctx.res_ht); 883 if (dev_priv->ctx.cmd_bounce) 884 vfree(dev_priv->ctx.cmd_bounce); 885 if (dev_priv->enable_fb) { 886 vmw_fb_close(dev_priv); 887 vmw_kms_restore_vga(dev_priv); 888 vmw_3d_resource_dec(dev_priv, false); 889 } 890 vmw_kms_close(dev_priv); 891 vmw_overlay_close(dev_priv); 892 vmw_fence_manager_takedown(dev_priv->fman); 893 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 894 drm_irq_uninstall(dev_priv->dev); 895 if (dev_priv->stealth) 896 pci_release_region(dev->pdev, 2); 897 else 898 pci_release_regions(dev->pdev); 899 900 ttm_object_device_release(&dev_priv->tdev); 901 iounmap(dev_priv->mmio_virt); 902 arch_phys_wc_del(dev_priv->mmio_mtrr); 903 if (dev_priv->has_mob) 904 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 905 if (dev_priv->has_gmr) 906 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 907 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 908 (void)ttm_bo_device_release(&dev_priv->bdev); 909 vmw_ttm_global_release(dev_priv); 910 911 for (i = vmw_res_context; i < vmw_res_max; ++i) 912 idr_destroy(&dev_priv->res_idr[i]); 913 914 kfree(dev_priv); 915 916 return 0; 917 } 918 919 static void vmw_preclose(struct drm_device *dev, 920 struct drm_file *file_priv) 921 { 922 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 923 struct vmw_private *dev_priv = vmw_priv(dev); 924 925 vmw_event_fence_fpriv_gone(dev_priv->fman, &vmw_fp->fence_events); 926 } 927 928 static void vmw_postclose(struct drm_device *dev, 929 struct drm_file *file_priv) 930 { 931 struct vmw_fpriv *vmw_fp; 932 933 vmw_fp = vmw_fpriv(file_priv); 934 935 if (vmw_fp->locked_master) { 936 struct vmw_master *vmaster = 937 vmw_master(vmw_fp->locked_master); 938 939 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 940 ttm_vt_unlock(&vmaster->lock); 941 drm_master_put(&vmw_fp->locked_master); 942 } 943 944 ttm_object_file_release(&vmw_fp->tfile); 945 kfree(vmw_fp); 946 } 947 948 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 949 { 950 struct vmw_private *dev_priv = vmw_priv(dev); 951 struct vmw_fpriv *vmw_fp; 952 int ret = -ENOMEM; 953 954 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 955 if (unlikely(vmw_fp == NULL)) 956 return ret; 957 958 INIT_LIST_HEAD(&vmw_fp->fence_events); 959 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 960 if (unlikely(vmw_fp->tfile == NULL)) 961 goto out_no_tfile; 962 963 file_priv->driver_priv = vmw_fp; 964 dev_priv->bdev.dev_mapping = dev->dev_mapping; 965 966 return 0; 967 968 out_no_tfile: 969 kfree(vmw_fp); 970 return ret; 971 } 972 973 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 974 unsigned long arg) 975 { 976 struct drm_file *file_priv = filp->private_data; 977 struct drm_device *dev = file_priv->minor->dev; 978 unsigned int nr = DRM_IOCTL_NR(cmd); 979 980 /* 981 * Do extra checking on driver private ioctls. 982 */ 983 984 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 985 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 986 const struct drm_ioctl_desc *ioctl = 987 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 988 989 if (unlikely(ioctl->cmd_drv != cmd)) { 990 DRM_ERROR("Invalid command format, ioctl %d\n", 991 nr - DRM_COMMAND_BASE); 992 return -EINVAL; 993 } 994 } 995 996 return drm_ioctl(filp, cmd, arg); 997 } 998 999 static void vmw_lastclose(struct drm_device *dev) 1000 { 1001 struct drm_crtc *crtc; 1002 struct drm_mode_set set; 1003 int ret; 1004 1005 set.x = 0; 1006 set.y = 0; 1007 set.fb = NULL; 1008 set.mode = NULL; 1009 set.connectors = NULL; 1010 set.num_connectors = 0; 1011 1012 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1013 set.crtc = crtc; 1014 ret = drm_mode_set_config_internal(&set); 1015 WARN_ON(ret != 0); 1016 } 1017 1018 } 1019 1020 static void vmw_master_init(struct vmw_master *vmaster) 1021 { 1022 ttm_lock_init(&vmaster->lock); 1023 INIT_LIST_HEAD(&vmaster->fb_surf); 1024 mutex_init(&vmaster->fb_surf_mutex); 1025 } 1026 1027 static int vmw_master_create(struct drm_device *dev, 1028 struct drm_master *master) 1029 { 1030 struct vmw_master *vmaster; 1031 1032 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); 1033 if (unlikely(vmaster == NULL)) 1034 return -ENOMEM; 1035 1036 vmw_master_init(vmaster); 1037 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1038 master->driver_priv = vmaster; 1039 1040 return 0; 1041 } 1042 1043 static void vmw_master_destroy(struct drm_device *dev, 1044 struct drm_master *master) 1045 { 1046 struct vmw_master *vmaster = vmw_master(master); 1047 1048 master->driver_priv = NULL; 1049 kfree(vmaster); 1050 } 1051 1052 1053 static int vmw_master_set(struct drm_device *dev, 1054 struct drm_file *file_priv, 1055 bool from_open) 1056 { 1057 struct vmw_private *dev_priv = vmw_priv(dev); 1058 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1059 struct vmw_master *active = dev_priv->active_master; 1060 struct vmw_master *vmaster = vmw_master(file_priv->master); 1061 int ret = 0; 1062 1063 if (!dev_priv->enable_fb) { 1064 ret = vmw_3d_resource_inc(dev_priv, true); 1065 if (unlikely(ret != 0)) 1066 return ret; 1067 vmw_kms_save_vga(dev_priv); 1068 mutex_lock(&dev_priv->hw_mutex); 1069 vmw_write(dev_priv, SVGA_REG_TRACES, 0); 1070 mutex_unlock(&dev_priv->hw_mutex); 1071 } 1072 1073 if (active) { 1074 BUG_ON(active != &dev_priv->fbdev_master); 1075 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 1076 if (unlikely(ret != 0)) 1077 goto out_no_active_lock; 1078 1079 ttm_lock_set_kill(&active->lock, true, SIGTERM); 1080 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); 1081 if (unlikely(ret != 0)) { 1082 DRM_ERROR("Unable to clean VRAM on " 1083 "master drop.\n"); 1084 } 1085 1086 dev_priv->active_master = NULL; 1087 } 1088 1089 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1090 if (!from_open) { 1091 ttm_vt_unlock(&vmaster->lock); 1092 BUG_ON(vmw_fp->locked_master != file_priv->master); 1093 drm_master_put(&vmw_fp->locked_master); 1094 } 1095 1096 dev_priv->active_master = vmaster; 1097 1098 return 0; 1099 1100 out_no_active_lock: 1101 if (!dev_priv->enable_fb) { 1102 vmw_kms_restore_vga(dev_priv); 1103 vmw_3d_resource_dec(dev_priv, true); 1104 mutex_lock(&dev_priv->hw_mutex); 1105 vmw_write(dev_priv, SVGA_REG_TRACES, 1); 1106 mutex_unlock(&dev_priv->hw_mutex); 1107 } 1108 return ret; 1109 } 1110 1111 static void vmw_master_drop(struct drm_device *dev, 1112 struct drm_file *file_priv, 1113 bool from_release) 1114 { 1115 struct vmw_private *dev_priv = vmw_priv(dev); 1116 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1117 struct vmw_master *vmaster = vmw_master(file_priv->master); 1118 int ret; 1119 1120 /** 1121 * Make sure the master doesn't disappear while we have 1122 * it locked. 1123 */ 1124 1125 vmw_fp->locked_master = drm_master_get(file_priv->master); 1126 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 1127 if (unlikely((ret != 0))) { 1128 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 1129 drm_master_put(&vmw_fp->locked_master); 1130 } 1131 1132 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1133 vmw_execbuf_release_pinned_bo(dev_priv); 1134 1135 if (!dev_priv->enable_fb) { 1136 ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM); 1137 if (unlikely(ret != 0)) 1138 DRM_ERROR("Unable to clean VRAM on master drop.\n"); 1139 vmw_kms_restore_vga(dev_priv); 1140 vmw_3d_resource_dec(dev_priv, true); 1141 mutex_lock(&dev_priv->hw_mutex); 1142 vmw_write(dev_priv, SVGA_REG_TRACES, 1); 1143 mutex_unlock(&dev_priv->hw_mutex); 1144 } 1145 1146 dev_priv->active_master = &dev_priv->fbdev_master; 1147 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 1148 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 1149 1150 if (dev_priv->enable_fb) 1151 vmw_fb_on(dev_priv); 1152 } 1153 1154 1155 static void vmw_remove(struct pci_dev *pdev) 1156 { 1157 struct drm_device *dev = pci_get_drvdata(pdev); 1158 1159 drm_put_dev(dev); 1160 } 1161 1162 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1163 void *ptr) 1164 { 1165 struct vmw_private *dev_priv = 1166 container_of(nb, struct vmw_private, pm_nb); 1167 struct vmw_master *vmaster = dev_priv->active_master; 1168 1169 switch (val) { 1170 case PM_HIBERNATION_PREPARE: 1171 case PM_SUSPEND_PREPARE: 1172 ttm_suspend_lock(&vmaster->lock); 1173 1174 /** 1175 * This empties VRAM and unbinds all GMR bindings. 1176 * Buffer contents is moved to swappable memory. 1177 */ 1178 vmw_execbuf_release_pinned_bo(dev_priv); 1179 vmw_resource_evict_all(dev_priv); 1180 ttm_bo_swapout_all(&dev_priv->bdev); 1181 1182 break; 1183 case PM_POST_HIBERNATION: 1184 case PM_POST_SUSPEND: 1185 case PM_POST_RESTORE: 1186 ttm_suspend_unlock(&vmaster->lock); 1187 1188 break; 1189 case PM_RESTORE_PREPARE: 1190 break; 1191 default: 1192 break; 1193 } 1194 return 0; 1195 } 1196 1197 /** 1198 * These might not be needed with the virtual SVGA device. 1199 */ 1200 1201 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1202 { 1203 struct drm_device *dev = pci_get_drvdata(pdev); 1204 struct vmw_private *dev_priv = vmw_priv(dev); 1205 1206 if (dev_priv->num_3d_resources != 0) { 1207 DRM_INFO("Can't suspend or hibernate " 1208 "while 3D resources are active.\n"); 1209 return -EBUSY; 1210 } 1211 1212 pci_save_state(pdev); 1213 pci_disable_device(pdev); 1214 pci_set_power_state(pdev, PCI_D3hot); 1215 return 0; 1216 } 1217 1218 static int vmw_pci_resume(struct pci_dev *pdev) 1219 { 1220 pci_set_power_state(pdev, PCI_D0); 1221 pci_restore_state(pdev); 1222 return pci_enable_device(pdev); 1223 } 1224 1225 static int vmw_pm_suspend(struct device *kdev) 1226 { 1227 struct pci_dev *pdev = to_pci_dev(kdev); 1228 struct pm_message dummy; 1229 1230 dummy.event = 0; 1231 1232 return vmw_pci_suspend(pdev, dummy); 1233 } 1234 1235 static int vmw_pm_resume(struct device *kdev) 1236 { 1237 struct pci_dev *pdev = to_pci_dev(kdev); 1238 1239 return vmw_pci_resume(pdev); 1240 } 1241 1242 static int vmw_pm_prepare(struct device *kdev) 1243 { 1244 struct pci_dev *pdev = to_pci_dev(kdev); 1245 struct drm_device *dev = pci_get_drvdata(pdev); 1246 struct vmw_private *dev_priv = vmw_priv(dev); 1247 1248 /** 1249 * Release 3d reference held by fbdev and potentially 1250 * stop fifo. 1251 */ 1252 dev_priv->suspended = true; 1253 if (dev_priv->enable_fb) 1254 vmw_3d_resource_dec(dev_priv, true); 1255 1256 if (dev_priv->num_3d_resources != 0) { 1257 1258 DRM_INFO("Can't suspend or hibernate " 1259 "while 3D resources are active.\n"); 1260 1261 if (dev_priv->enable_fb) 1262 vmw_3d_resource_inc(dev_priv, true); 1263 dev_priv->suspended = false; 1264 return -EBUSY; 1265 } 1266 1267 return 0; 1268 } 1269 1270 static void vmw_pm_complete(struct device *kdev) 1271 { 1272 struct pci_dev *pdev = to_pci_dev(kdev); 1273 struct drm_device *dev = pci_get_drvdata(pdev); 1274 struct vmw_private *dev_priv = vmw_priv(dev); 1275 1276 mutex_lock(&dev_priv->hw_mutex); 1277 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1278 (void) vmw_read(dev_priv, SVGA_REG_ID); 1279 mutex_unlock(&dev_priv->hw_mutex); 1280 1281 /** 1282 * Reclaim 3d reference held by fbdev and potentially 1283 * start fifo. 1284 */ 1285 if (dev_priv->enable_fb) 1286 vmw_3d_resource_inc(dev_priv, false); 1287 1288 dev_priv->suspended = false; 1289 } 1290 1291 static const struct dev_pm_ops vmw_pm_ops = { 1292 .prepare = vmw_pm_prepare, 1293 .complete = vmw_pm_complete, 1294 .suspend = vmw_pm_suspend, 1295 .resume = vmw_pm_resume, 1296 }; 1297 1298 static const struct file_operations vmwgfx_driver_fops = { 1299 .owner = THIS_MODULE, 1300 .open = drm_open, 1301 .release = drm_release, 1302 .unlocked_ioctl = vmw_unlocked_ioctl, 1303 .mmap = vmw_mmap, 1304 .poll = vmw_fops_poll, 1305 .read = vmw_fops_read, 1306 #if defined(CONFIG_COMPAT) 1307 .compat_ioctl = drm_compat_ioctl, 1308 #endif 1309 .llseek = noop_llseek, 1310 }; 1311 1312 static struct drm_driver driver = { 1313 .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | 1314 DRIVER_MODESET | DRIVER_PRIME, 1315 .load = vmw_driver_load, 1316 .unload = vmw_driver_unload, 1317 .lastclose = vmw_lastclose, 1318 .irq_preinstall = vmw_irq_preinstall, 1319 .irq_postinstall = vmw_irq_postinstall, 1320 .irq_uninstall = vmw_irq_uninstall, 1321 .irq_handler = vmw_irq_handler, 1322 .get_vblank_counter = vmw_get_vblank_counter, 1323 .enable_vblank = vmw_enable_vblank, 1324 .disable_vblank = vmw_disable_vblank, 1325 .ioctls = vmw_ioctls, 1326 .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls), 1327 .master_create = vmw_master_create, 1328 .master_destroy = vmw_master_destroy, 1329 .master_set = vmw_master_set, 1330 .master_drop = vmw_master_drop, 1331 .open = vmw_driver_open, 1332 .preclose = vmw_preclose, 1333 .postclose = vmw_postclose, 1334 1335 .dumb_create = vmw_dumb_create, 1336 .dumb_map_offset = vmw_dumb_map_offset, 1337 .dumb_destroy = vmw_dumb_destroy, 1338 1339 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1340 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1341 1342 .fops = &vmwgfx_driver_fops, 1343 .name = VMWGFX_DRIVER_NAME, 1344 .desc = VMWGFX_DRIVER_DESC, 1345 .date = VMWGFX_DRIVER_DATE, 1346 .major = VMWGFX_DRIVER_MAJOR, 1347 .minor = VMWGFX_DRIVER_MINOR, 1348 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1349 }; 1350 1351 static struct pci_driver vmw_pci_driver = { 1352 .name = VMWGFX_DRIVER_NAME, 1353 .id_table = vmw_pci_id_list, 1354 .probe = vmw_probe, 1355 .remove = vmw_remove, 1356 .driver = { 1357 .pm = &vmw_pm_ops 1358 } 1359 }; 1360 1361 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1362 { 1363 return drm_get_pci_dev(pdev, ent, &driver); 1364 } 1365 1366 static int __init vmwgfx_init(void) 1367 { 1368 int ret; 1369 ret = drm_pci_init(&driver, &vmw_pci_driver); 1370 if (ret) 1371 DRM_ERROR("Failed initializing DRM.\n"); 1372 return ret; 1373 } 1374 1375 static void __exit vmwgfx_exit(void) 1376 { 1377 drm_pci_exit(&driver, &vmw_pci_driver); 1378 } 1379 1380 module_init(vmwgfx_init); 1381 module_exit(vmwgfx_exit); 1382 1383 MODULE_AUTHOR("VMware Inc. and others"); 1384 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1385 MODULE_LICENSE("GPL and additional rights"); 1386 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1387 __stringify(VMWGFX_DRIVER_MINOR) "." 1388 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1389 "0"); 1390