1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 #include <linux/module.h> 28 #include <linux/console.h> 29 #include <linux/dma-mapping.h> 30 31 #include <drm/drmP.h> 32 #include "vmwgfx_drv.h" 33 #include "vmwgfx_binding.h" 34 #include "ttm_object.h" 35 #include <drm/ttm/ttm_placement.h> 36 #include <drm/ttm/ttm_bo_driver.h> 37 #include <drm/ttm/ttm_module.h> 38 39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 40 #define VMWGFX_CHIP_SVGAII 0 41 #define VMW_FB_RESERVATION 0 42 43 #define VMW_MIN_INITIAL_WIDTH 800 44 #define VMW_MIN_INITIAL_HEIGHT 600 45 46 #ifndef VMWGFX_GIT_VERSION 47 #define VMWGFX_GIT_VERSION "Unknown" 48 #endif 49 50 #define VMWGFX_REPO "In Tree" 51 52 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 53 54 55 /** 56 * Fully encoded drm commands. Might move to vmw_drm.h 57 */ 58 59 #define DRM_IOCTL_VMW_GET_PARAM \ 60 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 61 struct drm_vmw_getparam_arg) 62 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 63 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 64 union drm_vmw_alloc_dmabuf_arg) 65 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 66 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 67 struct drm_vmw_unref_dmabuf_arg) 68 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 69 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 70 struct drm_vmw_cursor_bypass_arg) 71 72 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 73 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 74 struct drm_vmw_control_stream_arg) 75 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 76 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 77 struct drm_vmw_stream_arg) 78 #define DRM_IOCTL_VMW_UNREF_STREAM \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 80 struct drm_vmw_stream_arg) 81 82 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 83 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 84 struct drm_vmw_context_arg) 85 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 86 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 87 struct drm_vmw_context_arg) 88 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 89 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 90 union drm_vmw_surface_create_arg) 91 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 93 struct drm_vmw_surface_arg) 94 #define DRM_IOCTL_VMW_REF_SURFACE \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 96 union drm_vmw_surface_reference_arg) 97 #define DRM_IOCTL_VMW_EXECBUF \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 99 struct drm_vmw_execbuf_arg) 100 #define DRM_IOCTL_VMW_GET_3D_CAP \ 101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 102 struct drm_vmw_get_3d_cap_arg) 103 #define DRM_IOCTL_VMW_FENCE_WAIT \ 104 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 105 struct drm_vmw_fence_wait_arg) 106 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 107 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 108 struct drm_vmw_fence_signaled_arg) 109 #define DRM_IOCTL_VMW_FENCE_UNREF \ 110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 111 struct drm_vmw_fence_arg) 112 #define DRM_IOCTL_VMW_FENCE_EVENT \ 113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 114 struct drm_vmw_fence_event_arg) 115 #define DRM_IOCTL_VMW_PRESENT \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 117 struct drm_vmw_present_arg) 118 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 120 struct drm_vmw_present_readback_arg) 121 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 123 struct drm_vmw_update_layout_arg) 124 #define DRM_IOCTL_VMW_CREATE_SHADER \ 125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 126 struct drm_vmw_shader_create_arg) 127 #define DRM_IOCTL_VMW_UNREF_SHADER \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 129 struct drm_vmw_shader_arg) 130 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 132 union drm_vmw_gb_surface_create_arg) 133 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 134 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 135 union drm_vmw_gb_surface_reference_arg) 136 #define DRM_IOCTL_VMW_SYNCCPU \ 137 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 138 struct drm_vmw_synccpu_arg) 139 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 141 struct drm_vmw_context_arg) 142 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 143 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 144 union drm_vmw_gb_surface_create_ext_arg) 145 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 147 union drm_vmw_gb_surface_reference_ext_arg) 148 149 /** 150 * The core DRM version of this macro doesn't account for 151 * DRM_COMMAND_BASE. 152 */ 153 154 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 155 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 156 157 /** 158 * Ioctl definitions. 159 */ 160 161 static const struct drm_ioctl_desc vmw_ioctls[] = { 162 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 163 DRM_AUTH | DRM_RENDER_ALLOW), 164 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 165 DRM_AUTH | DRM_RENDER_ALLOW), 166 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 167 DRM_RENDER_ALLOW), 168 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 169 vmw_kms_cursor_bypass_ioctl, 170 DRM_MASTER), 171 172 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 173 DRM_MASTER), 174 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 175 DRM_MASTER), 176 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 177 DRM_MASTER), 178 179 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 180 DRM_AUTH | DRM_RENDER_ALLOW), 181 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 182 DRM_RENDER_ALLOW), 183 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 184 DRM_AUTH | DRM_RENDER_ALLOW), 185 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 186 DRM_RENDER_ALLOW), 187 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 188 DRM_AUTH | DRM_RENDER_ALLOW), 189 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, DRM_AUTH | 190 DRM_RENDER_ALLOW), 191 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 192 DRM_RENDER_ALLOW), 193 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 194 vmw_fence_obj_signaled_ioctl, 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 197 DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 199 DRM_AUTH | DRM_RENDER_ALLOW), 200 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 201 DRM_AUTH | DRM_RENDER_ALLOW), 202 203 /* these allow direct access to the framebuffers mark as master only */ 204 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 205 DRM_MASTER | DRM_AUTH), 206 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 207 vmw_present_readback_ioctl, 208 DRM_MASTER | DRM_AUTH), 209 /* 210 * The permissions of the below ioctl are overridden in 211 * vmw_generic_ioctl(). We require either 212 * DRM_MASTER or capable(CAP_SYS_ADMIN). 213 */ 214 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 215 vmw_kms_update_layout_ioctl, 216 DRM_RENDER_ALLOW), 217 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 218 vmw_shader_define_ioctl, 219 DRM_AUTH | DRM_RENDER_ALLOW), 220 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 221 vmw_shader_destroy_ioctl, 222 DRM_RENDER_ALLOW), 223 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 224 vmw_gb_surface_define_ioctl, 225 DRM_AUTH | DRM_RENDER_ALLOW), 226 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 227 vmw_gb_surface_reference_ioctl, 228 DRM_AUTH | DRM_RENDER_ALLOW), 229 VMW_IOCTL_DEF(VMW_SYNCCPU, 230 vmw_user_bo_synccpu_ioctl, 231 DRM_RENDER_ALLOW), 232 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 233 vmw_extended_context_define_ioctl, 234 DRM_AUTH | DRM_RENDER_ALLOW), 235 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 236 vmw_gb_surface_define_ext_ioctl, 237 DRM_AUTH | DRM_RENDER_ALLOW), 238 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 239 vmw_gb_surface_reference_ext_ioctl, 240 DRM_AUTH | DRM_RENDER_ALLOW), 241 }; 242 243 static const struct pci_device_id vmw_pci_id_list[] = { 244 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 245 {0, 0, 0} 246 }; 247 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 248 249 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 250 static int vmw_force_iommu; 251 static int vmw_restrict_iommu; 252 static int vmw_force_coherent; 253 static int vmw_restrict_dma_mask; 254 static int vmw_assume_16bpp; 255 256 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 257 static void vmw_master_init(struct vmw_master *); 258 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 259 void *ptr); 260 261 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 262 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 263 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 264 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 265 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 266 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 267 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 268 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 269 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 270 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 271 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 272 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 273 274 275 static void vmw_print_capabilities2(uint32_t capabilities2) 276 { 277 DRM_INFO("Capabilities2:\n"); 278 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 279 DRM_INFO(" Grow oTable.\n"); 280 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 281 DRM_INFO(" IntraSurface copy.\n"); 282 } 283 284 static void vmw_print_capabilities(uint32_t capabilities) 285 { 286 DRM_INFO("Capabilities:\n"); 287 if (capabilities & SVGA_CAP_RECT_COPY) 288 DRM_INFO(" Rect copy.\n"); 289 if (capabilities & SVGA_CAP_CURSOR) 290 DRM_INFO(" Cursor.\n"); 291 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 292 DRM_INFO(" Cursor bypass.\n"); 293 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 294 DRM_INFO(" Cursor bypass 2.\n"); 295 if (capabilities & SVGA_CAP_8BIT_EMULATION) 296 DRM_INFO(" 8bit emulation.\n"); 297 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 298 DRM_INFO(" Alpha cursor.\n"); 299 if (capabilities & SVGA_CAP_3D) 300 DRM_INFO(" 3D.\n"); 301 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 302 DRM_INFO(" Extended Fifo.\n"); 303 if (capabilities & SVGA_CAP_MULTIMON) 304 DRM_INFO(" Multimon.\n"); 305 if (capabilities & SVGA_CAP_PITCHLOCK) 306 DRM_INFO(" Pitchlock.\n"); 307 if (capabilities & SVGA_CAP_IRQMASK) 308 DRM_INFO(" Irq mask.\n"); 309 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 310 DRM_INFO(" Display Topology.\n"); 311 if (capabilities & SVGA_CAP_GMR) 312 DRM_INFO(" GMR.\n"); 313 if (capabilities & SVGA_CAP_TRACES) 314 DRM_INFO(" Traces.\n"); 315 if (capabilities & SVGA_CAP_GMR2) 316 DRM_INFO(" GMR2.\n"); 317 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 318 DRM_INFO(" Screen Object 2.\n"); 319 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 320 DRM_INFO(" Command Buffers.\n"); 321 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 322 DRM_INFO(" Command Buffers 2.\n"); 323 if (capabilities & SVGA_CAP_GBOBJECTS) 324 DRM_INFO(" Guest Backed Resources.\n"); 325 if (capabilities & SVGA_CAP_DX) 326 DRM_INFO(" DX Features.\n"); 327 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 328 DRM_INFO(" HP Command Queue.\n"); 329 } 330 331 /** 332 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 333 * 334 * @dev_priv: A device private structure. 335 * 336 * This function creates a small buffer object that holds the query 337 * result for dummy queries emitted as query barriers. 338 * The function will then map the first page and initialize a pending 339 * occlusion query result structure, Finally it will unmap the buffer. 340 * No interruptible waits are done within this function. 341 * 342 * Returns an error if bo creation or initialization fails. 343 */ 344 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 345 { 346 int ret; 347 struct vmw_buffer_object *vbo; 348 struct ttm_bo_kmap_obj map; 349 volatile SVGA3dQueryResult *result; 350 bool dummy; 351 352 /* 353 * Create the vbo as pinned, so that a tryreserve will 354 * immediately succeed. This is because we're the only 355 * user of the bo currently. 356 */ 357 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 358 if (!vbo) 359 return -ENOMEM; 360 361 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 362 &vmw_sys_ne_placement, false, 363 &vmw_bo_bo_free); 364 if (unlikely(ret != 0)) 365 return ret; 366 367 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 368 BUG_ON(ret != 0); 369 vmw_bo_pin_reserved(vbo, true); 370 371 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 372 if (likely(ret == 0)) { 373 result = ttm_kmap_obj_virtual(&map, &dummy); 374 result->totalSize = sizeof(*result); 375 result->state = SVGA3D_QUERYSTATE_PENDING; 376 result->result32 = 0xff; 377 ttm_bo_kunmap(&map); 378 } 379 vmw_bo_pin_reserved(vbo, false); 380 ttm_bo_unreserve(&vbo->base); 381 382 if (unlikely(ret != 0)) { 383 DRM_ERROR("Dummy query buffer map failed.\n"); 384 vmw_bo_unreference(&vbo); 385 } else 386 dev_priv->dummy_query_bo = vbo; 387 388 return ret; 389 } 390 391 /** 392 * vmw_request_device_late - Perform late device setup 393 * 394 * @dev_priv: Pointer to device private. 395 * 396 * This function performs setup of otables and enables large command 397 * buffer submission. These tasks are split out to a separate function 398 * because it reverts vmw_release_device_early and is intended to be used 399 * by an error path in the hibernation code. 400 */ 401 static int vmw_request_device_late(struct vmw_private *dev_priv) 402 { 403 int ret; 404 405 if (dev_priv->has_mob) { 406 ret = vmw_otables_setup(dev_priv); 407 if (unlikely(ret != 0)) { 408 DRM_ERROR("Unable to initialize " 409 "guest Memory OBjects.\n"); 410 return ret; 411 } 412 } 413 414 if (dev_priv->cman) { 415 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 416 256*4096, 2*4096); 417 if (ret) { 418 struct vmw_cmdbuf_man *man = dev_priv->cman; 419 420 dev_priv->cman = NULL; 421 vmw_cmdbuf_man_destroy(man); 422 } 423 } 424 425 return 0; 426 } 427 428 static int vmw_request_device(struct vmw_private *dev_priv) 429 { 430 int ret; 431 432 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 433 if (unlikely(ret != 0)) { 434 DRM_ERROR("Unable to initialize FIFO.\n"); 435 return ret; 436 } 437 vmw_fence_fifo_up(dev_priv->fman); 438 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 439 if (IS_ERR(dev_priv->cman)) { 440 dev_priv->cman = NULL; 441 dev_priv->has_dx = false; 442 } 443 444 ret = vmw_request_device_late(dev_priv); 445 if (ret) 446 goto out_no_mob; 447 448 ret = vmw_dummy_query_bo_create(dev_priv); 449 if (unlikely(ret != 0)) 450 goto out_no_query_bo; 451 452 return 0; 453 454 out_no_query_bo: 455 if (dev_priv->cman) 456 vmw_cmdbuf_remove_pool(dev_priv->cman); 457 if (dev_priv->has_mob) { 458 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 459 vmw_otables_takedown(dev_priv); 460 } 461 if (dev_priv->cman) 462 vmw_cmdbuf_man_destroy(dev_priv->cman); 463 out_no_mob: 464 vmw_fence_fifo_down(dev_priv->fman); 465 vmw_fifo_release(dev_priv, &dev_priv->fifo); 466 return ret; 467 } 468 469 /** 470 * vmw_release_device_early - Early part of fifo takedown. 471 * 472 * @dev_priv: Pointer to device private struct. 473 * 474 * This is the first part of command submission takedown, to be called before 475 * buffer management is taken down. 476 */ 477 static void vmw_release_device_early(struct vmw_private *dev_priv) 478 { 479 /* 480 * Previous destructions should've released 481 * the pinned bo. 482 */ 483 484 BUG_ON(dev_priv->pinned_bo != NULL); 485 486 vmw_bo_unreference(&dev_priv->dummy_query_bo); 487 if (dev_priv->cman) 488 vmw_cmdbuf_remove_pool(dev_priv->cman); 489 490 if (dev_priv->has_mob) { 491 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 492 vmw_otables_takedown(dev_priv); 493 } 494 } 495 496 /** 497 * vmw_release_device_late - Late part of fifo takedown. 498 * 499 * @dev_priv: Pointer to device private struct. 500 * 501 * This is the last part of the command submission takedown, to be called when 502 * command submission is no longer needed. It may wait on pending fences. 503 */ 504 static void vmw_release_device_late(struct vmw_private *dev_priv) 505 { 506 vmw_fence_fifo_down(dev_priv->fman); 507 if (dev_priv->cman) 508 vmw_cmdbuf_man_destroy(dev_priv->cman); 509 510 vmw_fifo_release(dev_priv, &dev_priv->fifo); 511 } 512 513 /** 514 * Sets the initial_[width|height] fields on the given vmw_private. 515 * 516 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 517 * clamping the value to fb_max_[width|height] fields and the 518 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 519 * If the values appear to be invalid, set them to 520 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 521 */ 522 static void vmw_get_initial_size(struct vmw_private *dev_priv) 523 { 524 uint32_t width; 525 uint32_t height; 526 527 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 528 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 529 530 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 531 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 532 533 if (width > dev_priv->fb_max_width || 534 height > dev_priv->fb_max_height) { 535 536 /* 537 * This is a host error and shouldn't occur. 538 */ 539 540 width = VMW_MIN_INITIAL_WIDTH; 541 height = VMW_MIN_INITIAL_HEIGHT; 542 } 543 544 dev_priv->initial_width = width; 545 dev_priv->initial_height = height; 546 } 547 548 /** 549 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 550 * system. 551 * 552 * @dev_priv: Pointer to a struct vmw_private 553 * 554 * This functions tries to determine what actions need to be taken by the 555 * driver to make system pages visible to the device. 556 * If this function decides that DMA is not possible, it returns -EINVAL. 557 * The driver may then try to disable features of the device that require 558 * DMA. 559 */ 560 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 561 { 562 static const char *names[vmw_dma_map_max] = { 563 [vmw_dma_phys] = "Using physical TTM page addresses.", 564 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 565 [vmw_dma_map_populate] = "Caching DMA mappings.", 566 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 567 568 if (vmw_force_coherent) 569 dev_priv->map_mode = vmw_dma_alloc_coherent; 570 else if (vmw_restrict_iommu) 571 dev_priv->map_mode = vmw_dma_map_bind; 572 else 573 dev_priv->map_mode = vmw_dma_map_populate; 574 575 /* No TTM coherent page pool? FIXME: Ask TTM instead! */ 576 if (!(IS_ENABLED(CONFIG_SWIOTLB) || IS_ENABLED(CONFIG_INTEL_IOMMU)) && 577 (dev_priv->map_mode == vmw_dma_alloc_coherent)) 578 return -EINVAL; 579 580 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 581 return 0; 582 } 583 584 /** 585 * vmw_dma_masks - set required page- and dma masks 586 * 587 * @dev: Pointer to struct drm-device 588 * 589 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 590 * restriction also for 64-bit systems. 591 */ 592 static int vmw_dma_masks(struct vmw_private *dev_priv) 593 { 594 struct drm_device *dev = dev_priv->dev; 595 int ret = 0; 596 597 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 598 if (dev_priv->map_mode != vmw_dma_phys && 599 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 600 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 601 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 602 } 603 604 return ret; 605 } 606 607 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 608 { 609 struct vmw_private *dev_priv; 610 int ret; 611 uint32_t svga_id; 612 enum vmw_res_type i; 613 bool refuse_dma = false; 614 char host_log[100] = {0}; 615 616 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 617 if (unlikely(!dev_priv)) { 618 DRM_ERROR("Failed allocating a device private struct.\n"); 619 return -ENOMEM; 620 } 621 622 pci_set_master(dev->pdev); 623 624 dev_priv->dev = dev; 625 dev_priv->vmw_chipset = chipset; 626 dev_priv->last_read_seqno = (uint32_t) -100; 627 mutex_init(&dev_priv->cmdbuf_mutex); 628 mutex_init(&dev_priv->release_mutex); 629 mutex_init(&dev_priv->binding_mutex); 630 mutex_init(&dev_priv->global_kms_state_mutex); 631 ttm_lock_init(&dev_priv->reservation_sem); 632 spin_lock_init(&dev_priv->resource_lock); 633 spin_lock_init(&dev_priv->hw_lock); 634 spin_lock_init(&dev_priv->waiter_lock); 635 spin_lock_init(&dev_priv->cap_lock); 636 spin_lock_init(&dev_priv->svga_lock); 637 spin_lock_init(&dev_priv->cursor_lock); 638 639 for (i = vmw_res_context; i < vmw_res_max; ++i) { 640 idr_init(&dev_priv->res_idr[i]); 641 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 642 } 643 644 init_waitqueue_head(&dev_priv->fence_queue); 645 init_waitqueue_head(&dev_priv->fifo_queue); 646 dev_priv->fence_queue_waiters = 0; 647 dev_priv->fifo_queue_waiters = 0; 648 649 dev_priv->used_memory_size = 0; 650 651 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 652 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 653 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 654 655 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 656 657 dev_priv->enable_fb = enable_fbdev; 658 659 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 660 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 661 if (svga_id != SVGA_ID_2) { 662 ret = -ENOSYS; 663 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 664 goto out_err0; 665 } 666 667 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 668 669 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 670 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 671 } 672 673 674 ret = vmw_dma_select_mode(dev_priv); 675 if (unlikely(ret != 0)) { 676 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 677 refuse_dma = true; 678 } 679 680 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 681 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 682 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 683 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 684 685 vmw_get_initial_size(dev_priv); 686 687 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 688 dev_priv->max_gmr_ids = 689 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 690 dev_priv->max_gmr_pages = 691 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 692 dev_priv->memory_size = 693 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 694 dev_priv->memory_size -= dev_priv->vram_size; 695 } else { 696 /* 697 * An arbitrary limit of 512MiB on surface 698 * memory. But all HWV8 hardware supports GMR2. 699 */ 700 dev_priv->memory_size = 512*1024*1024; 701 } 702 dev_priv->max_mob_pages = 0; 703 dev_priv->max_mob_size = 0; 704 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 705 uint64_t mem_size = 706 vmw_read(dev_priv, 707 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 708 709 /* 710 * Workaround for low memory 2D VMs to compensate for the 711 * allocation taken by fbdev 712 */ 713 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 714 mem_size *= 3; 715 716 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 717 dev_priv->prim_bb_mem = 718 vmw_read(dev_priv, 719 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 720 dev_priv->max_mob_size = 721 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 722 dev_priv->stdu_max_width = 723 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 724 dev_priv->stdu_max_height = 725 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 726 727 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 728 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 729 dev_priv->texture_max_width = vmw_read(dev_priv, 730 SVGA_REG_DEV_CAP); 731 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 732 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 733 dev_priv->texture_max_height = vmw_read(dev_priv, 734 SVGA_REG_DEV_CAP); 735 } else { 736 dev_priv->texture_max_width = 8192; 737 dev_priv->texture_max_height = 8192; 738 dev_priv->prim_bb_mem = dev_priv->vram_size; 739 } 740 741 vmw_print_capabilities(dev_priv->capabilities); 742 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 743 vmw_print_capabilities2(dev_priv->capabilities2); 744 745 ret = vmw_dma_masks(dev_priv); 746 if (unlikely(ret != 0)) 747 goto out_err0; 748 749 dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK, 750 SCATTERLIST_MAX_SEGMENT)); 751 752 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 753 DRM_INFO("Max GMR ids is %u\n", 754 (unsigned)dev_priv->max_gmr_ids); 755 DRM_INFO("Max number of GMR pages is %u\n", 756 (unsigned)dev_priv->max_gmr_pages); 757 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 758 (unsigned)dev_priv->memory_size / 1024); 759 } 760 DRM_INFO("Maximum display memory size is %u kiB\n", 761 dev_priv->prim_bb_mem / 1024); 762 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 763 dev_priv->vram_start, dev_priv->vram_size / 1024); 764 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 765 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 766 767 vmw_master_init(&dev_priv->fbdev_master); 768 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 769 dev_priv->active_master = &dev_priv->fbdev_master; 770 771 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 772 dev_priv->mmio_size, MEMREMAP_WB); 773 774 if (unlikely(dev_priv->mmio_virt == NULL)) { 775 ret = -ENOMEM; 776 DRM_ERROR("Failed mapping MMIO.\n"); 777 goto out_err0; 778 } 779 780 /* Need mmio memory to check for fifo pitchlock cap. */ 781 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 782 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 783 !vmw_fifo_have_pitchlock(dev_priv)) { 784 ret = -ENOSYS; 785 DRM_ERROR("Hardware has no pitchlock\n"); 786 goto out_err4; 787 } 788 789 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 790 &vmw_prime_dmabuf_ops); 791 792 if (unlikely(dev_priv->tdev == NULL)) { 793 DRM_ERROR("Unable to initialize TTM object management.\n"); 794 ret = -ENOMEM; 795 goto out_err4; 796 } 797 798 dev->dev_private = dev_priv; 799 800 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 801 dev_priv->stealth = (ret != 0); 802 if (dev_priv->stealth) { 803 /** 804 * Request at least the mmio PCI resource. 805 */ 806 807 DRM_INFO("It appears like vesafb is loaded. " 808 "Ignore above error if any.\n"); 809 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 810 if (unlikely(ret != 0)) { 811 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 812 goto out_no_device; 813 } 814 } 815 816 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 817 ret = vmw_irq_install(dev, dev->pdev->irq); 818 if (ret != 0) { 819 DRM_ERROR("Failed installing irq: %d\n", ret); 820 goto out_no_irq; 821 } 822 } 823 824 dev_priv->fman = vmw_fence_manager_init(dev_priv); 825 if (unlikely(dev_priv->fman == NULL)) { 826 ret = -ENOMEM; 827 goto out_no_fman; 828 } 829 830 ret = ttm_bo_device_init(&dev_priv->bdev, 831 &vmw_bo_driver, 832 dev->anon_inode->i_mapping, 833 false); 834 if (unlikely(ret != 0)) { 835 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 836 goto out_no_bdev; 837 } 838 839 /* 840 * Enable VRAM, but initially don't use it until SVGA is enabled and 841 * unhidden. 842 */ 843 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 844 (dev_priv->vram_size >> PAGE_SHIFT)); 845 if (unlikely(ret != 0)) { 846 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 847 goto out_no_vram; 848 } 849 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 850 851 dev_priv->has_gmr = true; 852 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 853 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 854 VMW_PL_GMR) != 0) { 855 DRM_INFO("No GMR memory available. " 856 "Graphics memory resources are very limited.\n"); 857 dev_priv->has_gmr = false; 858 } 859 860 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 861 dev_priv->has_mob = true; 862 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 863 VMW_PL_MOB) != 0) { 864 DRM_INFO("No MOB memory available. " 865 "3D will be disabled.\n"); 866 dev_priv->has_mob = false; 867 } 868 } 869 870 if (dev_priv->has_mob) { 871 spin_lock(&dev_priv->cap_lock); 872 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 873 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 874 spin_unlock(&dev_priv->cap_lock); 875 } 876 877 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 878 ret = vmw_kms_init(dev_priv); 879 if (unlikely(ret != 0)) 880 goto out_no_kms; 881 vmw_overlay_init(dev_priv); 882 883 ret = vmw_request_device(dev_priv); 884 if (ret) 885 goto out_no_fifo; 886 887 if (dev_priv->has_dx) { 888 /* 889 * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 890 * support 891 */ 892 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) { 893 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 894 SVGA3D_DEVCAP_SM41); 895 dev_priv->has_sm4_1 = vmw_read(dev_priv, 896 SVGA_REG_DEV_CAP); 897 } 898 } 899 900 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 901 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 902 ? "yes." : "no."); 903 DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no."); 904 905 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 906 VMWGFX_REPO, VMWGFX_GIT_VERSION); 907 vmw_host_log(host_log); 908 909 memset(host_log, 0, sizeof(host_log)); 910 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 911 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 912 VMWGFX_DRIVER_PATCHLEVEL); 913 vmw_host_log(host_log); 914 915 if (dev_priv->enable_fb) { 916 vmw_fifo_resource_inc(dev_priv); 917 vmw_svga_enable(dev_priv); 918 vmw_fb_init(dev_priv); 919 } 920 921 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 922 register_pm_notifier(&dev_priv->pm_nb); 923 924 return 0; 925 926 out_no_fifo: 927 vmw_overlay_close(dev_priv); 928 vmw_kms_close(dev_priv); 929 out_no_kms: 930 if (dev_priv->has_mob) 931 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 932 if (dev_priv->has_gmr) 933 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 934 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 935 out_no_vram: 936 (void)ttm_bo_device_release(&dev_priv->bdev); 937 out_no_bdev: 938 vmw_fence_manager_takedown(dev_priv->fman); 939 out_no_fman: 940 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 941 vmw_irq_uninstall(dev_priv->dev); 942 out_no_irq: 943 if (dev_priv->stealth) 944 pci_release_region(dev->pdev, 2); 945 else 946 pci_release_regions(dev->pdev); 947 out_no_device: 948 ttm_object_device_release(&dev_priv->tdev); 949 out_err4: 950 memunmap(dev_priv->mmio_virt); 951 out_err0: 952 for (i = vmw_res_context; i < vmw_res_max; ++i) 953 idr_destroy(&dev_priv->res_idr[i]); 954 955 if (dev_priv->ctx.staged_bindings) 956 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 957 kfree(dev_priv); 958 return ret; 959 } 960 961 static void vmw_driver_unload(struct drm_device *dev) 962 { 963 struct vmw_private *dev_priv = vmw_priv(dev); 964 enum vmw_res_type i; 965 966 unregister_pm_notifier(&dev_priv->pm_nb); 967 968 if (dev_priv->ctx.res_ht_initialized) 969 drm_ht_remove(&dev_priv->ctx.res_ht); 970 vfree(dev_priv->ctx.cmd_bounce); 971 if (dev_priv->enable_fb) { 972 vmw_fb_off(dev_priv); 973 vmw_fb_close(dev_priv); 974 vmw_fifo_resource_dec(dev_priv); 975 vmw_svga_disable(dev_priv); 976 } 977 978 vmw_kms_close(dev_priv); 979 vmw_overlay_close(dev_priv); 980 981 if (dev_priv->has_gmr) 982 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 983 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 984 985 vmw_release_device_early(dev_priv); 986 if (dev_priv->has_mob) 987 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 988 (void) ttm_bo_device_release(&dev_priv->bdev); 989 vmw_release_device_late(dev_priv); 990 vmw_fence_manager_takedown(dev_priv->fman); 991 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 992 vmw_irq_uninstall(dev_priv->dev); 993 if (dev_priv->stealth) 994 pci_release_region(dev->pdev, 2); 995 else 996 pci_release_regions(dev->pdev); 997 998 ttm_object_device_release(&dev_priv->tdev); 999 memunmap(dev_priv->mmio_virt); 1000 if (dev_priv->ctx.staged_bindings) 1001 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1002 1003 for (i = vmw_res_context; i < vmw_res_max; ++i) 1004 idr_destroy(&dev_priv->res_idr[i]); 1005 1006 kfree(dev_priv); 1007 } 1008 1009 static void vmw_postclose(struct drm_device *dev, 1010 struct drm_file *file_priv) 1011 { 1012 struct vmw_fpriv *vmw_fp; 1013 1014 vmw_fp = vmw_fpriv(file_priv); 1015 1016 if (vmw_fp->locked_master) { 1017 struct vmw_master *vmaster = 1018 vmw_master(vmw_fp->locked_master); 1019 1020 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1021 ttm_vt_unlock(&vmaster->lock); 1022 drm_master_put(&vmw_fp->locked_master); 1023 } 1024 1025 ttm_object_file_release(&vmw_fp->tfile); 1026 kfree(vmw_fp); 1027 } 1028 1029 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1030 { 1031 struct vmw_private *dev_priv = vmw_priv(dev); 1032 struct vmw_fpriv *vmw_fp; 1033 int ret = -ENOMEM; 1034 1035 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1036 if (unlikely(!vmw_fp)) 1037 return ret; 1038 1039 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1040 if (unlikely(vmw_fp->tfile == NULL)) 1041 goto out_no_tfile; 1042 1043 file_priv->driver_priv = vmw_fp; 1044 1045 return 0; 1046 1047 out_no_tfile: 1048 kfree(vmw_fp); 1049 return ret; 1050 } 1051 1052 static struct vmw_master *vmw_master_check(struct drm_device *dev, 1053 struct drm_file *file_priv, 1054 unsigned int flags) 1055 { 1056 int ret; 1057 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1058 struct vmw_master *vmaster; 1059 1060 if (!drm_is_primary_client(file_priv) || !(flags & DRM_AUTH)) 1061 return NULL; 1062 1063 ret = mutex_lock_interruptible(&dev->master_mutex); 1064 if (unlikely(ret != 0)) 1065 return ERR_PTR(-ERESTARTSYS); 1066 1067 if (drm_is_current_master(file_priv)) { 1068 mutex_unlock(&dev->master_mutex); 1069 return NULL; 1070 } 1071 1072 /* 1073 * Check if we were previously master, but now dropped. In that 1074 * case, allow at least render node functionality. 1075 */ 1076 if (vmw_fp->locked_master) { 1077 mutex_unlock(&dev->master_mutex); 1078 1079 if (flags & DRM_RENDER_ALLOW) 1080 return NULL; 1081 1082 DRM_ERROR("Dropped master trying to access ioctl that " 1083 "requires authentication.\n"); 1084 return ERR_PTR(-EACCES); 1085 } 1086 mutex_unlock(&dev->master_mutex); 1087 1088 /* 1089 * Take the TTM lock. Possibly sleep waiting for the authenticating 1090 * master to become master again, or for a SIGTERM if the 1091 * authenticating master exits. 1092 */ 1093 vmaster = vmw_master(file_priv->master); 1094 ret = ttm_read_lock(&vmaster->lock, true); 1095 if (unlikely(ret != 0)) 1096 vmaster = ERR_PTR(ret); 1097 1098 return vmaster; 1099 } 1100 1101 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1102 unsigned long arg, 1103 long (*ioctl_func)(struct file *, unsigned int, 1104 unsigned long)) 1105 { 1106 struct drm_file *file_priv = filp->private_data; 1107 struct drm_device *dev = file_priv->minor->dev; 1108 unsigned int nr = DRM_IOCTL_NR(cmd); 1109 struct vmw_master *vmaster; 1110 unsigned int flags; 1111 long ret; 1112 1113 /* 1114 * Do extra checking on driver private ioctls. 1115 */ 1116 1117 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1118 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1119 const struct drm_ioctl_desc *ioctl = 1120 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1121 1122 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1123 return ioctl_func(filp, cmd, arg); 1124 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1125 if (!drm_is_current_master(file_priv) && 1126 !capable(CAP_SYS_ADMIN)) 1127 return -EACCES; 1128 } 1129 1130 if (unlikely(ioctl->cmd != cmd)) 1131 goto out_io_encoding; 1132 1133 flags = ioctl->flags; 1134 } else if (!drm_ioctl_flags(nr, &flags)) 1135 return -EINVAL; 1136 1137 vmaster = vmw_master_check(dev, file_priv, flags); 1138 if (IS_ERR(vmaster)) { 1139 ret = PTR_ERR(vmaster); 1140 1141 if (ret != -ERESTARTSYS) 1142 DRM_INFO("IOCTL ERROR Command %d, Error %ld.\n", 1143 nr, ret); 1144 return ret; 1145 } 1146 1147 ret = ioctl_func(filp, cmd, arg); 1148 if (vmaster) 1149 ttm_read_unlock(&vmaster->lock); 1150 1151 return ret; 1152 1153 out_io_encoding: 1154 DRM_ERROR("Invalid command format, ioctl %d\n", 1155 nr - DRM_COMMAND_BASE); 1156 1157 return -EINVAL; 1158 } 1159 1160 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1161 unsigned long arg) 1162 { 1163 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1164 } 1165 1166 #ifdef CONFIG_COMPAT 1167 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1168 unsigned long arg) 1169 { 1170 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1171 } 1172 #endif 1173 1174 static void vmw_master_init(struct vmw_master *vmaster) 1175 { 1176 ttm_lock_init(&vmaster->lock); 1177 } 1178 1179 static int vmw_master_create(struct drm_device *dev, 1180 struct drm_master *master) 1181 { 1182 struct vmw_master *vmaster; 1183 1184 vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL); 1185 if (unlikely(!vmaster)) 1186 return -ENOMEM; 1187 1188 vmw_master_init(vmaster); 1189 ttm_lock_set_kill(&vmaster->lock, true, SIGTERM); 1190 master->driver_priv = vmaster; 1191 1192 return 0; 1193 } 1194 1195 static void vmw_master_destroy(struct drm_device *dev, 1196 struct drm_master *master) 1197 { 1198 struct vmw_master *vmaster = vmw_master(master); 1199 1200 master->driver_priv = NULL; 1201 kfree(vmaster); 1202 } 1203 1204 static int vmw_master_set(struct drm_device *dev, 1205 struct drm_file *file_priv, 1206 bool from_open) 1207 { 1208 struct vmw_private *dev_priv = vmw_priv(dev); 1209 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1210 struct vmw_master *active = dev_priv->active_master; 1211 struct vmw_master *vmaster = vmw_master(file_priv->master); 1212 int ret = 0; 1213 1214 if (active) { 1215 BUG_ON(active != &dev_priv->fbdev_master); 1216 ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile); 1217 if (unlikely(ret != 0)) 1218 return ret; 1219 1220 ttm_lock_set_kill(&active->lock, true, SIGTERM); 1221 dev_priv->active_master = NULL; 1222 } 1223 1224 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1225 if (!from_open) { 1226 ttm_vt_unlock(&vmaster->lock); 1227 BUG_ON(vmw_fp->locked_master != file_priv->master); 1228 drm_master_put(&vmw_fp->locked_master); 1229 } 1230 1231 dev_priv->active_master = vmaster; 1232 1233 /* 1234 * Inform a new master that the layout may have changed while 1235 * it was gone. 1236 */ 1237 if (!from_open) 1238 drm_sysfs_hotplug_event(dev); 1239 1240 return 0; 1241 } 1242 1243 static void vmw_master_drop(struct drm_device *dev, 1244 struct drm_file *file_priv) 1245 { 1246 struct vmw_private *dev_priv = vmw_priv(dev); 1247 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1248 struct vmw_master *vmaster = vmw_master(file_priv->master); 1249 int ret; 1250 1251 /** 1252 * Make sure the master doesn't disappear while we have 1253 * it locked. 1254 */ 1255 1256 vmw_fp->locked_master = drm_master_get(file_priv->master); 1257 ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile); 1258 vmw_kms_legacy_hotspot_clear(dev_priv); 1259 if (unlikely((ret != 0))) { 1260 DRM_ERROR("Unable to lock TTM at VT switch.\n"); 1261 drm_master_put(&vmw_fp->locked_master); 1262 } 1263 1264 ttm_lock_set_kill(&vmaster->lock, false, SIGTERM); 1265 1266 if (!dev_priv->enable_fb) 1267 vmw_svga_disable(dev_priv); 1268 1269 dev_priv->active_master = &dev_priv->fbdev_master; 1270 ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM); 1271 ttm_vt_unlock(&dev_priv->fbdev_master.lock); 1272 } 1273 1274 /** 1275 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1276 * 1277 * @dev_priv: Pointer to device private struct. 1278 * Needs the reservation sem to be held in non-exclusive mode. 1279 */ 1280 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1281 { 1282 spin_lock(&dev_priv->svga_lock); 1283 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1284 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1285 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1286 } 1287 spin_unlock(&dev_priv->svga_lock); 1288 } 1289 1290 /** 1291 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1292 * 1293 * @dev_priv: Pointer to device private struct. 1294 */ 1295 void vmw_svga_enable(struct vmw_private *dev_priv) 1296 { 1297 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1298 __vmw_svga_enable(dev_priv); 1299 ttm_read_unlock(&dev_priv->reservation_sem); 1300 } 1301 1302 /** 1303 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1304 * 1305 * @dev_priv: Pointer to device private struct. 1306 * Needs the reservation sem to be held in exclusive mode. 1307 * Will not empty VRAM. VRAM must be emptied by caller. 1308 */ 1309 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1310 { 1311 spin_lock(&dev_priv->svga_lock); 1312 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1313 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1314 vmw_write(dev_priv, SVGA_REG_ENABLE, 1315 SVGA_REG_ENABLE_HIDE | 1316 SVGA_REG_ENABLE_ENABLE); 1317 } 1318 spin_unlock(&dev_priv->svga_lock); 1319 } 1320 1321 /** 1322 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1323 * running. 1324 * 1325 * @dev_priv: Pointer to device private struct. 1326 * Will empty VRAM. 1327 */ 1328 void vmw_svga_disable(struct vmw_private *dev_priv) 1329 { 1330 /* 1331 * Disabling SVGA will turn off device modesetting capabilities, so 1332 * notify KMS about that so that it doesn't cache atomic state that 1333 * isn't valid anymore, for example crtcs turned on. 1334 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1335 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1336 * end up with lock order reversal. Thus, a master may actually perform 1337 * a new modeset just after we call vmw_kms_lost_device() and race with 1338 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1339 * to be inconsistent with the device, causing modesetting problems. 1340 * 1341 */ 1342 vmw_kms_lost_device(dev_priv->dev); 1343 ttm_write_lock(&dev_priv->reservation_sem, false); 1344 spin_lock(&dev_priv->svga_lock); 1345 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1346 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1347 spin_unlock(&dev_priv->svga_lock); 1348 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1349 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1350 vmw_write(dev_priv, SVGA_REG_ENABLE, 1351 SVGA_REG_ENABLE_HIDE | 1352 SVGA_REG_ENABLE_ENABLE); 1353 } else 1354 spin_unlock(&dev_priv->svga_lock); 1355 ttm_write_unlock(&dev_priv->reservation_sem); 1356 } 1357 1358 static void vmw_remove(struct pci_dev *pdev) 1359 { 1360 struct drm_device *dev = pci_get_drvdata(pdev); 1361 1362 pci_disable_device(pdev); 1363 drm_put_dev(dev); 1364 } 1365 1366 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1367 void *ptr) 1368 { 1369 struct vmw_private *dev_priv = 1370 container_of(nb, struct vmw_private, pm_nb); 1371 1372 switch (val) { 1373 case PM_HIBERNATION_PREPARE: 1374 /* 1375 * Take the reservation sem in write mode, which will make sure 1376 * there are no other processes holding a buffer object 1377 * reservation, meaning we should be able to evict all buffer 1378 * objects if needed. 1379 * Once user-space processes have been frozen, we can release 1380 * the lock again. 1381 */ 1382 ttm_suspend_lock(&dev_priv->reservation_sem); 1383 dev_priv->suspend_locked = true; 1384 break; 1385 case PM_POST_HIBERNATION: 1386 case PM_POST_RESTORE: 1387 if (READ_ONCE(dev_priv->suspend_locked)) { 1388 dev_priv->suspend_locked = false; 1389 ttm_suspend_unlock(&dev_priv->reservation_sem); 1390 } 1391 break; 1392 default: 1393 break; 1394 } 1395 return 0; 1396 } 1397 1398 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1399 { 1400 struct drm_device *dev = pci_get_drvdata(pdev); 1401 struct vmw_private *dev_priv = vmw_priv(dev); 1402 1403 if (dev_priv->refuse_hibernation) 1404 return -EBUSY; 1405 1406 pci_save_state(pdev); 1407 pci_disable_device(pdev); 1408 pci_set_power_state(pdev, PCI_D3hot); 1409 return 0; 1410 } 1411 1412 static int vmw_pci_resume(struct pci_dev *pdev) 1413 { 1414 pci_set_power_state(pdev, PCI_D0); 1415 pci_restore_state(pdev); 1416 return pci_enable_device(pdev); 1417 } 1418 1419 static int vmw_pm_suspend(struct device *kdev) 1420 { 1421 struct pci_dev *pdev = to_pci_dev(kdev); 1422 struct pm_message dummy; 1423 1424 dummy.event = 0; 1425 1426 return vmw_pci_suspend(pdev, dummy); 1427 } 1428 1429 static int vmw_pm_resume(struct device *kdev) 1430 { 1431 struct pci_dev *pdev = to_pci_dev(kdev); 1432 1433 return vmw_pci_resume(pdev); 1434 } 1435 1436 static int vmw_pm_freeze(struct device *kdev) 1437 { 1438 struct pci_dev *pdev = to_pci_dev(kdev); 1439 struct drm_device *dev = pci_get_drvdata(pdev); 1440 struct vmw_private *dev_priv = vmw_priv(dev); 1441 int ret; 1442 1443 /* 1444 * Unlock for vmw_kms_suspend. 1445 * No user-space processes should be running now. 1446 */ 1447 ttm_suspend_unlock(&dev_priv->reservation_sem); 1448 ret = vmw_kms_suspend(dev_priv->dev); 1449 if (ret) { 1450 ttm_suspend_lock(&dev_priv->reservation_sem); 1451 DRM_ERROR("Failed to freeze modesetting.\n"); 1452 return ret; 1453 } 1454 if (dev_priv->enable_fb) 1455 vmw_fb_off(dev_priv); 1456 1457 ttm_suspend_lock(&dev_priv->reservation_sem); 1458 vmw_execbuf_release_pinned_bo(dev_priv); 1459 vmw_resource_evict_all(dev_priv); 1460 vmw_release_device_early(dev_priv); 1461 ttm_bo_swapout_all(&dev_priv->bdev); 1462 if (dev_priv->enable_fb) 1463 vmw_fifo_resource_dec(dev_priv); 1464 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1465 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1466 if (dev_priv->enable_fb) 1467 vmw_fifo_resource_inc(dev_priv); 1468 WARN_ON(vmw_request_device_late(dev_priv)); 1469 dev_priv->suspend_locked = false; 1470 ttm_suspend_unlock(&dev_priv->reservation_sem); 1471 if (dev_priv->suspend_state) 1472 vmw_kms_resume(dev); 1473 if (dev_priv->enable_fb) 1474 vmw_fb_on(dev_priv); 1475 return -EBUSY; 1476 } 1477 1478 vmw_fence_fifo_down(dev_priv->fman); 1479 __vmw_svga_disable(dev_priv); 1480 1481 vmw_release_device_late(dev_priv); 1482 return 0; 1483 } 1484 1485 static int vmw_pm_restore(struct device *kdev) 1486 { 1487 struct pci_dev *pdev = to_pci_dev(kdev); 1488 struct drm_device *dev = pci_get_drvdata(pdev); 1489 struct vmw_private *dev_priv = vmw_priv(dev); 1490 int ret; 1491 1492 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1493 (void) vmw_read(dev_priv, SVGA_REG_ID); 1494 1495 if (dev_priv->enable_fb) 1496 vmw_fifo_resource_inc(dev_priv); 1497 1498 ret = vmw_request_device(dev_priv); 1499 if (ret) 1500 return ret; 1501 1502 if (dev_priv->enable_fb) 1503 __vmw_svga_enable(dev_priv); 1504 1505 vmw_fence_fifo_up(dev_priv->fman); 1506 dev_priv->suspend_locked = false; 1507 ttm_suspend_unlock(&dev_priv->reservation_sem); 1508 if (dev_priv->suspend_state) 1509 vmw_kms_resume(dev_priv->dev); 1510 1511 if (dev_priv->enable_fb) 1512 vmw_fb_on(dev_priv); 1513 1514 return 0; 1515 } 1516 1517 static const struct dev_pm_ops vmw_pm_ops = { 1518 .freeze = vmw_pm_freeze, 1519 .thaw = vmw_pm_restore, 1520 .restore = vmw_pm_restore, 1521 .suspend = vmw_pm_suspend, 1522 .resume = vmw_pm_resume, 1523 }; 1524 1525 static const struct file_operations vmwgfx_driver_fops = { 1526 .owner = THIS_MODULE, 1527 .open = drm_open, 1528 .release = drm_release, 1529 .unlocked_ioctl = vmw_unlocked_ioctl, 1530 .mmap = vmw_mmap, 1531 .poll = vmw_fops_poll, 1532 .read = vmw_fops_read, 1533 #if defined(CONFIG_COMPAT) 1534 .compat_ioctl = vmw_compat_ioctl, 1535 #endif 1536 .llseek = noop_llseek, 1537 }; 1538 1539 static struct drm_driver driver = { 1540 .driver_features = 1541 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC, 1542 .load = vmw_driver_load, 1543 .unload = vmw_driver_unload, 1544 .get_vblank_counter = vmw_get_vblank_counter, 1545 .enable_vblank = vmw_enable_vblank, 1546 .disable_vblank = vmw_disable_vblank, 1547 .ioctls = vmw_ioctls, 1548 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1549 .master_create = vmw_master_create, 1550 .master_destroy = vmw_master_destroy, 1551 .master_set = vmw_master_set, 1552 .master_drop = vmw_master_drop, 1553 .open = vmw_driver_open, 1554 .postclose = vmw_postclose, 1555 1556 .dumb_create = vmw_dumb_create, 1557 .dumb_map_offset = vmw_dumb_map_offset, 1558 .dumb_destroy = vmw_dumb_destroy, 1559 1560 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1561 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1562 1563 .fops = &vmwgfx_driver_fops, 1564 .name = VMWGFX_DRIVER_NAME, 1565 .desc = VMWGFX_DRIVER_DESC, 1566 .date = VMWGFX_DRIVER_DATE, 1567 .major = VMWGFX_DRIVER_MAJOR, 1568 .minor = VMWGFX_DRIVER_MINOR, 1569 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1570 }; 1571 1572 static struct pci_driver vmw_pci_driver = { 1573 .name = VMWGFX_DRIVER_NAME, 1574 .id_table = vmw_pci_id_list, 1575 .probe = vmw_probe, 1576 .remove = vmw_remove, 1577 .driver = { 1578 .pm = &vmw_pm_ops 1579 } 1580 }; 1581 1582 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1583 { 1584 return drm_get_pci_dev(pdev, ent, &driver); 1585 } 1586 1587 static int __init vmwgfx_init(void) 1588 { 1589 int ret; 1590 1591 if (vgacon_text_force()) 1592 return -EINVAL; 1593 1594 ret = pci_register_driver(&vmw_pci_driver); 1595 if (ret) 1596 DRM_ERROR("Failed initializing DRM.\n"); 1597 return ret; 1598 } 1599 1600 static void __exit vmwgfx_exit(void) 1601 { 1602 pci_unregister_driver(&vmw_pci_driver); 1603 } 1604 1605 module_init(vmwgfx_init); 1606 module_exit(vmwgfx_exit); 1607 1608 MODULE_AUTHOR("VMware Inc. and others"); 1609 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1610 MODULE_LICENSE("GPL and additional rights"); 1611 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1612 __stringify(VMWGFX_DRIVER_MINOR) "." 1613 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1614 "0"); 1615