1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 #include <linux/module.h> 28 #include <linux/console.h> 29 #include <linux/dma-mapping.h> 30 31 #include <drm/drmP.h> 32 #include "vmwgfx_drv.h" 33 #include "vmwgfx_binding.h" 34 #include "ttm_object.h" 35 #include <drm/ttm/ttm_placement.h> 36 #include <drm/ttm/ttm_bo_driver.h> 37 #include <drm/ttm/ttm_module.h> 38 39 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 40 #define VMWGFX_CHIP_SVGAII 0 41 #define VMW_FB_RESERVATION 0 42 43 #define VMW_MIN_INITIAL_WIDTH 800 44 #define VMW_MIN_INITIAL_HEIGHT 600 45 46 #ifndef VMWGFX_GIT_VERSION 47 #define VMWGFX_GIT_VERSION "Unknown" 48 #endif 49 50 #define VMWGFX_REPO "In Tree" 51 52 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 53 54 55 /** 56 * Fully encoded drm commands. Might move to vmw_drm.h 57 */ 58 59 #define DRM_IOCTL_VMW_GET_PARAM \ 60 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 61 struct drm_vmw_getparam_arg) 62 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 63 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 64 union drm_vmw_alloc_dmabuf_arg) 65 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 66 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 67 struct drm_vmw_unref_dmabuf_arg) 68 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 69 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 70 struct drm_vmw_cursor_bypass_arg) 71 72 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 73 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 74 struct drm_vmw_control_stream_arg) 75 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 76 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 77 struct drm_vmw_stream_arg) 78 #define DRM_IOCTL_VMW_UNREF_STREAM \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 80 struct drm_vmw_stream_arg) 81 82 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 83 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 84 struct drm_vmw_context_arg) 85 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 86 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 87 struct drm_vmw_context_arg) 88 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 89 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 90 union drm_vmw_surface_create_arg) 91 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 93 struct drm_vmw_surface_arg) 94 #define DRM_IOCTL_VMW_REF_SURFACE \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 96 union drm_vmw_surface_reference_arg) 97 #define DRM_IOCTL_VMW_EXECBUF \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 99 struct drm_vmw_execbuf_arg) 100 #define DRM_IOCTL_VMW_GET_3D_CAP \ 101 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 102 struct drm_vmw_get_3d_cap_arg) 103 #define DRM_IOCTL_VMW_FENCE_WAIT \ 104 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 105 struct drm_vmw_fence_wait_arg) 106 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 107 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 108 struct drm_vmw_fence_signaled_arg) 109 #define DRM_IOCTL_VMW_FENCE_UNREF \ 110 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 111 struct drm_vmw_fence_arg) 112 #define DRM_IOCTL_VMW_FENCE_EVENT \ 113 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 114 struct drm_vmw_fence_event_arg) 115 #define DRM_IOCTL_VMW_PRESENT \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 117 struct drm_vmw_present_arg) 118 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 120 struct drm_vmw_present_readback_arg) 121 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 123 struct drm_vmw_update_layout_arg) 124 #define DRM_IOCTL_VMW_CREATE_SHADER \ 125 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 126 struct drm_vmw_shader_create_arg) 127 #define DRM_IOCTL_VMW_UNREF_SHADER \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 129 struct drm_vmw_shader_arg) 130 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 132 union drm_vmw_gb_surface_create_arg) 133 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 134 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 135 union drm_vmw_gb_surface_reference_arg) 136 #define DRM_IOCTL_VMW_SYNCCPU \ 137 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 138 struct drm_vmw_synccpu_arg) 139 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 141 struct drm_vmw_context_arg) 142 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 143 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 144 union drm_vmw_gb_surface_create_ext_arg) 145 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 147 union drm_vmw_gb_surface_reference_ext_arg) 148 149 /** 150 * The core DRM version of this macro doesn't account for 151 * DRM_COMMAND_BASE. 152 */ 153 154 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 155 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 156 157 /** 158 * Ioctl definitions. 159 */ 160 161 static const struct drm_ioctl_desc vmw_ioctls[] = { 162 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 163 DRM_AUTH | DRM_RENDER_ALLOW), 164 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 165 DRM_AUTH | DRM_RENDER_ALLOW), 166 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 167 DRM_RENDER_ALLOW), 168 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 169 vmw_kms_cursor_bypass_ioctl, 170 DRM_MASTER), 171 172 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 173 DRM_MASTER), 174 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 175 DRM_MASTER), 176 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 177 DRM_MASTER), 178 179 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 180 DRM_AUTH | DRM_RENDER_ALLOW), 181 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 182 DRM_RENDER_ALLOW), 183 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 184 DRM_AUTH | DRM_RENDER_ALLOW), 185 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 186 DRM_RENDER_ALLOW), 187 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 188 DRM_AUTH | DRM_RENDER_ALLOW), 189 VMW_IOCTL_DEF(VMW_EXECBUF, NULL, DRM_AUTH | 190 DRM_RENDER_ALLOW), 191 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 192 DRM_RENDER_ALLOW), 193 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 194 vmw_fence_obj_signaled_ioctl, 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 197 DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 199 DRM_AUTH | DRM_RENDER_ALLOW), 200 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 201 DRM_AUTH | DRM_RENDER_ALLOW), 202 203 /* these allow direct access to the framebuffers mark as master only */ 204 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 205 DRM_MASTER | DRM_AUTH), 206 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 207 vmw_present_readback_ioctl, 208 DRM_MASTER | DRM_AUTH), 209 /* 210 * The permissions of the below ioctl are overridden in 211 * vmw_generic_ioctl(). We require either 212 * DRM_MASTER or capable(CAP_SYS_ADMIN). 213 */ 214 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 215 vmw_kms_update_layout_ioctl, 216 DRM_RENDER_ALLOW), 217 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 218 vmw_shader_define_ioctl, 219 DRM_AUTH | DRM_RENDER_ALLOW), 220 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 221 vmw_shader_destroy_ioctl, 222 DRM_RENDER_ALLOW), 223 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 224 vmw_gb_surface_define_ioctl, 225 DRM_AUTH | DRM_RENDER_ALLOW), 226 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 227 vmw_gb_surface_reference_ioctl, 228 DRM_AUTH | DRM_RENDER_ALLOW), 229 VMW_IOCTL_DEF(VMW_SYNCCPU, 230 vmw_user_bo_synccpu_ioctl, 231 DRM_RENDER_ALLOW), 232 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 233 vmw_extended_context_define_ioctl, 234 DRM_AUTH | DRM_RENDER_ALLOW), 235 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 236 vmw_gb_surface_define_ext_ioctl, 237 DRM_AUTH | DRM_RENDER_ALLOW), 238 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 239 vmw_gb_surface_reference_ext_ioctl, 240 DRM_AUTH | DRM_RENDER_ALLOW), 241 }; 242 243 static const struct pci_device_id vmw_pci_id_list[] = { 244 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 245 {0, 0, 0} 246 }; 247 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 248 249 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 250 static int vmw_force_iommu; 251 static int vmw_restrict_iommu; 252 static int vmw_force_coherent; 253 static int vmw_restrict_dma_mask; 254 static int vmw_assume_16bpp; 255 256 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 257 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 258 void *ptr); 259 260 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 261 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 262 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 263 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 264 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 265 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 266 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 267 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 268 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 269 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 270 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 271 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 272 273 274 static void vmw_print_capabilities2(uint32_t capabilities2) 275 { 276 DRM_INFO("Capabilities2:\n"); 277 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 278 DRM_INFO(" Grow oTable.\n"); 279 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 280 DRM_INFO(" IntraSurface copy.\n"); 281 } 282 283 static void vmw_print_capabilities(uint32_t capabilities) 284 { 285 DRM_INFO("Capabilities:\n"); 286 if (capabilities & SVGA_CAP_RECT_COPY) 287 DRM_INFO(" Rect copy.\n"); 288 if (capabilities & SVGA_CAP_CURSOR) 289 DRM_INFO(" Cursor.\n"); 290 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 291 DRM_INFO(" Cursor bypass.\n"); 292 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 293 DRM_INFO(" Cursor bypass 2.\n"); 294 if (capabilities & SVGA_CAP_8BIT_EMULATION) 295 DRM_INFO(" 8bit emulation.\n"); 296 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 297 DRM_INFO(" Alpha cursor.\n"); 298 if (capabilities & SVGA_CAP_3D) 299 DRM_INFO(" 3D.\n"); 300 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 301 DRM_INFO(" Extended Fifo.\n"); 302 if (capabilities & SVGA_CAP_MULTIMON) 303 DRM_INFO(" Multimon.\n"); 304 if (capabilities & SVGA_CAP_PITCHLOCK) 305 DRM_INFO(" Pitchlock.\n"); 306 if (capabilities & SVGA_CAP_IRQMASK) 307 DRM_INFO(" Irq mask.\n"); 308 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 309 DRM_INFO(" Display Topology.\n"); 310 if (capabilities & SVGA_CAP_GMR) 311 DRM_INFO(" GMR.\n"); 312 if (capabilities & SVGA_CAP_TRACES) 313 DRM_INFO(" Traces.\n"); 314 if (capabilities & SVGA_CAP_GMR2) 315 DRM_INFO(" GMR2.\n"); 316 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 317 DRM_INFO(" Screen Object 2.\n"); 318 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 319 DRM_INFO(" Command Buffers.\n"); 320 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 321 DRM_INFO(" Command Buffers 2.\n"); 322 if (capabilities & SVGA_CAP_GBOBJECTS) 323 DRM_INFO(" Guest Backed Resources.\n"); 324 if (capabilities & SVGA_CAP_DX) 325 DRM_INFO(" DX Features.\n"); 326 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 327 DRM_INFO(" HP Command Queue.\n"); 328 } 329 330 /** 331 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 332 * 333 * @dev_priv: A device private structure. 334 * 335 * This function creates a small buffer object that holds the query 336 * result for dummy queries emitted as query barriers. 337 * The function will then map the first page and initialize a pending 338 * occlusion query result structure, Finally it will unmap the buffer. 339 * No interruptible waits are done within this function. 340 * 341 * Returns an error if bo creation or initialization fails. 342 */ 343 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 344 { 345 int ret; 346 struct vmw_buffer_object *vbo; 347 struct ttm_bo_kmap_obj map; 348 volatile SVGA3dQueryResult *result; 349 bool dummy; 350 351 /* 352 * Create the vbo as pinned, so that a tryreserve will 353 * immediately succeed. This is because we're the only 354 * user of the bo currently. 355 */ 356 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 357 if (!vbo) 358 return -ENOMEM; 359 360 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 361 &vmw_sys_ne_placement, false, 362 &vmw_bo_bo_free); 363 if (unlikely(ret != 0)) 364 return ret; 365 366 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 367 BUG_ON(ret != 0); 368 vmw_bo_pin_reserved(vbo, true); 369 370 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 371 if (likely(ret == 0)) { 372 result = ttm_kmap_obj_virtual(&map, &dummy); 373 result->totalSize = sizeof(*result); 374 result->state = SVGA3D_QUERYSTATE_PENDING; 375 result->result32 = 0xff; 376 ttm_bo_kunmap(&map); 377 } 378 vmw_bo_pin_reserved(vbo, false); 379 ttm_bo_unreserve(&vbo->base); 380 381 if (unlikely(ret != 0)) { 382 DRM_ERROR("Dummy query buffer map failed.\n"); 383 vmw_bo_unreference(&vbo); 384 } else 385 dev_priv->dummy_query_bo = vbo; 386 387 return ret; 388 } 389 390 /** 391 * vmw_request_device_late - Perform late device setup 392 * 393 * @dev_priv: Pointer to device private. 394 * 395 * This function performs setup of otables and enables large command 396 * buffer submission. These tasks are split out to a separate function 397 * because it reverts vmw_release_device_early and is intended to be used 398 * by an error path in the hibernation code. 399 */ 400 static int vmw_request_device_late(struct vmw_private *dev_priv) 401 { 402 int ret; 403 404 if (dev_priv->has_mob) { 405 ret = vmw_otables_setup(dev_priv); 406 if (unlikely(ret != 0)) { 407 DRM_ERROR("Unable to initialize " 408 "guest Memory OBjects.\n"); 409 return ret; 410 } 411 } 412 413 if (dev_priv->cman) { 414 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 415 256*4096, 2*4096); 416 if (ret) { 417 struct vmw_cmdbuf_man *man = dev_priv->cman; 418 419 dev_priv->cman = NULL; 420 vmw_cmdbuf_man_destroy(man); 421 } 422 } 423 424 return 0; 425 } 426 427 static int vmw_request_device(struct vmw_private *dev_priv) 428 { 429 int ret; 430 431 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 432 if (unlikely(ret != 0)) { 433 DRM_ERROR("Unable to initialize FIFO.\n"); 434 return ret; 435 } 436 vmw_fence_fifo_up(dev_priv->fman); 437 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 438 if (IS_ERR(dev_priv->cman)) { 439 dev_priv->cman = NULL; 440 dev_priv->has_dx = false; 441 } 442 443 ret = vmw_request_device_late(dev_priv); 444 if (ret) 445 goto out_no_mob; 446 447 ret = vmw_dummy_query_bo_create(dev_priv); 448 if (unlikely(ret != 0)) 449 goto out_no_query_bo; 450 451 return 0; 452 453 out_no_query_bo: 454 if (dev_priv->cman) 455 vmw_cmdbuf_remove_pool(dev_priv->cman); 456 if (dev_priv->has_mob) { 457 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 458 vmw_otables_takedown(dev_priv); 459 } 460 if (dev_priv->cman) 461 vmw_cmdbuf_man_destroy(dev_priv->cman); 462 out_no_mob: 463 vmw_fence_fifo_down(dev_priv->fman); 464 vmw_fifo_release(dev_priv, &dev_priv->fifo); 465 return ret; 466 } 467 468 /** 469 * vmw_release_device_early - Early part of fifo takedown. 470 * 471 * @dev_priv: Pointer to device private struct. 472 * 473 * This is the first part of command submission takedown, to be called before 474 * buffer management is taken down. 475 */ 476 static void vmw_release_device_early(struct vmw_private *dev_priv) 477 { 478 /* 479 * Previous destructions should've released 480 * the pinned bo. 481 */ 482 483 BUG_ON(dev_priv->pinned_bo != NULL); 484 485 vmw_bo_unreference(&dev_priv->dummy_query_bo); 486 if (dev_priv->cman) 487 vmw_cmdbuf_remove_pool(dev_priv->cman); 488 489 if (dev_priv->has_mob) { 490 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 491 vmw_otables_takedown(dev_priv); 492 } 493 } 494 495 /** 496 * vmw_release_device_late - Late part of fifo takedown. 497 * 498 * @dev_priv: Pointer to device private struct. 499 * 500 * This is the last part of the command submission takedown, to be called when 501 * command submission is no longer needed. It may wait on pending fences. 502 */ 503 static void vmw_release_device_late(struct vmw_private *dev_priv) 504 { 505 vmw_fence_fifo_down(dev_priv->fman); 506 if (dev_priv->cman) 507 vmw_cmdbuf_man_destroy(dev_priv->cman); 508 509 vmw_fifo_release(dev_priv, &dev_priv->fifo); 510 } 511 512 /** 513 * Sets the initial_[width|height] fields on the given vmw_private. 514 * 515 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 516 * clamping the value to fb_max_[width|height] fields and the 517 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 518 * If the values appear to be invalid, set them to 519 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 520 */ 521 static void vmw_get_initial_size(struct vmw_private *dev_priv) 522 { 523 uint32_t width; 524 uint32_t height; 525 526 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 527 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 528 529 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 530 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 531 532 if (width > dev_priv->fb_max_width || 533 height > dev_priv->fb_max_height) { 534 535 /* 536 * This is a host error and shouldn't occur. 537 */ 538 539 width = VMW_MIN_INITIAL_WIDTH; 540 height = VMW_MIN_INITIAL_HEIGHT; 541 } 542 543 dev_priv->initial_width = width; 544 dev_priv->initial_height = height; 545 } 546 547 /** 548 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 549 * system. 550 * 551 * @dev_priv: Pointer to a struct vmw_private 552 * 553 * This functions tries to determine what actions need to be taken by the 554 * driver to make system pages visible to the device. 555 * If this function decides that DMA is not possible, it returns -EINVAL. 556 * The driver may then try to disable features of the device that require 557 * DMA. 558 */ 559 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 560 { 561 static const char *names[vmw_dma_map_max] = { 562 [vmw_dma_phys] = "Using physical TTM page addresses.", 563 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 564 [vmw_dma_map_populate] = "Caching DMA mappings.", 565 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 566 567 if (vmw_force_coherent) 568 dev_priv->map_mode = vmw_dma_alloc_coherent; 569 else if (vmw_restrict_iommu) 570 dev_priv->map_mode = vmw_dma_map_bind; 571 else 572 dev_priv->map_mode = vmw_dma_map_populate; 573 574 /* No TTM coherent page pool? FIXME: Ask TTM instead! */ 575 if (!(IS_ENABLED(CONFIG_SWIOTLB) || IS_ENABLED(CONFIG_INTEL_IOMMU)) && 576 (dev_priv->map_mode == vmw_dma_alloc_coherent)) 577 return -EINVAL; 578 579 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 580 return 0; 581 } 582 583 /** 584 * vmw_dma_masks - set required page- and dma masks 585 * 586 * @dev: Pointer to struct drm-device 587 * 588 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 589 * restriction also for 64-bit systems. 590 */ 591 static int vmw_dma_masks(struct vmw_private *dev_priv) 592 { 593 struct drm_device *dev = dev_priv->dev; 594 int ret = 0; 595 596 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 597 if (dev_priv->map_mode != vmw_dma_phys && 598 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 599 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 600 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 601 } 602 603 return ret; 604 } 605 606 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 607 { 608 struct vmw_private *dev_priv; 609 int ret; 610 uint32_t svga_id; 611 enum vmw_res_type i; 612 bool refuse_dma = false; 613 char host_log[100] = {0}; 614 615 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 616 if (unlikely(!dev_priv)) { 617 DRM_ERROR("Failed allocating a device private struct.\n"); 618 return -ENOMEM; 619 } 620 621 pci_set_master(dev->pdev); 622 623 dev_priv->dev = dev; 624 dev_priv->vmw_chipset = chipset; 625 dev_priv->last_read_seqno = (uint32_t) -100; 626 mutex_init(&dev_priv->cmdbuf_mutex); 627 mutex_init(&dev_priv->release_mutex); 628 mutex_init(&dev_priv->binding_mutex); 629 mutex_init(&dev_priv->global_kms_state_mutex); 630 ttm_lock_init(&dev_priv->reservation_sem); 631 spin_lock_init(&dev_priv->resource_lock); 632 spin_lock_init(&dev_priv->hw_lock); 633 spin_lock_init(&dev_priv->waiter_lock); 634 spin_lock_init(&dev_priv->cap_lock); 635 spin_lock_init(&dev_priv->svga_lock); 636 spin_lock_init(&dev_priv->cursor_lock); 637 638 for (i = vmw_res_context; i < vmw_res_max; ++i) { 639 idr_init(&dev_priv->res_idr[i]); 640 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 641 } 642 643 mutex_init(&dev_priv->init_mutex); 644 init_waitqueue_head(&dev_priv->fence_queue); 645 init_waitqueue_head(&dev_priv->fifo_queue); 646 dev_priv->fence_queue_waiters = 0; 647 dev_priv->fifo_queue_waiters = 0; 648 649 dev_priv->used_memory_size = 0; 650 651 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 652 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 653 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 654 655 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 656 657 dev_priv->enable_fb = enable_fbdev; 658 659 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 660 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 661 if (svga_id != SVGA_ID_2) { 662 ret = -ENOSYS; 663 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 664 goto out_err0; 665 } 666 667 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 668 669 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 670 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 671 } 672 673 674 ret = vmw_dma_select_mode(dev_priv); 675 if (unlikely(ret != 0)) { 676 DRM_INFO("Restricting capabilities due to IOMMU setup.\n"); 677 refuse_dma = true; 678 } 679 680 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 681 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 682 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 683 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 684 685 vmw_get_initial_size(dev_priv); 686 687 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 688 dev_priv->max_gmr_ids = 689 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 690 dev_priv->max_gmr_pages = 691 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 692 dev_priv->memory_size = 693 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 694 dev_priv->memory_size -= dev_priv->vram_size; 695 } else { 696 /* 697 * An arbitrary limit of 512MiB on surface 698 * memory. But all HWV8 hardware supports GMR2. 699 */ 700 dev_priv->memory_size = 512*1024*1024; 701 } 702 dev_priv->max_mob_pages = 0; 703 dev_priv->max_mob_size = 0; 704 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 705 uint64_t mem_size = 706 vmw_read(dev_priv, 707 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 708 709 /* 710 * Workaround for low memory 2D VMs to compensate for the 711 * allocation taken by fbdev 712 */ 713 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 714 mem_size *= 3; 715 716 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 717 dev_priv->prim_bb_mem = 718 vmw_read(dev_priv, 719 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 720 dev_priv->max_mob_size = 721 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 722 dev_priv->stdu_max_width = 723 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 724 dev_priv->stdu_max_height = 725 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 726 727 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 728 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 729 dev_priv->texture_max_width = vmw_read(dev_priv, 730 SVGA_REG_DEV_CAP); 731 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 732 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 733 dev_priv->texture_max_height = vmw_read(dev_priv, 734 SVGA_REG_DEV_CAP); 735 } else { 736 dev_priv->texture_max_width = 8192; 737 dev_priv->texture_max_height = 8192; 738 dev_priv->prim_bb_mem = dev_priv->vram_size; 739 } 740 741 vmw_print_capabilities(dev_priv->capabilities); 742 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 743 vmw_print_capabilities2(dev_priv->capabilities2); 744 745 ret = vmw_dma_masks(dev_priv); 746 if (unlikely(ret != 0)) 747 goto out_err0; 748 749 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 750 DRM_INFO("Max GMR ids is %u\n", 751 (unsigned)dev_priv->max_gmr_ids); 752 DRM_INFO("Max number of GMR pages is %u\n", 753 (unsigned)dev_priv->max_gmr_pages); 754 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 755 (unsigned)dev_priv->memory_size / 1024); 756 } 757 DRM_INFO("Maximum display memory size is %u kiB\n", 758 dev_priv->prim_bb_mem / 1024); 759 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 760 dev_priv->vram_start, dev_priv->vram_size / 1024); 761 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 762 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 763 764 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 765 dev_priv->mmio_size, MEMREMAP_WB); 766 767 if (unlikely(dev_priv->mmio_virt == NULL)) { 768 ret = -ENOMEM; 769 DRM_ERROR("Failed mapping MMIO.\n"); 770 goto out_err0; 771 } 772 773 /* Need mmio memory to check for fifo pitchlock cap. */ 774 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 775 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 776 !vmw_fifo_have_pitchlock(dev_priv)) { 777 ret = -ENOSYS; 778 DRM_ERROR("Hardware has no pitchlock\n"); 779 goto out_err4; 780 } 781 782 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 783 &vmw_prime_dmabuf_ops); 784 785 if (unlikely(dev_priv->tdev == NULL)) { 786 DRM_ERROR("Unable to initialize TTM object management.\n"); 787 ret = -ENOMEM; 788 goto out_err4; 789 } 790 791 dev->dev_private = dev_priv; 792 793 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 794 dev_priv->stealth = (ret != 0); 795 if (dev_priv->stealth) { 796 /** 797 * Request at least the mmio PCI resource. 798 */ 799 800 DRM_INFO("It appears like vesafb is loaded. " 801 "Ignore above error if any.\n"); 802 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 803 if (unlikely(ret != 0)) { 804 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 805 goto out_no_device; 806 } 807 } 808 809 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 810 ret = vmw_irq_install(dev, dev->pdev->irq); 811 if (ret != 0) { 812 DRM_ERROR("Failed installing irq: %d\n", ret); 813 goto out_no_irq; 814 } 815 } 816 817 dev_priv->fman = vmw_fence_manager_init(dev_priv); 818 if (unlikely(dev_priv->fman == NULL)) { 819 ret = -ENOMEM; 820 goto out_no_fman; 821 } 822 823 ret = ttm_bo_device_init(&dev_priv->bdev, 824 &vmw_bo_driver, 825 dev->anon_inode->i_mapping, 826 false); 827 if (unlikely(ret != 0)) { 828 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 829 goto out_no_bdev; 830 } 831 dev_priv->vm_ops = *dev_priv->bdev.vm_ops; 832 dev_priv->vm_ops.fault = vmw_bo_vm_fault; 833 dev_priv->vm_ops.pfn_mkwrite = vmw_bo_vm_mkwrite; 834 dev_priv->vm_ops.page_mkwrite = vmw_bo_vm_mkwrite; 835 dev_priv->bdev.vm_ops = &dev_priv->vm_ops; 836 837 /* 838 * Enable VRAM, but initially don't use it until SVGA is enabled and 839 * unhidden. 840 */ 841 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 842 (dev_priv->vram_size >> PAGE_SHIFT)); 843 if (unlikely(ret != 0)) { 844 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 845 goto out_no_vram; 846 } 847 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 848 849 dev_priv->has_gmr = true; 850 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 851 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 852 VMW_PL_GMR) != 0) { 853 DRM_INFO("No GMR memory available. " 854 "Graphics memory resources are very limited.\n"); 855 dev_priv->has_gmr = false; 856 } 857 858 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 859 dev_priv->has_mob = true; 860 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 861 VMW_PL_MOB) != 0) { 862 DRM_INFO("No MOB memory available. " 863 "3D will be disabled.\n"); 864 dev_priv->has_mob = false; 865 } 866 } 867 868 if (dev_priv->has_mob) { 869 spin_lock(&dev_priv->cap_lock); 870 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 871 dev_priv->has_dx = !!vmw_read(dev_priv, SVGA_REG_DEV_CAP); 872 spin_unlock(&dev_priv->cap_lock); 873 } 874 875 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 876 ret = vmw_kms_init(dev_priv); 877 if (unlikely(ret != 0)) 878 goto out_no_kms; 879 vmw_overlay_init(dev_priv); 880 881 ret = vmw_request_device(dev_priv); 882 if (ret) 883 goto out_no_fifo; 884 885 if (dev_priv->has_dx) { 886 /* 887 * SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 888 * support 889 */ 890 if ((dev_priv->capabilities2 & SVGA_CAP2_DX2) != 0) { 891 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 892 SVGA3D_DEVCAP_SM41); 893 dev_priv->has_sm4_1 = vmw_read(dev_priv, 894 SVGA_REG_DEV_CAP); 895 } 896 } 897 898 DRM_INFO("DX: %s\n", dev_priv->has_dx ? "yes." : "no."); 899 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 900 ? "yes." : "no."); 901 DRM_INFO("SM4_1: %s\n", dev_priv->has_sm4_1 ? "yes." : "no."); 902 903 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 904 VMWGFX_REPO, VMWGFX_GIT_VERSION); 905 vmw_host_log(host_log); 906 907 memset(host_log, 0, sizeof(host_log)); 908 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 909 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 910 VMWGFX_DRIVER_PATCHLEVEL); 911 vmw_host_log(host_log); 912 913 if (dev_priv->enable_fb) { 914 vmw_fifo_resource_inc(dev_priv); 915 vmw_svga_enable(dev_priv); 916 vmw_fb_init(dev_priv); 917 } 918 919 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 920 register_pm_notifier(&dev_priv->pm_nb); 921 922 return 0; 923 924 out_no_fifo: 925 vmw_overlay_close(dev_priv); 926 vmw_kms_close(dev_priv); 927 out_no_kms: 928 if (dev_priv->has_mob) 929 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 930 if (dev_priv->has_gmr) 931 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 932 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 933 out_no_vram: 934 (void)ttm_bo_device_release(&dev_priv->bdev); 935 out_no_bdev: 936 vmw_fence_manager_takedown(dev_priv->fman); 937 out_no_fman: 938 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 939 vmw_irq_uninstall(dev_priv->dev); 940 out_no_irq: 941 if (dev_priv->stealth) 942 pci_release_region(dev->pdev, 2); 943 else 944 pci_release_regions(dev->pdev); 945 out_no_device: 946 ttm_object_device_release(&dev_priv->tdev); 947 out_err4: 948 memunmap(dev_priv->mmio_virt); 949 out_err0: 950 for (i = vmw_res_context; i < vmw_res_max; ++i) 951 idr_destroy(&dev_priv->res_idr[i]); 952 953 if (dev_priv->ctx.staged_bindings) 954 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 955 kfree(dev_priv); 956 return ret; 957 } 958 959 static void vmw_driver_unload(struct drm_device *dev) 960 { 961 struct vmw_private *dev_priv = vmw_priv(dev); 962 enum vmw_res_type i; 963 964 unregister_pm_notifier(&dev_priv->pm_nb); 965 966 if (dev_priv->ctx.res_ht_initialized) 967 drm_ht_remove(&dev_priv->ctx.res_ht); 968 vfree(dev_priv->ctx.cmd_bounce); 969 if (dev_priv->enable_fb) { 970 vmw_fb_off(dev_priv); 971 vmw_fb_close(dev_priv); 972 vmw_fifo_resource_dec(dev_priv); 973 vmw_svga_disable(dev_priv); 974 } 975 976 vmw_kms_close(dev_priv); 977 vmw_overlay_close(dev_priv); 978 979 if (dev_priv->has_gmr) 980 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 981 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 982 983 vmw_release_device_early(dev_priv); 984 if (dev_priv->has_mob) 985 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 986 (void) ttm_bo_device_release(&dev_priv->bdev); 987 vmw_release_device_late(dev_priv); 988 vmw_fence_manager_takedown(dev_priv->fman); 989 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 990 vmw_irq_uninstall(dev_priv->dev); 991 if (dev_priv->stealth) 992 pci_release_region(dev->pdev, 2); 993 else 994 pci_release_regions(dev->pdev); 995 996 ttm_object_device_release(&dev_priv->tdev); 997 memunmap(dev_priv->mmio_virt); 998 if (dev_priv->ctx.staged_bindings) 999 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1000 1001 for (i = vmw_res_context; i < vmw_res_max; ++i) 1002 idr_destroy(&dev_priv->res_idr[i]); 1003 1004 kfree(dev_priv); 1005 } 1006 1007 static void vmw_postclose(struct drm_device *dev, 1008 struct drm_file *file_priv) 1009 { 1010 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1011 1012 ttm_object_file_release(&vmw_fp->tfile); 1013 kfree(vmw_fp); 1014 } 1015 1016 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1017 { 1018 struct vmw_private *dev_priv = vmw_priv(dev); 1019 struct vmw_fpriv *vmw_fp; 1020 int ret = -ENOMEM; 1021 1022 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1023 if (unlikely(!vmw_fp)) 1024 return ret; 1025 1026 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1027 if (unlikely(vmw_fp->tfile == NULL)) 1028 goto out_no_tfile; 1029 1030 file_priv->driver_priv = vmw_fp; 1031 1032 return 0; 1033 1034 out_no_tfile: 1035 kfree(vmw_fp); 1036 return ret; 1037 } 1038 1039 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1040 unsigned long arg, 1041 long (*ioctl_func)(struct file *, unsigned int, 1042 unsigned long)) 1043 { 1044 struct drm_file *file_priv = filp->private_data; 1045 struct drm_device *dev = file_priv->minor->dev; 1046 unsigned int nr = DRM_IOCTL_NR(cmd); 1047 unsigned int flags; 1048 long ret; 1049 1050 /* 1051 * Do extra checking on driver private ioctls. 1052 */ 1053 1054 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1055 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1056 const struct drm_ioctl_desc *ioctl = 1057 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1058 1059 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1060 ret = (long) drm_ioctl_permit(ioctl->flags, file_priv); 1061 if (unlikely(ret != 0)) 1062 return ret; 1063 1064 if (unlikely((cmd & (IOC_IN | IOC_OUT)) != IOC_IN)) 1065 goto out_io_encoding; 1066 1067 return (long) vmw_execbuf_ioctl(dev, arg, file_priv, 1068 _IOC_SIZE(cmd)); 1069 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1070 if (!drm_is_current_master(file_priv) && 1071 !capable(CAP_SYS_ADMIN)) 1072 return -EACCES; 1073 } 1074 1075 if (unlikely(ioctl->cmd != cmd)) 1076 goto out_io_encoding; 1077 1078 flags = ioctl->flags; 1079 } else if (!drm_ioctl_flags(nr, &flags)) 1080 return -EINVAL; 1081 1082 return ioctl_func(filp, cmd, arg); 1083 1084 out_io_encoding: 1085 DRM_ERROR("Invalid command format, ioctl %d\n", 1086 nr - DRM_COMMAND_BASE); 1087 1088 return -EINVAL; 1089 } 1090 1091 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1092 unsigned long arg) 1093 { 1094 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1095 } 1096 1097 #ifdef CONFIG_COMPAT 1098 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1099 unsigned long arg) 1100 { 1101 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1102 } 1103 #endif 1104 1105 static void vmw_lastclose(struct drm_device *dev) 1106 { 1107 } 1108 1109 static int vmw_master_set(struct drm_device *dev, 1110 struct drm_file *file_priv, 1111 bool from_open) 1112 { 1113 /* 1114 * Inform a new master that the layout may have changed while 1115 * it was gone. 1116 */ 1117 if (!from_open) 1118 drm_sysfs_hotplug_event(dev); 1119 1120 return 0; 1121 } 1122 1123 static void vmw_master_drop(struct drm_device *dev, 1124 struct drm_file *file_priv) 1125 { 1126 struct vmw_private *dev_priv = vmw_priv(dev); 1127 1128 vmw_kms_legacy_hotspot_clear(dev_priv); 1129 if (!dev_priv->enable_fb) 1130 vmw_svga_disable(dev_priv); 1131 } 1132 1133 /** 1134 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1135 * 1136 * @dev_priv: Pointer to device private struct. 1137 * Needs the reservation sem to be held in non-exclusive mode. 1138 */ 1139 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1140 { 1141 spin_lock(&dev_priv->svga_lock); 1142 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1143 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1144 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1145 } 1146 spin_unlock(&dev_priv->svga_lock); 1147 } 1148 1149 /** 1150 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1151 * 1152 * @dev_priv: Pointer to device private struct. 1153 */ 1154 void vmw_svga_enable(struct vmw_private *dev_priv) 1155 { 1156 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1157 __vmw_svga_enable(dev_priv); 1158 ttm_read_unlock(&dev_priv->reservation_sem); 1159 } 1160 1161 /** 1162 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1163 * 1164 * @dev_priv: Pointer to device private struct. 1165 * Needs the reservation sem to be held in exclusive mode. 1166 * Will not empty VRAM. VRAM must be emptied by caller. 1167 */ 1168 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1169 { 1170 spin_lock(&dev_priv->svga_lock); 1171 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1172 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1173 vmw_write(dev_priv, SVGA_REG_ENABLE, 1174 SVGA_REG_ENABLE_HIDE | 1175 SVGA_REG_ENABLE_ENABLE); 1176 } 1177 spin_unlock(&dev_priv->svga_lock); 1178 } 1179 1180 /** 1181 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1182 * running. 1183 * 1184 * @dev_priv: Pointer to device private struct. 1185 * Will empty VRAM. 1186 */ 1187 void vmw_svga_disable(struct vmw_private *dev_priv) 1188 { 1189 /* 1190 * Disabling SVGA will turn off device modesetting capabilities, so 1191 * notify KMS about that so that it doesn't cache atomic state that 1192 * isn't valid anymore, for example crtcs turned on. 1193 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1194 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1195 * end up with lock order reversal. Thus, a master may actually perform 1196 * a new modeset just after we call vmw_kms_lost_device() and race with 1197 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1198 * to be inconsistent with the device, causing modesetting problems. 1199 * 1200 */ 1201 vmw_kms_lost_device(dev_priv->dev); 1202 ttm_write_lock(&dev_priv->reservation_sem, false); 1203 spin_lock(&dev_priv->svga_lock); 1204 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1205 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1206 spin_unlock(&dev_priv->svga_lock); 1207 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1208 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1209 vmw_write(dev_priv, SVGA_REG_ENABLE, 1210 SVGA_REG_ENABLE_HIDE | 1211 SVGA_REG_ENABLE_ENABLE); 1212 } else 1213 spin_unlock(&dev_priv->svga_lock); 1214 ttm_write_unlock(&dev_priv->reservation_sem); 1215 } 1216 1217 static void vmw_remove(struct pci_dev *pdev) 1218 { 1219 struct drm_device *dev = pci_get_drvdata(pdev); 1220 1221 pci_disable_device(pdev); 1222 drm_put_dev(dev); 1223 } 1224 1225 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1226 void *ptr) 1227 { 1228 struct vmw_private *dev_priv = 1229 container_of(nb, struct vmw_private, pm_nb); 1230 1231 switch (val) { 1232 case PM_HIBERNATION_PREPARE: 1233 /* 1234 * Take the reservation sem in write mode, which will make sure 1235 * there are no other processes holding a buffer object 1236 * reservation, meaning we should be able to evict all buffer 1237 * objects if needed. 1238 * Once user-space processes have been frozen, we can release 1239 * the lock again. 1240 */ 1241 ttm_suspend_lock(&dev_priv->reservation_sem); 1242 dev_priv->suspend_locked = true; 1243 break; 1244 case PM_POST_HIBERNATION: 1245 case PM_POST_RESTORE: 1246 if (READ_ONCE(dev_priv->suspend_locked)) { 1247 dev_priv->suspend_locked = false; 1248 ttm_suspend_unlock(&dev_priv->reservation_sem); 1249 } 1250 break; 1251 default: 1252 break; 1253 } 1254 return 0; 1255 } 1256 1257 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1258 { 1259 struct drm_device *dev = pci_get_drvdata(pdev); 1260 struct vmw_private *dev_priv = vmw_priv(dev); 1261 1262 if (dev_priv->refuse_hibernation) 1263 return -EBUSY; 1264 1265 pci_save_state(pdev); 1266 pci_disable_device(pdev); 1267 pci_set_power_state(pdev, PCI_D3hot); 1268 return 0; 1269 } 1270 1271 static int vmw_pci_resume(struct pci_dev *pdev) 1272 { 1273 pci_set_power_state(pdev, PCI_D0); 1274 pci_restore_state(pdev); 1275 return pci_enable_device(pdev); 1276 } 1277 1278 static int vmw_pm_suspend(struct device *kdev) 1279 { 1280 struct pci_dev *pdev = to_pci_dev(kdev); 1281 struct pm_message dummy; 1282 1283 dummy.event = 0; 1284 1285 return vmw_pci_suspend(pdev, dummy); 1286 } 1287 1288 static int vmw_pm_resume(struct device *kdev) 1289 { 1290 struct pci_dev *pdev = to_pci_dev(kdev); 1291 1292 return vmw_pci_resume(pdev); 1293 } 1294 1295 static int vmw_pm_freeze(struct device *kdev) 1296 { 1297 struct pci_dev *pdev = to_pci_dev(kdev); 1298 struct drm_device *dev = pci_get_drvdata(pdev); 1299 struct vmw_private *dev_priv = vmw_priv(dev); 1300 int ret; 1301 1302 /* 1303 * Unlock for vmw_kms_suspend. 1304 * No user-space processes should be running now. 1305 */ 1306 ttm_suspend_unlock(&dev_priv->reservation_sem); 1307 ret = vmw_kms_suspend(dev_priv->dev); 1308 if (ret) { 1309 ttm_suspend_lock(&dev_priv->reservation_sem); 1310 DRM_ERROR("Failed to freeze modesetting.\n"); 1311 return ret; 1312 } 1313 if (dev_priv->enable_fb) 1314 vmw_fb_off(dev_priv); 1315 1316 ttm_suspend_lock(&dev_priv->reservation_sem); 1317 vmw_execbuf_release_pinned_bo(dev_priv); 1318 vmw_resource_evict_all(dev_priv); 1319 vmw_release_device_early(dev_priv); 1320 ttm_bo_swapout_all(&dev_priv->bdev); 1321 if (dev_priv->enable_fb) 1322 vmw_fifo_resource_dec(dev_priv); 1323 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1324 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1325 if (dev_priv->enable_fb) 1326 vmw_fifo_resource_inc(dev_priv); 1327 WARN_ON(vmw_request_device_late(dev_priv)); 1328 dev_priv->suspend_locked = false; 1329 ttm_suspend_unlock(&dev_priv->reservation_sem); 1330 if (dev_priv->suspend_state) 1331 vmw_kms_resume(dev); 1332 if (dev_priv->enable_fb) 1333 vmw_fb_on(dev_priv); 1334 return -EBUSY; 1335 } 1336 1337 vmw_fence_fifo_down(dev_priv->fman); 1338 __vmw_svga_disable(dev_priv); 1339 1340 vmw_release_device_late(dev_priv); 1341 return 0; 1342 } 1343 1344 static int vmw_pm_restore(struct device *kdev) 1345 { 1346 struct pci_dev *pdev = to_pci_dev(kdev); 1347 struct drm_device *dev = pci_get_drvdata(pdev); 1348 struct vmw_private *dev_priv = vmw_priv(dev); 1349 int ret; 1350 1351 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1352 (void) vmw_read(dev_priv, SVGA_REG_ID); 1353 1354 if (dev_priv->enable_fb) 1355 vmw_fifo_resource_inc(dev_priv); 1356 1357 ret = vmw_request_device(dev_priv); 1358 if (ret) 1359 return ret; 1360 1361 if (dev_priv->enable_fb) 1362 __vmw_svga_enable(dev_priv); 1363 1364 vmw_fence_fifo_up(dev_priv->fman); 1365 dev_priv->suspend_locked = false; 1366 ttm_suspend_unlock(&dev_priv->reservation_sem); 1367 if (dev_priv->suspend_state) 1368 vmw_kms_resume(dev_priv->dev); 1369 1370 if (dev_priv->enable_fb) 1371 vmw_fb_on(dev_priv); 1372 1373 return 0; 1374 } 1375 1376 static const struct dev_pm_ops vmw_pm_ops = { 1377 .freeze = vmw_pm_freeze, 1378 .thaw = vmw_pm_restore, 1379 .restore = vmw_pm_restore, 1380 .suspend = vmw_pm_suspend, 1381 .resume = vmw_pm_resume, 1382 }; 1383 1384 static const struct file_operations vmwgfx_driver_fops = { 1385 .owner = THIS_MODULE, 1386 .open = drm_open, 1387 .release = drm_release, 1388 .unlocked_ioctl = vmw_unlocked_ioctl, 1389 .mmap = vmw_mmap, 1390 .poll = vmw_fops_poll, 1391 .read = vmw_fops_read, 1392 #if defined(CONFIG_COMPAT) 1393 .compat_ioctl = vmw_compat_ioctl, 1394 #endif 1395 .llseek = noop_llseek, 1396 }; 1397 1398 static struct drm_driver driver = { 1399 .driver_features = 1400 DRIVER_MODESET | DRIVER_PRIME | DRIVER_RENDER | DRIVER_ATOMIC, 1401 .load = vmw_driver_load, 1402 .unload = vmw_driver_unload, 1403 .lastclose = vmw_lastclose, 1404 .get_vblank_counter = vmw_get_vblank_counter, 1405 .enable_vblank = vmw_enable_vblank, 1406 .disable_vblank = vmw_disable_vblank, 1407 .ioctls = vmw_ioctls, 1408 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1409 .master_set = vmw_master_set, 1410 .master_drop = vmw_master_drop, 1411 .open = vmw_driver_open, 1412 .postclose = vmw_postclose, 1413 1414 .dumb_create = vmw_dumb_create, 1415 .dumb_map_offset = vmw_dumb_map_offset, 1416 .dumb_destroy = vmw_dumb_destroy, 1417 1418 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1419 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1420 1421 .fops = &vmwgfx_driver_fops, 1422 .name = VMWGFX_DRIVER_NAME, 1423 .desc = VMWGFX_DRIVER_DESC, 1424 .date = VMWGFX_DRIVER_DATE, 1425 .major = VMWGFX_DRIVER_MAJOR, 1426 .minor = VMWGFX_DRIVER_MINOR, 1427 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1428 }; 1429 1430 static struct pci_driver vmw_pci_driver = { 1431 .name = VMWGFX_DRIVER_NAME, 1432 .id_table = vmw_pci_id_list, 1433 .probe = vmw_probe, 1434 .remove = vmw_remove, 1435 .driver = { 1436 .pm = &vmw_pm_ops 1437 } 1438 }; 1439 1440 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1441 { 1442 return drm_get_pci_dev(pdev, ent, &driver); 1443 } 1444 1445 static int __init vmwgfx_init(void) 1446 { 1447 int ret; 1448 1449 if (vgacon_text_force()) 1450 return -EINVAL; 1451 1452 ret = pci_register_driver(&vmw_pci_driver); 1453 if (ret) 1454 DRM_ERROR("Failed initializing DRM.\n"); 1455 return ret; 1456 } 1457 1458 static void __exit vmwgfx_exit(void) 1459 { 1460 pci_unregister_driver(&vmw_pci_driver); 1461 } 1462 1463 module_init(vmwgfx_init); 1464 module_exit(vmwgfx_exit); 1465 1466 MODULE_AUTHOR("VMware Inc. and others"); 1467 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1468 MODULE_LICENSE("GPL and additional rights"); 1469 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1470 __stringify(VMWGFX_DRIVER_MINOR) "." 1471 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1472 "0"); 1473