1 /**************************************************************************
2  *
3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the
8  * "Software"), to deal in the Software without restriction, including
9  * without limitation the rights to use, copy, modify, merge, publish,
10  * distribute, sub license, and/or sell copies of the Software, and to
11  * permit persons to whom the Software is furnished to do so, subject to
12  * the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the
15  * next paragraph) shall be included in all copies or substantial portions
16  * of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
25  *
26  **************************************************************************/
27 
28 #include "drmP.h"
29 #include "vmwgfx_drv.h"
30 #include "ttm/ttm_placement.h"
31 #include "ttm/ttm_bo_driver.h"
32 #include "ttm/ttm_object.h"
33 #include "ttm/ttm_module.h"
34 
35 #define VMWGFX_DRIVER_NAME "vmwgfx"
36 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices"
37 #define VMWGFX_CHIP_SVGAII 0
38 #define VMW_FB_RESERVATION 0
39 
40 /**
41  * Fully encoded drm commands. Might move to vmw_drm.h
42  */
43 
44 #define DRM_IOCTL_VMW_GET_PARAM					\
45 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM,		\
46 		 struct drm_vmw_getparam_arg)
47 #define DRM_IOCTL_VMW_ALLOC_DMABUF				\
48 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF,	\
49 		union drm_vmw_alloc_dmabuf_arg)
50 #define DRM_IOCTL_VMW_UNREF_DMABUF				\
51 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF,	\
52 		struct drm_vmw_unref_dmabuf_arg)
53 #define DRM_IOCTL_VMW_CURSOR_BYPASS				\
54 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS,	\
55 		 struct drm_vmw_cursor_bypass_arg)
56 
57 #define DRM_IOCTL_VMW_CONTROL_STREAM				\
58 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM,	\
59 		 struct drm_vmw_control_stream_arg)
60 #define DRM_IOCTL_VMW_CLAIM_STREAM				\
61 	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM,	\
62 		 struct drm_vmw_stream_arg)
63 #define DRM_IOCTL_VMW_UNREF_STREAM				\
64 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM,	\
65 		 struct drm_vmw_stream_arg)
66 
67 #define DRM_IOCTL_VMW_CREATE_CONTEXT				\
68 	DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT,	\
69 		struct drm_vmw_context_arg)
70 #define DRM_IOCTL_VMW_UNREF_CONTEXT				\
71 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT,	\
72 		struct drm_vmw_context_arg)
73 #define DRM_IOCTL_VMW_CREATE_SURFACE				\
74 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE,	\
75 		 union drm_vmw_surface_create_arg)
76 #define DRM_IOCTL_VMW_UNREF_SURFACE				\
77 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE,	\
78 		 struct drm_vmw_surface_arg)
79 #define DRM_IOCTL_VMW_REF_SURFACE				\
80 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE,	\
81 		 union drm_vmw_surface_reference_arg)
82 #define DRM_IOCTL_VMW_EXECBUF					\
83 	DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,		\
84 		struct drm_vmw_execbuf_arg)
85 #define DRM_IOCTL_VMW_FIFO_DEBUG				\
86 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FIFO_DEBUG,		\
87 		 struct drm_vmw_fifo_debug_arg)
88 #define DRM_IOCTL_VMW_FENCE_WAIT				\
89 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,		\
90 		 struct drm_vmw_fence_wait_arg)
91 #define DRM_IOCTL_VMW_UPDATE_LAYOUT				\
92 	DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,	\
93 		 struct drm_vmw_update_layout_arg)
94 
95 
96 /**
97  * The core DRM version of this macro doesn't account for
98  * DRM_COMMAND_BASE.
99  */
100 
101 #define VMW_IOCTL_DEF(ioctl, func, flags) \
102   [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_##ioctl, flags, func, DRM_IOCTL_##ioctl}
103 
104 /**
105  * Ioctl definitions.
106  */
107 
108 static struct drm_ioctl_desc vmw_ioctls[] = {
109 	VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl,
110 		      DRM_AUTH | DRM_UNLOCKED),
111 	VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_dmabuf_alloc_ioctl,
112 		      DRM_AUTH | DRM_UNLOCKED),
113 	VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_dmabuf_unref_ioctl,
114 		      DRM_AUTH | DRM_UNLOCKED),
115 	VMW_IOCTL_DEF(VMW_CURSOR_BYPASS,
116 		      vmw_kms_cursor_bypass_ioctl,
117 		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
118 
119 	VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl,
120 		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
121 	VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl,
122 		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
123 	VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl,
124 		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED),
125 
126 	VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl,
127 		      DRM_AUTH | DRM_UNLOCKED),
128 	VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl,
129 		      DRM_AUTH | DRM_UNLOCKED),
130 	VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl,
131 		      DRM_AUTH | DRM_UNLOCKED),
132 	VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl,
133 		      DRM_AUTH | DRM_UNLOCKED),
134 	VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl,
135 		      DRM_AUTH | DRM_UNLOCKED),
136 	VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
137 		      DRM_AUTH | DRM_UNLOCKED),
138 	VMW_IOCTL_DEF(VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl,
139 		      DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED),
140 	VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_wait_ioctl,
141 		      DRM_AUTH | DRM_UNLOCKED),
142 	VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, vmw_kms_update_layout_ioctl,
143 		      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED)
144 };
145 
146 static struct pci_device_id vmw_pci_id_list[] = {
147 	{0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII},
148 	{0, 0, 0}
149 };
150 
151 static int enable_fbdev;
152 
153 static int vmw_probe(struct pci_dev *, const struct pci_device_id *);
154 static void vmw_master_init(struct vmw_master *);
155 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
156 			      void *ptr);
157 
158 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev");
159 module_param_named(enable_fbdev, enable_fbdev, int, 0600);
160 
161 static void vmw_print_capabilities(uint32_t capabilities)
162 {
163 	DRM_INFO("Capabilities:\n");
164 	if (capabilities & SVGA_CAP_RECT_COPY)
165 		DRM_INFO("  Rect copy.\n");
166 	if (capabilities & SVGA_CAP_CURSOR)
167 		DRM_INFO("  Cursor.\n");
168 	if (capabilities & SVGA_CAP_CURSOR_BYPASS)
169 		DRM_INFO("  Cursor bypass.\n");
170 	if (capabilities & SVGA_CAP_CURSOR_BYPASS_2)
171 		DRM_INFO("  Cursor bypass 2.\n");
172 	if (capabilities & SVGA_CAP_8BIT_EMULATION)
173 		DRM_INFO("  8bit emulation.\n");
174 	if (capabilities & SVGA_CAP_ALPHA_CURSOR)
175 		DRM_INFO("  Alpha cursor.\n");
176 	if (capabilities & SVGA_CAP_3D)
177 		DRM_INFO("  3D.\n");
178 	if (capabilities & SVGA_CAP_EXTENDED_FIFO)
179 		DRM_INFO("  Extended Fifo.\n");
180 	if (capabilities & SVGA_CAP_MULTIMON)
181 		DRM_INFO("  Multimon.\n");
182 	if (capabilities & SVGA_CAP_PITCHLOCK)
183 		DRM_INFO("  Pitchlock.\n");
184 	if (capabilities & SVGA_CAP_IRQMASK)
185 		DRM_INFO("  Irq mask.\n");
186 	if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY)
187 		DRM_INFO("  Display Topology.\n");
188 	if (capabilities & SVGA_CAP_GMR)
189 		DRM_INFO("  GMR.\n");
190 	if (capabilities & SVGA_CAP_TRACES)
191 		DRM_INFO("  Traces.\n");
192 }
193 
194 static int vmw_request_device(struct vmw_private *dev_priv)
195 {
196 	int ret;
197 
198 	ret = vmw_fifo_init(dev_priv, &dev_priv->fifo);
199 	if (unlikely(ret != 0)) {
200 		DRM_ERROR("Unable to initialize FIFO.\n");
201 		return ret;
202 	}
203 
204 	return 0;
205 }
206 
207 static void vmw_release_device(struct vmw_private *dev_priv)
208 {
209 	vmw_fifo_release(dev_priv, &dev_priv->fifo);
210 }
211 
212 int vmw_3d_resource_inc(struct vmw_private *dev_priv)
213 {
214 	int ret = 0;
215 
216 	mutex_lock(&dev_priv->release_mutex);
217 	if (unlikely(dev_priv->num_3d_resources++ == 0)) {
218 		ret = vmw_request_device(dev_priv);
219 		if (unlikely(ret != 0))
220 			--dev_priv->num_3d_resources;
221 	}
222 	mutex_unlock(&dev_priv->release_mutex);
223 	return ret;
224 }
225 
226 
227 void vmw_3d_resource_dec(struct vmw_private *dev_priv)
228 {
229 	int32_t n3d;
230 
231 	mutex_lock(&dev_priv->release_mutex);
232 	if (unlikely(--dev_priv->num_3d_resources == 0))
233 		vmw_release_device(dev_priv);
234 	n3d = (int32_t) dev_priv->num_3d_resources;
235 	mutex_unlock(&dev_priv->release_mutex);
236 
237 	BUG_ON(n3d < 0);
238 }
239 
240 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
241 {
242 	struct vmw_private *dev_priv;
243 	int ret;
244 	uint32_t svga_id;
245 
246 	dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
247 	if (unlikely(dev_priv == NULL)) {
248 		DRM_ERROR("Failed allocating a device private struct.\n");
249 		return -ENOMEM;
250 	}
251 	memset(dev_priv, 0, sizeof(*dev_priv));
252 
253 	dev_priv->dev = dev;
254 	dev_priv->vmw_chipset = chipset;
255 	dev_priv->last_read_sequence = (uint32_t) -100;
256 	mutex_init(&dev_priv->hw_mutex);
257 	mutex_init(&dev_priv->cmdbuf_mutex);
258 	mutex_init(&dev_priv->release_mutex);
259 	rwlock_init(&dev_priv->resource_lock);
260 	idr_init(&dev_priv->context_idr);
261 	idr_init(&dev_priv->surface_idr);
262 	idr_init(&dev_priv->stream_idr);
263 	mutex_init(&dev_priv->init_mutex);
264 	init_waitqueue_head(&dev_priv->fence_queue);
265 	init_waitqueue_head(&dev_priv->fifo_queue);
266 	atomic_set(&dev_priv->fence_queue_waiters, 0);
267 	atomic_set(&dev_priv->fifo_queue_waiters, 0);
268 
269 	dev_priv->io_start = pci_resource_start(dev->pdev, 0);
270 	dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
271 	dev_priv->mmio_start = pci_resource_start(dev->pdev, 2);
272 
273 	dev_priv->enable_fb = enable_fbdev;
274 
275 	mutex_lock(&dev_priv->hw_mutex);
276 
277 	vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2);
278 	svga_id = vmw_read(dev_priv, SVGA_REG_ID);
279 	if (svga_id != SVGA_ID_2) {
280 		ret = -ENOSYS;
281 		DRM_ERROR("Unsuported SVGA ID 0x%x\n", svga_id);
282 		mutex_unlock(&dev_priv->hw_mutex);
283 		goto out_err0;
284 	}
285 
286 	dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
287 
288 	if (dev_priv->capabilities & SVGA_CAP_GMR) {
289 		dev_priv->max_gmr_descriptors =
290 			vmw_read(dev_priv,
291 				 SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH);
292 		dev_priv->max_gmr_ids =
293 			vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
294 	}
295 
296 	dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
297 	dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
298 	dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
299 	dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
300 
301 	mutex_unlock(&dev_priv->hw_mutex);
302 
303 	vmw_print_capabilities(dev_priv->capabilities);
304 
305 	if (dev_priv->capabilities & SVGA_CAP_GMR) {
306 		DRM_INFO("Max GMR ids is %u\n",
307 			 (unsigned)dev_priv->max_gmr_ids);
308 		DRM_INFO("Max GMR descriptors is %u\n",
309 			 (unsigned)dev_priv->max_gmr_descriptors);
310 	}
311 	DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
312 		 dev_priv->vram_start, dev_priv->vram_size / 1024);
313 	DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
314 		 dev_priv->mmio_start, dev_priv->mmio_size / 1024);
315 
316 	ret = vmw_ttm_global_init(dev_priv);
317 	if (unlikely(ret != 0))
318 		goto out_err0;
319 
320 
321 	vmw_master_init(&dev_priv->fbdev_master);
322 	ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
323 	dev_priv->active_master = &dev_priv->fbdev_master;
324 
325 
326 	ret = ttm_bo_device_init(&dev_priv->bdev,
327 				 dev_priv->bo_global_ref.ref.object,
328 				 &vmw_bo_driver, VMWGFX_FILE_PAGE_OFFSET,
329 				 false);
330 	if (unlikely(ret != 0)) {
331 		DRM_ERROR("Failed initializing TTM buffer object driver.\n");
332 		goto out_err1;
333 	}
334 
335 	ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM,
336 			     (dev_priv->vram_size >> PAGE_SHIFT));
337 	if (unlikely(ret != 0)) {
338 		DRM_ERROR("Failed initializing memory manager for VRAM.\n");
339 		goto out_err2;
340 	}
341 
342 	dev_priv->has_gmr = true;
343 	if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR,
344 			   dev_priv->max_gmr_ids) != 0) {
345 		DRM_INFO("No GMR memory available. "
346 			 "Graphics memory resources are very limited.\n");
347 		dev_priv->has_gmr = false;
348 	}
349 
350 	dev_priv->mmio_mtrr = drm_mtrr_add(dev_priv->mmio_start,
351 					   dev_priv->mmio_size, DRM_MTRR_WC);
352 
353 	dev_priv->mmio_virt = ioremap_wc(dev_priv->mmio_start,
354 					 dev_priv->mmio_size);
355 
356 	if (unlikely(dev_priv->mmio_virt == NULL)) {
357 		ret = -ENOMEM;
358 		DRM_ERROR("Failed mapping MMIO.\n");
359 		goto out_err3;
360 	}
361 
362 	/* Need mmio memory to check for fifo pitchlock cap. */
363 	if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
364 	    !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) &&
365 	    !vmw_fifo_have_pitchlock(dev_priv)) {
366 		ret = -ENOSYS;
367 		DRM_ERROR("Hardware has no pitchlock\n");
368 		goto out_err4;
369 	}
370 
371 	dev_priv->tdev = ttm_object_device_init
372 	    (dev_priv->mem_global_ref.object, 12);
373 
374 	if (unlikely(dev_priv->tdev == NULL)) {
375 		DRM_ERROR("Unable to initialize TTM object management.\n");
376 		ret = -ENOMEM;
377 		goto out_err4;
378 	}
379 
380 	dev->dev_private = dev_priv;
381 
382 	ret = pci_request_regions(dev->pdev, "vmwgfx probe");
383 	dev_priv->stealth = (ret != 0);
384 	if (dev_priv->stealth) {
385 		/**
386 		 * Request at least the mmio PCI resource.
387 		 */
388 
389 		DRM_INFO("It appears like vesafb is loaded. "
390 			 "Ignore above error if any.\n");
391 		ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe");
392 		if (unlikely(ret != 0)) {
393 			DRM_ERROR("Failed reserving the SVGA MMIO resource.\n");
394 			goto out_no_device;
395 		}
396 	}
397 	ret = vmw_kms_init(dev_priv);
398 	if (unlikely(ret != 0))
399 		goto out_no_kms;
400 	vmw_overlay_init(dev_priv);
401 	if (dev_priv->enable_fb) {
402 		ret = vmw_3d_resource_inc(dev_priv);
403 		if (unlikely(ret != 0))
404 			goto out_no_fifo;
405 		vmw_kms_save_vga(dev_priv);
406 		vmw_fb_init(dev_priv);
407 		DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ?
408 			 "Detected device 3D availability.\n" :
409 			 "Detected no device 3D availability.\n");
410 	} else {
411 		DRM_INFO("Delayed 3D detection since we're not "
412 			 "running the device in SVGA mode yet.\n");
413 	}
414 
415 	if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
416 		ret = drm_irq_install(dev);
417 		if (unlikely(ret != 0)) {
418 			DRM_ERROR("Failed installing irq: %d\n", ret);
419 			goto out_no_irq;
420 		}
421 	}
422 
423 	dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier;
424 	register_pm_notifier(&dev_priv->pm_nb);
425 
426 	return 0;
427 
428 out_no_irq:
429 	if (dev_priv->enable_fb) {
430 		vmw_fb_close(dev_priv);
431 		vmw_kms_restore_vga(dev_priv);
432 		vmw_3d_resource_dec(dev_priv);
433 	}
434 out_no_fifo:
435 	vmw_overlay_close(dev_priv);
436 	vmw_kms_close(dev_priv);
437 out_no_kms:
438 	if (dev_priv->stealth)
439 		pci_release_region(dev->pdev, 2);
440 	else
441 		pci_release_regions(dev->pdev);
442 out_no_device:
443 	ttm_object_device_release(&dev_priv->tdev);
444 out_err4:
445 	iounmap(dev_priv->mmio_virt);
446 out_err3:
447 	drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
448 		     dev_priv->mmio_size, DRM_MTRR_WC);
449 	if (dev_priv->has_gmr)
450 		(void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
451 	(void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
452 out_err2:
453 	(void)ttm_bo_device_release(&dev_priv->bdev);
454 out_err1:
455 	vmw_ttm_global_release(dev_priv);
456 out_err0:
457 	idr_destroy(&dev_priv->surface_idr);
458 	idr_destroy(&dev_priv->context_idr);
459 	idr_destroy(&dev_priv->stream_idr);
460 	kfree(dev_priv);
461 	return ret;
462 }
463 
464 static int vmw_driver_unload(struct drm_device *dev)
465 {
466 	struct vmw_private *dev_priv = vmw_priv(dev);
467 
468 	unregister_pm_notifier(&dev_priv->pm_nb);
469 
470 	if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
471 		drm_irq_uninstall(dev_priv->dev);
472 	if (dev_priv->enable_fb) {
473 		vmw_fb_close(dev_priv);
474 		vmw_kms_restore_vga(dev_priv);
475 		vmw_3d_resource_dec(dev_priv);
476 	}
477 	vmw_kms_close(dev_priv);
478 	vmw_overlay_close(dev_priv);
479 	if (dev_priv->stealth)
480 		pci_release_region(dev->pdev, 2);
481 	else
482 		pci_release_regions(dev->pdev);
483 
484 	ttm_object_device_release(&dev_priv->tdev);
485 	iounmap(dev_priv->mmio_virt);
486 	drm_mtrr_del(dev_priv->mmio_mtrr, dev_priv->mmio_start,
487 		     dev_priv->mmio_size, DRM_MTRR_WC);
488 	if (dev_priv->has_gmr)
489 		(void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR);
490 	(void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM);
491 	(void)ttm_bo_device_release(&dev_priv->bdev);
492 	vmw_ttm_global_release(dev_priv);
493 	idr_destroy(&dev_priv->surface_idr);
494 	idr_destroy(&dev_priv->context_idr);
495 	idr_destroy(&dev_priv->stream_idr);
496 
497 	kfree(dev_priv);
498 
499 	return 0;
500 }
501 
502 static void vmw_postclose(struct drm_device *dev,
503 			 struct drm_file *file_priv)
504 {
505 	struct vmw_fpriv *vmw_fp;
506 
507 	vmw_fp = vmw_fpriv(file_priv);
508 	ttm_object_file_release(&vmw_fp->tfile);
509 	if (vmw_fp->locked_master)
510 		drm_master_put(&vmw_fp->locked_master);
511 	kfree(vmw_fp);
512 }
513 
514 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv)
515 {
516 	struct vmw_private *dev_priv = vmw_priv(dev);
517 	struct vmw_fpriv *vmw_fp;
518 	int ret = -ENOMEM;
519 
520 	vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL);
521 	if (unlikely(vmw_fp == NULL))
522 		return ret;
523 
524 	vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10);
525 	if (unlikely(vmw_fp->tfile == NULL))
526 		goto out_no_tfile;
527 
528 	file_priv->driver_priv = vmw_fp;
529 
530 	if (unlikely(dev_priv->bdev.dev_mapping == NULL))
531 		dev_priv->bdev.dev_mapping =
532 			file_priv->filp->f_path.dentry->d_inode->i_mapping;
533 
534 	return 0;
535 
536 out_no_tfile:
537 	kfree(vmw_fp);
538 	return ret;
539 }
540 
541 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd,
542 			       unsigned long arg)
543 {
544 	struct drm_file *file_priv = filp->private_data;
545 	struct drm_device *dev = file_priv->minor->dev;
546 	unsigned int nr = DRM_IOCTL_NR(cmd);
547 
548 	/*
549 	 * Do extra checking on driver private ioctls.
550 	 */
551 
552 	if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
553 	    && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
554 		struct drm_ioctl_desc *ioctl =
555 		    &vmw_ioctls[nr - DRM_COMMAND_BASE];
556 
557 		if (unlikely(ioctl->cmd_drv != cmd)) {
558 			DRM_ERROR("Invalid command format, ioctl %d\n",
559 				  nr - DRM_COMMAND_BASE);
560 			return -EINVAL;
561 		}
562 	}
563 
564 	return drm_ioctl(filp, cmd, arg);
565 }
566 
567 static int vmw_firstopen(struct drm_device *dev)
568 {
569 	struct vmw_private *dev_priv = vmw_priv(dev);
570 	dev_priv->is_opened = true;
571 
572 	return 0;
573 }
574 
575 static void vmw_lastclose(struct drm_device *dev)
576 {
577 	struct vmw_private *dev_priv = vmw_priv(dev);
578 	struct drm_crtc *crtc;
579 	struct drm_mode_set set;
580 	int ret;
581 
582 	/**
583 	 * Do nothing on the lastclose call from drm_unload.
584 	 */
585 
586 	if (!dev_priv->is_opened)
587 		return;
588 
589 	dev_priv->is_opened = false;
590 	set.x = 0;
591 	set.y = 0;
592 	set.fb = NULL;
593 	set.mode = NULL;
594 	set.connectors = NULL;
595 	set.num_connectors = 0;
596 
597 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
598 		set.crtc = crtc;
599 		ret = crtc->funcs->set_config(&set);
600 		WARN_ON(ret != 0);
601 	}
602 
603 }
604 
605 static void vmw_master_init(struct vmw_master *vmaster)
606 {
607 	ttm_lock_init(&vmaster->lock);
608 	INIT_LIST_HEAD(&vmaster->fb_surf);
609 	mutex_init(&vmaster->fb_surf_mutex);
610 }
611 
612 static int vmw_master_create(struct drm_device *dev,
613 			     struct drm_master *master)
614 {
615 	struct vmw_master *vmaster;
616 
617 	vmaster = kzalloc(sizeof(*vmaster), GFP_KERNEL);
618 	if (unlikely(vmaster == NULL))
619 		return -ENOMEM;
620 
621 	vmw_master_init(vmaster);
622 	ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
623 	master->driver_priv = vmaster;
624 
625 	return 0;
626 }
627 
628 static void vmw_master_destroy(struct drm_device *dev,
629 			       struct drm_master *master)
630 {
631 	struct vmw_master *vmaster = vmw_master(master);
632 
633 	master->driver_priv = NULL;
634 	kfree(vmaster);
635 }
636 
637 
638 static int vmw_master_set(struct drm_device *dev,
639 			  struct drm_file *file_priv,
640 			  bool from_open)
641 {
642 	struct vmw_private *dev_priv = vmw_priv(dev);
643 	struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
644 	struct vmw_master *active = dev_priv->active_master;
645 	struct vmw_master *vmaster = vmw_master(file_priv->master);
646 	int ret = 0;
647 
648 	if (!dev_priv->enable_fb) {
649 		ret = vmw_3d_resource_inc(dev_priv);
650 		if (unlikely(ret != 0))
651 			return ret;
652 		vmw_kms_save_vga(dev_priv);
653 		mutex_lock(&dev_priv->hw_mutex);
654 		vmw_write(dev_priv, SVGA_REG_TRACES, 0);
655 		mutex_unlock(&dev_priv->hw_mutex);
656 	}
657 
658 	if (active) {
659 		BUG_ON(active != &dev_priv->fbdev_master);
660 		ret = ttm_vt_lock(&active->lock, false, vmw_fp->tfile);
661 		if (unlikely(ret != 0))
662 			goto out_no_active_lock;
663 
664 		ttm_lock_set_kill(&active->lock, true, SIGTERM);
665 		ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
666 		if (unlikely(ret != 0)) {
667 			DRM_ERROR("Unable to clean VRAM on "
668 				  "master drop.\n");
669 		}
670 
671 		dev_priv->active_master = NULL;
672 	}
673 
674 	ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
675 	if (!from_open) {
676 		ttm_vt_unlock(&vmaster->lock);
677 		BUG_ON(vmw_fp->locked_master != file_priv->master);
678 		drm_master_put(&vmw_fp->locked_master);
679 	}
680 
681 	dev_priv->active_master = vmaster;
682 
683 	return 0;
684 
685 out_no_active_lock:
686 	if (!dev_priv->enable_fb) {
687 		mutex_lock(&dev_priv->hw_mutex);
688 		vmw_write(dev_priv, SVGA_REG_TRACES, 1);
689 		mutex_unlock(&dev_priv->hw_mutex);
690 		vmw_kms_restore_vga(dev_priv);
691 		vmw_3d_resource_dec(dev_priv);
692 	}
693 	return ret;
694 }
695 
696 static void vmw_master_drop(struct drm_device *dev,
697 			    struct drm_file *file_priv,
698 			    bool from_release)
699 {
700 	struct vmw_private *dev_priv = vmw_priv(dev);
701 	struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
702 	struct vmw_master *vmaster = vmw_master(file_priv->master);
703 	int ret;
704 
705 	/**
706 	 * Make sure the master doesn't disappear while we have
707 	 * it locked.
708 	 */
709 
710 	vmw_fp->locked_master = drm_master_get(file_priv->master);
711 	ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
712 	vmw_kms_idle_workqueues(vmaster);
713 
714 	if (unlikely((ret != 0))) {
715 		DRM_ERROR("Unable to lock TTM at VT switch.\n");
716 		drm_master_put(&vmw_fp->locked_master);
717 	}
718 
719 	ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
720 
721 	if (!dev_priv->enable_fb) {
722 		ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
723 		if (unlikely(ret != 0))
724 			DRM_ERROR("Unable to clean VRAM on master drop.\n");
725 		mutex_lock(&dev_priv->hw_mutex);
726 		vmw_write(dev_priv, SVGA_REG_TRACES, 1);
727 		mutex_unlock(&dev_priv->hw_mutex);
728 		vmw_kms_restore_vga(dev_priv);
729 		vmw_3d_resource_dec(dev_priv);
730 	}
731 
732 	dev_priv->active_master = &dev_priv->fbdev_master;
733 	ttm_lock_set_kill(&dev_priv->fbdev_master.lock, false, SIGTERM);
734 	ttm_vt_unlock(&dev_priv->fbdev_master.lock);
735 
736 	if (dev_priv->enable_fb)
737 		vmw_fb_on(dev_priv);
738 }
739 
740 
741 static void vmw_remove(struct pci_dev *pdev)
742 {
743 	struct drm_device *dev = pci_get_drvdata(pdev);
744 
745 	drm_put_dev(dev);
746 }
747 
748 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
749 			      void *ptr)
750 {
751 	struct vmw_private *dev_priv =
752 		container_of(nb, struct vmw_private, pm_nb);
753 	struct vmw_master *vmaster = dev_priv->active_master;
754 
755 	switch (val) {
756 	case PM_HIBERNATION_PREPARE:
757 	case PM_SUSPEND_PREPARE:
758 		ttm_suspend_lock(&vmaster->lock);
759 
760 		/**
761 		 * This empties VRAM and unbinds all GMR bindings.
762 		 * Buffer contents is moved to swappable memory.
763 		 */
764 		ttm_bo_swapout_all(&dev_priv->bdev);
765 
766 		break;
767 	case PM_POST_HIBERNATION:
768 	case PM_POST_SUSPEND:
769 	case PM_POST_RESTORE:
770 		ttm_suspend_unlock(&vmaster->lock);
771 
772 		break;
773 	case PM_RESTORE_PREPARE:
774 		break;
775 	default:
776 		break;
777 	}
778 	return 0;
779 }
780 
781 /**
782  * These might not be needed with the virtual SVGA device.
783  */
784 
785 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state)
786 {
787 	struct drm_device *dev = pci_get_drvdata(pdev);
788 	struct vmw_private *dev_priv = vmw_priv(dev);
789 
790 	if (dev_priv->num_3d_resources != 0) {
791 		DRM_INFO("Can't suspend or hibernate "
792 			 "while 3D resources are active.\n");
793 		return -EBUSY;
794 	}
795 
796 	pci_save_state(pdev);
797 	pci_disable_device(pdev);
798 	pci_set_power_state(pdev, PCI_D3hot);
799 	return 0;
800 }
801 
802 static int vmw_pci_resume(struct pci_dev *pdev)
803 {
804 	pci_set_power_state(pdev, PCI_D0);
805 	pci_restore_state(pdev);
806 	return pci_enable_device(pdev);
807 }
808 
809 static int vmw_pm_suspend(struct device *kdev)
810 {
811 	struct pci_dev *pdev = to_pci_dev(kdev);
812 	struct pm_message dummy;
813 
814 	dummy.event = 0;
815 
816 	return vmw_pci_suspend(pdev, dummy);
817 }
818 
819 static int vmw_pm_resume(struct device *kdev)
820 {
821 	struct pci_dev *pdev = to_pci_dev(kdev);
822 
823 	return vmw_pci_resume(pdev);
824 }
825 
826 static int vmw_pm_prepare(struct device *kdev)
827 {
828 	struct pci_dev *pdev = to_pci_dev(kdev);
829 	struct drm_device *dev = pci_get_drvdata(pdev);
830 	struct vmw_private *dev_priv = vmw_priv(dev);
831 
832 	/**
833 	 * Release 3d reference held by fbdev and potentially
834 	 * stop fifo.
835 	 */
836 	dev_priv->suspended = true;
837 	if (dev_priv->enable_fb)
838 		vmw_3d_resource_dec(dev_priv);
839 
840 	if (dev_priv->num_3d_resources != 0) {
841 
842 		DRM_INFO("Can't suspend or hibernate "
843 			 "while 3D resources are active.\n");
844 
845 		if (dev_priv->enable_fb)
846 			vmw_3d_resource_inc(dev_priv);
847 		dev_priv->suspended = false;
848 		return -EBUSY;
849 	}
850 
851 	return 0;
852 }
853 
854 static void vmw_pm_complete(struct device *kdev)
855 {
856 	struct pci_dev *pdev = to_pci_dev(kdev);
857 	struct drm_device *dev = pci_get_drvdata(pdev);
858 	struct vmw_private *dev_priv = vmw_priv(dev);
859 
860 	/**
861 	 * Reclaim 3d reference held by fbdev and potentially
862 	 * start fifo.
863 	 */
864 	if (dev_priv->enable_fb)
865 		vmw_3d_resource_inc(dev_priv);
866 
867 	dev_priv->suspended = false;
868 }
869 
870 static const struct dev_pm_ops vmw_pm_ops = {
871 	.prepare = vmw_pm_prepare,
872 	.complete = vmw_pm_complete,
873 	.suspend = vmw_pm_suspend,
874 	.resume = vmw_pm_resume,
875 };
876 
877 static struct drm_driver driver = {
878 	.driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED |
879 	DRIVER_MODESET,
880 	.load = vmw_driver_load,
881 	.unload = vmw_driver_unload,
882 	.firstopen = vmw_firstopen,
883 	.lastclose = vmw_lastclose,
884 	.irq_preinstall = vmw_irq_preinstall,
885 	.irq_postinstall = vmw_irq_postinstall,
886 	.irq_uninstall = vmw_irq_uninstall,
887 	.irq_handler = vmw_irq_handler,
888 	.get_vblank_counter = vmw_get_vblank_counter,
889 	.reclaim_buffers_locked = NULL,
890 	.ioctls = vmw_ioctls,
891 	.num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
892 	.dma_quiescent = NULL,	/*vmw_dma_quiescent, */
893 	.master_create = vmw_master_create,
894 	.master_destroy = vmw_master_destroy,
895 	.master_set = vmw_master_set,
896 	.master_drop = vmw_master_drop,
897 	.open = vmw_driver_open,
898 	.postclose = vmw_postclose,
899 	.fops = {
900 		 .owner = THIS_MODULE,
901 		 .open = drm_open,
902 		 .release = drm_release,
903 		 .unlocked_ioctl = vmw_unlocked_ioctl,
904 		 .mmap = vmw_mmap,
905 		 .poll = drm_poll,
906 		 .fasync = drm_fasync,
907 #if defined(CONFIG_COMPAT)
908 		 .compat_ioctl = drm_compat_ioctl,
909 #endif
910 		 .llseek = noop_llseek,
911 	},
912 	.pci_driver = {
913 		 .name = VMWGFX_DRIVER_NAME,
914 		 .id_table = vmw_pci_id_list,
915 		 .probe = vmw_probe,
916 		 .remove = vmw_remove,
917 		 .driver = {
918 			 .pm = &vmw_pm_ops
919 		 }
920 	 },
921 	.name = VMWGFX_DRIVER_NAME,
922 	.desc = VMWGFX_DRIVER_DESC,
923 	.date = VMWGFX_DRIVER_DATE,
924 	.major = VMWGFX_DRIVER_MAJOR,
925 	.minor = VMWGFX_DRIVER_MINOR,
926 	.patchlevel = VMWGFX_DRIVER_PATCHLEVEL
927 };
928 
929 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
930 {
931 	return drm_get_pci_dev(pdev, ent, &driver);
932 }
933 
934 static int __init vmwgfx_init(void)
935 {
936 	int ret;
937 	ret = drm_init(&driver);
938 	if (ret)
939 		DRM_ERROR("Failed initializing DRM.\n");
940 	return ret;
941 }
942 
943 static void __exit vmwgfx_exit(void)
944 {
945 	drm_exit(&driver);
946 }
947 
948 module_init(vmwgfx_init);
949 module_exit(vmwgfx_exit);
950 
951 MODULE_AUTHOR("VMware Inc. and others");
952 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device");
953 MODULE_LICENSE("GPL and additional rights");
954 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "."
955 	       __stringify(VMWGFX_DRIVER_MINOR) "."
956 	       __stringify(VMWGFX_DRIVER_PATCHLEVEL) "."
957 	       "0");
958