1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include <linux/console.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/mem_encrypt.h> 33 34 #include <drm/drm_drv.h> 35 #include <drm/drm_ioctl.h> 36 #include <drm/drm_sysfs.h> 37 #include <drm/ttm/ttm_bo_driver.h> 38 #include <drm/ttm/ttm_module.h> 39 #include <drm/ttm/ttm_placement.h> 40 41 #include "ttm_object.h" 42 #include "vmwgfx_binding.h" 43 #include "vmwgfx_drv.h" 44 45 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 46 #define VMWGFX_CHIP_SVGAII 0 47 #define VMW_FB_RESERVATION 0 48 49 #define VMW_MIN_INITIAL_WIDTH 800 50 #define VMW_MIN_INITIAL_HEIGHT 600 51 52 #ifndef VMWGFX_GIT_VERSION 53 #define VMWGFX_GIT_VERSION "Unknown" 54 #endif 55 56 #define VMWGFX_REPO "In Tree" 57 58 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 59 60 61 /** 62 * Fully encoded drm commands. Might move to vmw_drm.h 63 */ 64 65 #define DRM_IOCTL_VMW_GET_PARAM \ 66 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 67 struct drm_vmw_getparam_arg) 68 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 69 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 70 union drm_vmw_alloc_dmabuf_arg) 71 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 72 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 73 struct drm_vmw_unref_dmabuf_arg) 74 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 75 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 76 struct drm_vmw_cursor_bypass_arg) 77 78 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 80 struct drm_vmw_control_stream_arg) 81 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 82 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 83 struct drm_vmw_stream_arg) 84 #define DRM_IOCTL_VMW_UNREF_STREAM \ 85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 86 struct drm_vmw_stream_arg) 87 88 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 89 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 90 struct drm_vmw_context_arg) 91 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 93 struct drm_vmw_context_arg) 94 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 96 union drm_vmw_surface_create_arg) 97 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 99 struct drm_vmw_surface_arg) 100 #define DRM_IOCTL_VMW_REF_SURFACE \ 101 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 102 union drm_vmw_surface_reference_arg) 103 #define DRM_IOCTL_VMW_EXECBUF \ 104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 105 struct drm_vmw_execbuf_arg) 106 #define DRM_IOCTL_VMW_GET_3D_CAP \ 107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 108 struct drm_vmw_get_3d_cap_arg) 109 #define DRM_IOCTL_VMW_FENCE_WAIT \ 110 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 111 struct drm_vmw_fence_wait_arg) 112 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 113 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 114 struct drm_vmw_fence_signaled_arg) 115 #define DRM_IOCTL_VMW_FENCE_UNREF \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 117 struct drm_vmw_fence_arg) 118 #define DRM_IOCTL_VMW_FENCE_EVENT \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 120 struct drm_vmw_fence_event_arg) 121 #define DRM_IOCTL_VMW_PRESENT \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 123 struct drm_vmw_present_arg) 124 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 125 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 126 struct drm_vmw_present_readback_arg) 127 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 129 struct drm_vmw_update_layout_arg) 130 #define DRM_IOCTL_VMW_CREATE_SHADER \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 132 struct drm_vmw_shader_create_arg) 133 #define DRM_IOCTL_VMW_UNREF_SHADER \ 134 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 135 struct drm_vmw_shader_arg) 136 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 137 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 138 union drm_vmw_gb_surface_create_arg) 139 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 141 union drm_vmw_gb_surface_reference_arg) 142 #define DRM_IOCTL_VMW_SYNCCPU \ 143 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 144 struct drm_vmw_synccpu_arg) 145 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 147 struct drm_vmw_context_arg) 148 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 149 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 150 union drm_vmw_gb_surface_create_ext_arg) 151 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 152 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 153 union drm_vmw_gb_surface_reference_ext_arg) 154 #define DRM_IOCTL_VMW_MSG \ 155 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 156 struct drm_vmw_msg_arg) 157 158 /** 159 * The core DRM version of this macro doesn't account for 160 * DRM_COMMAND_BASE. 161 */ 162 163 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 164 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 165 166 /** 167 * Ioctl definitions. 168 */ 169 170 static const struct drm_ioctl_desc vmw_ioctls[] = { 171 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 172 DRM_RENDER_ALLOW), 173 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 174 DRM_RENDER_ALLOW), 175 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 176 DRM_RENDER_ALLOW), 177 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 178 vmw_kms_cursor_bypass_ioctl, 179 DRM_MASTER), 180 181 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 182 DRM_MASTER), 183 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 184 DRM_MASTER), 185 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 186 DRM_MASTER), 187 188 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 189 DRM_RENDER_ALLOW), 190 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 191 DRM_RENDER_ALLOW), 192 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 193 DRM_RENDER_ALLOW), 194 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 197 DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, 199 DRM_RENDER_ALLOW), 200 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 201 DRM_RENDER_ALLOW), 202 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 203 vmw_fence_obj_signaled_ioctl, 204 DRM_RENDER_ALLOW), 205 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 206 DRM_RENDER_ALLOW), 207 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 208 DRM_RENDER_ALLOW), 209 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 210 DRM_RENDER_ALLOW), 211 212 /* these allow direct access to the framebuffers mark as master only */ 213 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 214 DRM_MASTER | DRM_AUTH), 215 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 216 vmw_present_readback_ioctl, 217 DRM_MASTER | DRM_AUTH), 218 /* 219 * The permissions of the below ioctl are overridden in 220 * vmw_generic_ioctl(). We require either 221 * DRM_MASTER or capable(CAP_SYS_ADMIN). 222 */ 223 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 224 vmw_kms_update_layout_ioctl, 225 DRM_RENDER_ALLOW), 226 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 227 vmw_shader_define_ioctl, 228 DRM_RENDER_ALLOW), 229 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 230 vmw_shader_destroy_ioctl, 231 DRM_RENDER_ALLOW), 232 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 233 vmw_gb_surface_define_ioctl, 234 DRM_RENDER_ALLOW), 235 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 236 vmw_gb_surface_reference_ioctl, 237 DRM_RENDER_ALLOW), 238 VMW_IOCTL_DEF(VMW_SYNCCPU, 239 vmw_user_bo_synccpu_ioctl, 240 DRM_RENDER_ALLOW), 241 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 242 vmw_extended_context_define_ioctl, 243 DRM_RENDER_ALLOW), 244 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 245 vmw_gb_surface_define_ext_ioctl, 246 DRM_RENDER_ALLOW), 247 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 248 vmw_gb_surface_reference_ext_ioctl, 249 DRM_RENDER_ALLOW), 250 VMW_IOCTL_DEF(VMW_MSG, 251 vmw_msg_ioctl, 252 DRM_RENDER_ALLOW), 253 }; 254 255 static const struct pci_device_id vmw_pci_id_list[] = { 256 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 257 {0, 0, 0} 258 }; 259 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 260 261 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 262 static int vmw_force_iommu; 263 static int vmw_restrict_iommu; 264 static int vmw_force_coherent; 265 static int vmw_restrict_dma_mask; 266 static int vmw_assume_16bpp; 267 268 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 269 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 270 void *ptr); 271 272 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 273 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 274 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 275 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 276 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 277 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 278 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 279 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 280 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 281 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 282 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 283 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 284 285 286 static void vmw_print_capabilities2(uint32_t capabilities2) 287 { 288 DRM_INFO("Capabilities2:\n"); 289 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 290 DRM_INFO(" Grow oTable.\n"); 291 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 292 DRM_INFO(" IntraSurface copy.\n"); 293 if (capabilities2 & SVGA_CAP2_DX3) 294 DRM_INFO(" DX3.\n"); 295 } 296 297 static void vmw_print_capabilities(uint32_t capabilities) 298 { 299 DRM_INFO("Capabilities:\n"); 300 if (capabilities & SVGA_CAP_RECT_COPY) 301 DRM_INFO(" Rect copy.\n"); 302 if (capabilities & SVGA_CAP_CURSOR) 303 DRM_INFO(" Cursor.\n"); 304 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 305 DRM_INFO(" Cursor bypass.\n"); 306 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 307 DRM_INFO(" Cursor bypass 2.\n"); 308 if (capabilities & SVGA_CAP_8BIT_EMULATION) 309 DRM_INFO(" 8bit emulation.\n"); 310 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 311 DRM_INFO(" Alpha cursor.\n"); 312 if (capabilities & SVGA_CAP_3D) 313 DRM_INFO(" 3D.\n"); 314 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 315 DRM_INFO(" Extended Fifo.\n"); 316 if (capabilities & SVGA_CAP_MULTIMON) 317 DRM_INFO(" Multimon.\n"); 318 if (capabilities & SVGA_CAP_PITCHLOCK) 319 DRM_INFO(" Pitchlock.\n"); 320 if (capabilities & SVGA_CAP_IRQMASK) 321 DRM_INFO(" Irq mask.\n"); 322 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 323 DRM_INFO(" Display Topology.\n"); 324 if (capabilities & SVGA_CAP_GMR) 325 DRM_INFO(" GMR.\n"); 326 if (capabilities & SVGA_CAP_TRACES) 327 DRM_INFO(" Traces.\n"); 328 if (capabilities & SVGA_CAP_GMR2) 329 DRM_INFO(" GMR2.\n"); 330 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 331 DRM_INFO(" Screen Object 2.\n"); 332 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 333 DRM_INFO(" Command Buffers.\n"); 334 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 335 DRM_INFO(" Command Buffers 2.\n"); 336 if (capabilities & SVGA_CAP_GBOBJECTS) 337 DRM_INFO(" Guest Backed Resources.\n"); 338 if (capabilities & SVGA_CAP_DX) 339 DRM_INFO(" DX Features.\n"); 340 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 341 DRM_INFO(" HP Command Queue.\n"); 342 } 343 344 /** 345 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 346 * 347 * @dev_priv: A device private structure. 348 * 349 * This function creates a small buffer object that holds the query 350 * result for dummy queries emitted as query barriers. 351 * The function will then map the first page and initialize a pending 352 * occlusion query result structure, Finally it will unmap the buffer. 353 * No interruptible waits are done within this function. 354 * 355 * Returns an error if bo creation or initialization fails. 356 */ 357 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 358 { 359 int ret; 360 struct vmw_buffer_object *vbo; 361 struct ttm_bo_kmap_obj map; 362 volatile SVGA3dQueryResult *result; 363 bool dummy; 364 365 /* 366 * Create the vbo as pinned, so that a tryreserve will 367 * immediately succeed. This is because we're the only 368 * user of the bo currently. 369 */ 370 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 371 if (!vbo) 372 return -ENOMEM; 373 374 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 375 &vmw_sys_ne_placement, false, 376 &vmw_bo_bo_free); 377 if (unlikely(ret != 0)) 378 return ret; 379 380 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 381 BUG_ON(ret != 0); 382 vmw_bo_pin_reserved(vbo, true); 383 384 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 385 if (likely(ret == 0)) { 386 result = ttm_kmap_obj_virtual(&map, &dummy); 387 result->totalSize = sizeof(*result); 388 result->state = SVGA3D_QUERYSTATE_PENDING; 389 result->result32 = 0xff; 390 ttm_bo_kunmap(&map); 391 } 392 vmw_bo_pin_reserved(vbo, false); 393 ttm_bo_unreserve(&vbo->base); 394 395 if (unlikely(ret != 0)) { 396 DRM_ERROR("Dummy query buffer map failed.\n"); 397 vmw_bo_unreference(&vbo); 398 } else 399 dev_priv->dummy_query_bo = vbo; 400 401 return ret; 402 } 403 404 /** 405 * vmw_request_device_late - Perform late device setup 406 * 407 * @dev_priv: Pointer to device private. 408 * 409 * This function performs setup of otables and enables large command 410 * buffer submission. These tasks are split out to a separate function 411 * because it reverts vmw_release_device_early and is intended to be used 412 * by an error path in the hibernation code. 413 */ 414 static int vmw_request_device_late(struct vmw_private *dev_priv) 415 { 416 int ret; 417 418 if (dev_priv->has_mob) { 419 ret = vmw_otables_setup(dev_priv); 420 if (unlikely(ret != 0)) { 421 DRM_ERROR("Unable to initialize " 422 "guest Memory OBjects.\n"); 423 return ret; 424 } 425 } 426 427 if (dev_priv->cman) { 428 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 429 256*4096, 2*4096); 430 if (ret) { 431 struct vmw_cmdbuf_man *man = dev_priv->cman; 432 433 dev_priv->cman = NULL; 434 vmw_cmdbuf_man_destroy(man); 435 } 436 } 437 438 return 0; 439 } 440 441 static int vmw_request_device(struct vmw_private *dev_priv) 442 { 443 int ret; 444 445 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 446 if (unlikely(ret != 0)) { 447 DRM_ERROR("Unable to initialize FIFO.\n"); 448 return ret; 449 } 450 vmw_fence_fifo_up(dev_priv->fman); 451 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 452 if (IS_ERR(dev_priv->cman)) { 453 dev_priv->cman = NULL; 454 dev_priv->sm_type = VMW_SM_LEGACY; 455 } 456 457 ret = vmw_request_device_late(dev_priv); 458 if (ret) 459 goto out_no_mob; 460 461 ret = vmw_dummy_query_bo_create(dev_priv); 462 if (unlikely(ret != 0)) 463 goto out_no_query_bo; 464 465 return 0; 466 467 out_no_query_bo: 468 if (dev_priv->cman) 469 vmw_cmdbuf_remove_pool(dev_priv->cman); 470 if (dev_priv->has_mob) { 471 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 472 vmw_otables_takedown(dev_priv); 473 } 474 if (dev_priv->cman) 475 vmw_cmdbuf_man_destroy(dev_priv->cman); 476 out_no_mob: 477 vmw_fence_fifo_down(dev_priv->fman); 478 vmw_fifo_release(dev_priv, &dev_priv->fifo); 479 return ret; 480 } 481 482 /** 483 * vmw_release_device_early - Early part of fifo takedown. 484 * 485 * @dev_priv: Pointer to device private struct. 486 * 487 * This is the first part of command submission takedown, to be called before 488 * buffer management is taken down. 489 */ 490 static void vmw_release_device_early(struct vmw_private *dev_priv) 491 { 492 /* 493 * Previous destructions should've released 494 * the pinned bo. 495 */ 496 497 BUG_ON(dev_priv->pinned_bo != NULL); 498 499 vmw_bo_unreference(&dev_priv->dummy_query_bo); 500 if (dev_priv->cman) 501 vmw_cmdbuf_remove_pool(dev_priv->cman); 502 503 if (dev_priv->has_mob) { 504 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 505 vmw_otables_takedown(dev_priv); 506 } 507 } 508 509 /** 510 * vmw_release_device_late - Late part of fifo takedown. 511 * 512 * @dev_priv: Pointer to device private struct. 513 * 514 * This is the last part of the command submission takedown, to be called when 515 * command submission is no longer needed. It may wait on pending fences. 516 */ 517 static void vmw_release_device_late(struct vmw_private *dev_priv) 518 { 519 vmw_fence_fifo_down(dev_priv->fman); 520 if (dev_priv->cman) 521 vmw_cmdbuf_man_destroy(dev_priv->cman); 522 523 vmw_fifo_release(dev_priv, &dev_priv->fifo); 524 } 525 526 /** 527 * Sets the initial_[width|height] fields on the given vmw_private. 528 * 529 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 530 * clamping the value to fb_max_[width|height] fields and the 531 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 532 * If the values appear to be invalid, set them to 533 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 534 */ 535 static void vmw_get_initial_size(struct vmw_private *dev_priv) 536 { 537 uint32_t width; 538 uint32_t height; 539 540 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 541 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 542 543 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 544 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 545 546 if (width > dev_priv->fb_max_width || 547 height > dev_priv->fb_max_height) { 548 549 /* 550 * This is a host error and shouldn't occur. 551 */ 552 553 width = VMW_MIN_INITIAL_WIDTH; 554 height = VMW_MIN_INITIAL_HEIGHT; 555 } 556 557 dev_priv->initial_width = width; 558 dev_priv->initial_height = height; 559 } 560 561 /** 562 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 563 * system. 564 * 565 * @dev_priv: Pointer to a struct vmw_private 566 * 567 * This functions tries to determine what actions need to be taken by the 568 * driver to make system pages visible to the device. 569 * If this function decides that DMA is not possible, it returns -EINVAL. 570 * The driver may then try to disable features of the device that require 571 * DMA. 572 */ 573 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 574 { 575 static const char *names[vmw_dma_map_max] = { 576 [vmw_dma_phys] = "Using physical TTM page addresses.", 577 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 578 [vmw_dma_map_populate] = "Caching DMA mappings.", 579 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 580 581 /* TTM currently doesn't fully support SEV encryption. */ 582 if (mem_encrypt_active()) 583 return -EINVAL; 584 585 if (vmw_force_coherent) 586 dev_priv->map_mode = vmw_dma_alloc_coherent; 587 else if (vmw_restrict_iommu) 588 dev_priv->map_mode = vmw_dma_map_bind; 589 else 590 dev_priv->map_mode = vmw_dma_map_populate; 591 592 if (!IS_ENABLED(CONFIG_DRM_TTM_DMA_PAGE_POOL) && 593 (dev_priv->map_mode == vmw_dma_alloc_coherent)) 594 return -EINVAL; 595 596 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 597 return 0; 598 } 599 600 /** 601 * vmw_dma_masks - set required page- and dma masks 602 * 603 * @dev: Pointer to struct drm-device 604 * 605 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 606 * restriction also for 64-bit systems. 607 */ 608 static int vmw_dma_masks(struct vmw_private *dev_priv) 609 { 610 struct drm_device *dev = dev_priv->dev; 611 int ret = 0; 612 613 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 614 if (dev_priv->map_mode != vmw_dma_phys && 615 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 616 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 617 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 618 } 619 620 return ret; 621 } 622 623 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 624 { 625 int ret; 626 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 627 ret = vmw_thp_init(dev_priv); 628 #else 629 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, 630 TTM_PL_FLAG_CACHED, TTM_PL_FLAG_CACHED, 631 false, dev_priv->vram_size >> PAGE_SHIFT); 632 #endif 633 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 634 return ret; 635 } 636 637 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 638 { 639 #ifdef CONFIG_TRANSPARENT_HUGEPAGE 640 vmw_thp_fini(dev_priv); 641 #else 642 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 643 #endif 644 } 645 646 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 647 { 648 struct vmw_private *dev_priv; 649 int ret; 650 uint32_t svga_id; 651 enum vmw_res_type i; 652 bool refuse_dma = false; 653 char host_log[100] = {0}; 654 655 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 656 if (unlikely(!dev_priv)) { 657 DRM_ERROR("Failed allocating a device private struct.\n"); 658 return -ENOMEM; 659 } 660 661 pci_set_master(dev->pdev); 662 663 dev_priv->dev = dev; 664 dev_priv->vmw_chipset = chipset; 665 dev_priv->last_read_seqno = (uint32_t) -100; 666 mutex_init(&dev_priv->cmdbuf_mutex); 667 mutex_init(&dev_priv->release_mutex); 668 mutex_init(&dev_priv->binding_mutex); 669 mutex_init(&dev_priv->global_kms_state_mutex); 670 ttm_lock_init(&dev_priv->reservation_sem); 671 spin_lock_init(&dev_priv->resource_lock); 672 spin_lock_init(&dev_priv->hw_lock); 673 spin_lock_init(&dev_priv->waiter_lock); 674 spin_lock_init(&dev_priv->cap_lock); 675 spin_lock_init(&dev_priv->svga_lock); 676 spin_lock_init(&dev_priv->cursor_lock); 677 678 for (i = vmw_res_context; i < vmw_res_max; ++i) { 679 idr_init(&dev_priv->res_idr[i]); 680 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 681 } 682 683 init_waitqueue_head(&dev_priv->fence_queue); 684 init_waitqueue_head(&dev_priv->fifo_queue); 685 dev_priv->fence_queue_waiters = 0; 686 dev_priv->fifo_queue_waiters = 0; 687 688 dev_priv->used_memory_size = 0; 689 690 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 691 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 692 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 693 694 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 695 696 dev_priv->enable_fb = enable_fbdev; 697 698 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 699 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 700 if (svga_id != SVGA_ID_2) { 701 ret = -ENOSYS; 702 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 703 goto out_err0; 704 } 705 706 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 707 708 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 709 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 710 } 711 712 713 ret = vmw_dma_select_mode(dev_priv); 714 if (unlikely(ret != 0)) { 715 DRM_INFO("Restricting capabilities since DMA not available.\n"); 716 refuse_dma = true; 717 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 718 DRM_INFO("Disabling 3D acceleration.\n"); 719 } 720 721 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 722 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 723 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 724 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 725 726 vmw_get_initial_size(dev_priv); 727 728 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 729 dev_priv->max_gmr_ids = 730 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 731 dev_priv->max_gmr_pages = 732 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 733 dev_priv->memory_size = 734 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 735 dev_priv->memory_size -= dev_priv->vram_size; 736 } else { 737 /* 738 * An arbitrary limit of 512MiB on surface 739 * memory. But all HWV8 hardware supports GMR2. 740 */ 741 dev_priv->memory_size = 512*1024*1024; 742 } 743 dev_priv->max_mob_pages = 0; 744 dev_priv->max_mob_size = 0; 745 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 746 uint64_t mem_size; 747 748 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 749 mem_size = vmw_read(dev_priv, 750 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 751 else 752 mem_size = 753 vmw_read(dev_priv, 754 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 755 756 /* 757 * Workaround for low memory 2D VMs to compensate for the 758 * allocation taken by fbdev 759 */ 760 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 761 mem_size *= 3; 762 763 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 764 dev_priv->prim_bb_mem = 765 vmw_read(dev_priv, 766 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 767 dev_priv->max_mob_size = 768 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 769 dev_priv->stdu_max_width = 770 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 771 dev_priv->stdu_max_height = 772 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 773 774 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 775 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 776 dev_priv->texture_max_width = vmw_read(dev_priv, 777 SVGA_REG_DEV_CAP); 778 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 779 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 780 dev_priv->texture_max_height = vmw_read(dev_priv, 781 SVGA_REG_DEV_CAP); 782 } else { 783 dev_priv->texture_max_width = 8192; 784 dev_priv->texture_max_height = 8192; 785 dev_priv->prim_bb_mem = dev_priv->vram_size; 786 } 787 788 vmw_print_capabilities(dev_priv->capabilities); 789 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 790 vmw_print_capabilities2(dev_priv->capabilities2); 791 792 ret = vmw_dma_masks(dev_priv); 793 if (unlikely(ret != 0)) 794 goto out_err0; 795 796 dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK, 797 SCATTERLIST_MAX_SEGMENT)); 798 799 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 800 DRM_INFO("Max GMR ids is %u\n", 801 (unsigned)dev_priv->max_gmr_ids); 802 DRM_INFO("Max number of GMR pages is %u\n", 803 (unsigned)dev_priv->max_gmr_pages); 804 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 805 (unsigned)dev_priv->memory_size / 1024); 806 } 807 DRM_INFO("Maximum display memory size is %u kiB\n", 808 dev_priv->prim_bb_mem / 1024); 809 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 810 dev_priv->vram_start, dev_priv->vram_size / 1024); 811 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 812 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 813 814 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 815 dev_priv->mmio_size, MEMREMAP_WB); 816 817 if (unlikely(dev_priv->mmio_virt == NULL)) { 818 ret = -ENOMEM; 819 DRM_ERROR("Failed mapping MMIO.\n"); 820 goto out_err0; 821 } 822 823 /* Need mmio memory to check for fifo pitchlock cap. */ 824 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 825 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 826 !vmw_fifo_have_pitchlock(dev_priv)) { 827 ret = -ENOSYS; 828 DRM_ERROR("Hardware has no pitchlock\n"); 829 goto out_err4; 830 } 831 832 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 833 &vmw_prime_dmabuf_ops); 834 835 if (unlikely(dev_priv->tdev == NULL)) { 836 DRM_ERROR("Unable to initialize TTM object management.\n"); 837 ret = -ENOMEM; 838 goto out_err4; 839 } 840 841 dev->dev_private = dev_priv; 842 843 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 844 dev_priv->stealth = (ret != 0); 845 if (dev_priv->stealth) { 846 /** 847 * Request at least the mmio PCI resource. 848 */ 849 850 DRM_INFO("It appears like vesafb is loaded. " 851 "Ignore above error if any.\n"); 852 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 853 if (unlikely(ret != 0)) { 854 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 855 goto out_no_device; 856 } 857 } 858 859 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 860 ret = vmw_irq_install(dev, dev->pdev->irq); 861 if (ret != 0) { 862 DRM_ERROR("Failed installing irq: %d\n", ret); 863 goto out_no_irq; 864 } 865 } 866 867 dev_priv->fman = vmw_fence_manager_init(dev_priv); 868 if (unlikely(dev_priv->fman == NULL)) { 869 ret = -ENOMEM; 870 goto out_no_fman; 871 } 872 873 drm_vma_offset_manager_init(&dev_priv->vma_manager, 874 DRM_FILE_PAGE_OFFSET_START, 875 DRM_FILE_PAGE_OFFSET_SIZE); 876 ret = ttm_bo_device_init(&dev_priv->bdev, 877 &vmw_bo_driver, 878 dev->anon_inode->i_mapping, 879 &dev_priv->vma_manager, 880 false); 881 if (unlikely(ret != 0)) { 882 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 883 goto out_no_bdev; 884 } 885 ttm_manager_type(&dev_priv->bdev, TTM_PL_SYSTEM)->available_caching = 886 TTM_PL_FLAG_CACHED; 887 888 /* 889 * Enable VRAM, but initially don't use it until SVGA is enabled and 890 * unhidden. 891 */ 892 893 ret = vmw_vram_manager_init(dev_priv); 894 if (unlikely(ret != 0)) { 895 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 896 goto out_no_vram; 897 } 898 899 /* 900 * "Guest Memory Regions" is an aperture like feature with 901 * one slot per bo. There is an upper limit of the number of 902 * slots as well as the bo size. 903 */ 904 dev_priv->has_gmr = true; 905 /* TODO: This is most likely not correct */ 906 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 907 refuse_dma || 908 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 909 DRM_INFO("No GMR memory available. " 910 "Graphics memory resources are very limited.\n"); 911 dev_priv->has_gmr = false; 912 } 913 914 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 915 dev_priv->has_mob = true; 916 917 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 918 DRM_INFO("No MOB memory available. " 919 "3D will be disabled.\n"); 920 dev_priv->has_mob = false; 921 } 922 } 923 924 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 925 spin_lock(&dev_priv->cap_lock); 926 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 927 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 928 dev_priv->sm_type = VMW_SM_4; 929 spin_unlock(&dev_priv->cap_lock); 930 } 931 932 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 933 934 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 935 if (has_sm4_context(dev_priv) && 936 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 937 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM41); 938 939 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 940 dev_priv->sm_type = VMW_SM_4_1; 941 942 if (has_sm4_1_context(dev_priv) && 943 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 944 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM5); 945 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 946 dev_priv->sm_type = VMW_SM_5; 947 } 948 } 949 950 ret = vmw_kms_init(dev_priv); 951 if (unlikely(ret != 0)) 952 goto out_no_kms; 953 vmw_overlay_init(dev_priv); 954 955 ret = vmw_request_device(dev_priv); 956 if (ret) 957 goto out_no_fifo; 958 959 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 960 ? "yes." : "no."); 961 if (dev_priv->sm_type == VMW_SM_5) 962 DRM_INFO("SM5 support available.\n"); 963 if (dev_priv->sm_type == VMW_SM_4_1) 964 DRM_INFO("SM4_1 support available.\n"); 965 if (dev_priv->sm_type == VMW_SM_4) 966 DRM_INFO("SM4 support available.\n"); 967 968 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 969 VMWGFX_REPO, VMWGFX_GIT_VERSION); 970 vmw_host_log(host_log); 971 972 memset(host_log, 0, sizeof(host_log)); 973 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 974 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 975 VMWGFX_DRIVER_PATCHLEVEL); 976 vmw_host_log(host_log); 977 978 if (dev_priv->enable_fb) { 979 vmw_fifo_resource_inc(dev_priv); 980 vmw_svga_enable(dev_priv); 981 vmw_fb_init(dev_priv); 982 } 983 984 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 985 register_pm_notifier(&dev_priv->pm_nb); 986 987 return 0; 988 989 out_no_fifo: 990 vmw_overlay_close(dev_priv); 991 vmw_kms_close(dev_priv); 992 out_no_kms: 993 if (dev_priv->has_mob) 994 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 995 if (dev_priv->has_gmr) 996 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 997 vmw_vram_manager_fini(dev_priv); 998 out_no_vram: 999 (void)ttm_bo_device_release(&dev_priv->bdev); 1000 out_no_bdev: 1001 vmw_fence_manager_takedown(dev_priv->fman); 1002 out_no_fman: 1003 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1004 vmw_irq_uninstall(dev_priv->dev); 1005 out_no_irq: 1006 if (dev_priv->stealth) 1007 pci_release_region(dev->pdev, 2); 1008 else 1009 pci_release_regions(dev->pdev); 1010 out_no_device: 1011 ttm_object_device_release(&dev_priv->tdev); 1012 out_err4: 1013 memunmap(dev_priv->mmio_virt); 1014 out_err0: 1015 for (i = vmw_res_context; i < vmw_res_max; ++i) 1016 idr_destroy(&dev_priv->res_idr[i]); 1017 1018 if (dev_priv->ctx.staged_bindings) 1019 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1020 kfree(dev_priv); 1021 return ret; 1022 } 1023 1024 static void vmw_driver_unload(struct drm_device *dev) 1025 { 1026 struct vmw_private *dev_priv = vmw_priv(dev); 1027 enum vmw_res_type i; 1028 1029 unregister_pm_notifier(&dev_priv->pm_nb); 1030 1031 if (dev_priv->ctx.res_ht_initialized) 1032 drm_ht_remove(&dev_priv->ctx.res_ht); 1033 vfree(dev_priv->ctx.cmd_bounce); 1034 if (dev_priv->enable_fb) { 1035 vmw_fb_off(dev_priv); 1036 vmw_fb_close(dev_priv); 1037 vmw_fifo_resource_dec(dev_priv); 1038 vmw_svga_disable(dev_priv); 1039 } 1040 1041 vmw_kms_close(dev_priv); 1042 vmw_overlay_close(dev_priv); 1043 1044 if (dev_priv->has_gmr) 1045 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1046 1047 vmw_release_device_early(dev_priv); 1048 if (dev_priv->has_mob) 1049 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1050 vmw_vram_manager_fini(dev_priv); 1051 (void) ttm_bo_device_release(&dev_priv->bdev); 1052 drm_vma_offset_manager_destroy(&dev_priv->vma_manager); 1053 vmw_release_device_late(dev_priv); 1054 vmw_fence_manager_takedown(dev_priv->fman); 1055 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1056 vmw_irq_uninstall(dev_priv->dev); 1057 if (dev_priv->stealth) 1058 pci_release_region(dev->pdev, 2); 1059 else 1060 pci_release_regions(dev->pdev); 1061 1062 ttm_object_device_release(&dev_priv->tdev); 1063 memunmap(dev_priv->mmio_virt); 1064 if (dev_priv->ctx.staged_bindings) 1065 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1066 1067 for (i = vmw_res_context; i < vmw_res_max; ++i) 1068 idr_destroy(&dev_priv->res_idr[i]); 1069 1070 kfree(dev_priv); 1071 } 1072 1073 static void vmw_postclose(struct drm_device *dev, 1074 struct drm_file *file_priv) 1075 { 1076 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1077 1078 ttm_object_file_release(&vmw_fp->tfile); 1079 kfree(vmw_fp); 1080 } 1081 1082 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1083 { 1084 struct vmw_private *dev_priv = vmw_priv(dev); 1085 struct vmw_fpriv *vmw_fp; 1086 int ret = -ENOMEM; 1087 1088 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1089 if (unlikely(!vmw_fp)) 1090 return ret; 1091 1092 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1093 if (unlikely(vmw_fp->tfile == NULL)) 1094 goto out_no_tfile; 1095 1096 file_priv->driver_priv = vmw_fp; 1097 1098 return 0; 1099 1100 out_no_tfile: 1101 kfree(vmw_fp); 1102 return ret; 1103 } 1104 1105 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1106 unsigned long arg, 1107 long (*ioctl_func)(struct file *, unsigned int, 1108 unsigned long)) 1109 { 1110 struct drm_file *file_priv = filp->private_data; 1111 struct drm_device *dev = file_priv->minor->dev; 1112 unsigned int nr = DRM_IOCTL_NR(cmd); 1113 unsigned int flags; 1114 1115 /* 1116 * Do extra checking on driver private ioctls. 1117 */ 1118 1119 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1120 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1121 const struct drm_ioctl_desc *ioctl = 1122 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1123 1124 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1125 return ioctl_func(filp, cmd, arg); 1126 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1127 if (!drm_is_current_master(file_priv) && 1128 !capable(CAP_SYS_ADMIN)) 1129 return -EACCES; 1130 } 1131 1132 if (unlikely(ioctl->cmd != cmd)) 1133 goto out_io_encoding; 1134 1135 flags = ioctl->flags; 1136 } else if (!drm_ioctl_flags(nr, &flags)) 1137 return -EINVAL; 1138 1139 return ioctl_func(filp, cmd, arg); 1140 1141 out_io_encoding: 1142 DRM_ERROR("Invalid command format, ioctl %d\n", 1143 nr - DRM_COMMAND_BASE); 1144 1145 return -EINVAL; 1146 } 1147 1148 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1149 unsigned long arg) 1150 { 1151 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1152 } 1153 1154 #ifdef CONFIG_COMPAT 1155 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1156 unsigned long arg) 1157 { 1158 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1159 } 1160 #endif 1161 1162 static void vmw_master_set(struct drm_device *dev, 1163 struct drm_file *file_priv, 1164 bool from_open) 1165 { 1166 /* 1167 * Inform a new master that the layout may have changed while 1168 * it was gone. 1169 */ 1170 if (!from_open) 1171 drm_sysfs_hotplug_event(dev); 1172 } 1173 1174 static void vmw_master_drop(struct drm_device *dev, 1175 struct drm_file *file_priv) 1176 { 1177 struct vmw_private *dev_priv = vmw_priv(dev); 1178 1179 vmw_kms_legacy_hotspot_clear(dev_priv); 1180 if (!dev_priv->enable_fb) 1181 vmw_svga_disable(dev_priv); 1182 } 1183 1184 /** 1185 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1186 * 1187 * @dev_priv: Pointer to device private struct. 1188 * Needs the reservation sem to be held in non-exclusive mode. 1189 */ 1190 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1191 { 1192 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1193 1194 spin_lock(&dev_priv->svga_lock); 1195 if (!ttm_resource_manager_used(man)) { 1196 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1197 ttm_resource_manager_set_used(man, true); 1198 } 1199 spin_unlock(&dev_priv->svga_lock); 1200 } 1201 1202 /** 1203 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1204 * 1205 * @dev_priv: Pointer to device private struct. 1206 */ 1207 void vmw_svga_enable(struct vmw_private *dev_priv) 1208 { 1209 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1210 __vmw_svga_enable(dev_priv); 1211 ttm_read_unlock(&dev_priv->reservation_sem); 1212 } 1213 1214 /** 1215 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1216 * 1217 * @dev_priv: Pointer to device private struct. 1218 * Needs the reservation sem to be held in exclusive mode. 1219 * Will not empty VRAM. VRAM must be emptied by caller. 1220 */ 1221 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1222 { 1223 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1224 1225 spin_lock(&dev_priv->svga_lock); 1226 if (ttm_resource_manager_used(man)) { 1227 ttm_resource_manager_set_used(man, false); 1228 vmw_write(dev_priv, SVGA_REG_ENABLE, 1229 SVGA_REG_ENABLE_HIDE | 1230 SVGA_REG_ENABLE_ENABLE); 1231 } 1232 spin_unlock(&dev_priv->svga_lock); 1233 } 1234 1235 /** 1236 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1237 * running. 1238 * 1239 * @dev_priv: Pointer to device private struct. 1240 * Will empty VRAM. 1241 */ 1242 void vmw_svga_disable(struct vmw_private *dev_priv) 1243 { 1244 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1245 /* 1246 * Disabling SVGA will turn off device modesetting capabilities, so 1247 * notify KMS about that so that it doesn't cache atomic state that 1248 * isn't valid anymore, for example crtcs turned on. 1249 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1250 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1251 * end up with lock order reversal. Thus, a master may actually perform 1252 * a new modeset just after we call vmw_kms_lost_device() and race with 1253 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1254 * to be inconsistent with the device, causing modesetting problems. 1255 * 1256 */ 1257 vmw_kms_lost_device(dev_priv->dev); 1258 ttm_write_lock(&dev_priv->reservation_sem, false); 1259 spin_lock(&dev_priv->svga_lock); 1260 if (ttm_resource_manager_used(man)) { 1261 ttm_resource_manager_set_used(man, false); 1262 spin_unlock(&dev_priv->svga_lock); 1263 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1264 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1265 vmw_write(dev_priv, SVGA_REG_ENABLE, 1266 SVGA_REG_ENABLE_HIDE | 1267 SVGA_REG_ENABLE_ENABLE); 1268 } else 1269 spin_unlock(&dev_priv->svga_lock); 1270 ttm_write_unlock(&dev_priv->reservation_sem); 1271 } 1272 1273 static void vmw_remove(struct pci_dev *pdev) 1274 { 1275 struct drm_device *dev = pci_get_drvdata(pdev); 1276 1277 drm_dev_unregister(dev); 1278 vmw_driver_unload(dev); 1279 drm_dev_put(dev); 1280 pci_disable_device(pdev); 1281 } 1282 1283 static unsigned long 1284 vmw_get_unmapped_area(struct file *file, unsigned long uaddr, 1285 unsigned long len, unsigned long pgoff, 1286 unsigned long flags) 1287 { 1288 struct drm_file *file_priv = file->private_data; 1289 struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev); 1290 1291 return drm_get_unmapped_area(file, uaddr, len, pgoff, flags, 1292 &dev_priv->vma_manager); 1293 } 1294 1295 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1296 void *ptr) 1297 { 1298 struct vmw_private *dev_priv = 1299 container_of(nb, struct vmw_private, pm_nb); 1300 1301 switch (val) { 1302 case PM_HIBERNATION_PREPARE: 1303 /* 1304 * Take the reservation sem in write mode, which will make sure 1305 * there are no other processes holding a buffer object 1306 * reservation, meaning we should be able to evict all buffer 1307 * objects if needed. 1308 * Once user-space processes have been frozen, we can release 1309 * the lock again. 1310 */ 1311 ttm_suspend_lock(&dev_priv->reservation_sem); 1312 dev_priv->suspend_locked = true; 1313 break; 1314 case PM_POST_HIBERNATION: 1315 case PM_POST_RESTORE: 1316 if (READ_ONCE(dev_priv->suspend_locked)) { 1317 dev_priv->suspend_locked = false; 1318 ttm_suspend_unlock(&dev_priv->reservation_sem); 1319 } 1320 break; 1321 default: 1322 break; 1323 } 1324 return 0; 1325 } 1326 1327 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1328 { 1329 struct drm_device *dev = pci_get_drvdata(pdev); 1330 struct vmw_private *dev_priv = vmw_priv(dev); 1331 1332 if (dev_priv->refuse_hibernation) 1333 return -EBUSY; 1334 1335 pci_save_state(pdev); 1336 pci_disable_device(pdev); 1337 pci_set_power_state(pdev, PCI_D3hot); 1338 return 0; 1339 } 1340 1341 static int vmw_pci_resume(struct pci_dev *pdev) 1342 { 1343 pci_set_power_state(pdev, PCI_D0); 1344 pci_restore_state(pdev); 1345 return pci_enable_device(pdev); 1346 } 1347 1348 static int vmw_pm_suspend(struct device *kdev) 1349 { 1350 struct pci_dev *pdev = to_pci_dev(kdev); 1351 struct pm_message dummy; 1352 1353 dummy.event = 0; 1354 1355 return vmw_pci_suspend(pdev, dummy); 1356 } 1357 1358 static int vmw_pm_resume(struct device *kdev) 1359 { 1360 struct pci_dev *pdev = to_pci_dev(kdev); 1361 1362 return vmw_pci_resume(pdev); 1363 } 1364 1365 static int vmw_pm_freeze(struct device *kdev) 1366 { 1367 struct pci_dev *pdev = to_pci_dev(kdev); 1368 struct drm_device *dev = pci_get_drvdata(pdev); 1369 struct vmw_private *dev_priv = vmw_priv(dev); 1370 int ret; 1371 1372 /* 1373 * Unlock for vmw_kms_suspend. 1374 * No user-space processes should be running now. 1375 */ 1376 ttm_suspend_unlock(&dev_priv->reservation_sem); 1377 ret = vmw_kms_suspend(dev_priv->dev); 1378 if (ret) { 1379 ttm_suspend_lock(&dev_priv->reservation_sem); 1380 DRM_ERROR("Failed to freeze modesetting.\n"); 1381 return ret; 1382 } 1383 if (dev_priv->enable_fb) 1384 vmw_fb_off(dev_priv); 1385 1386 ttm_suspend_lock(&dev_priv->reservation_sem); 1387 vmw_execbuf_release_pinned_bo(dev_priv); 1388 vmw_resource_evict_all(dev_priv); 1389 vmw_release_device_early(dev_priv); 1390 ttm_bo_swapout_all(); 1391 if (dev_priv->enable_fb) 1392 vmw_fifo_resource_dec(dev_priv); 1393 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1394 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1395 if (dev_priv->enable_fb) 1396 vmw_fifo_resource_inc(dev_priv); 1397 WARN_ON(vmw_request_device_late(dev_priv)); 1398 dev_priv->suspend_locked = false; 1399 ttm_suspend_unlock(&dev_priv->reservation_sem); 1400 if (dev_priv->suspend_state) 1401 vmw_kms_resume(dev); 1402 if (dev_priv->enable_fb) 1403 vmw_fb_on(dev_priv); 1404 return -EBUSY; 1405 } 1406 1407 vmw_fence_fifo_down(dev_priv->fman); 1408 __vmw_svga_disable(dev_priv); 1409 1410 vmw_release_device_late(dev_priv); 1411 return 0; 1412 } 1413 1414 static int vmw_pm_restore(struct device *kdev) 1415 { 1416 struct pci_dev *pdev = to_pci_dev(kdev); 1417 struct drm_device *dev = pci_get_drvdata(pdev); 1418 struct vmw_private *dev_priv = vmw_priv(dev); 1419 int ret; 1420 1421 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1422 (void) vmw_read(dev_priv, SVGA_REG_ID); 1423 1424 if (dev_priv->enable_fb) 1425 vmw_fifo_resource_inc(dev_priv); 1426 1427 ret = vmw_request_device(dev_priv); 1428 if (ret) 1429 return ret; 1430 1431 if (dev_priv->enable_fb) 1432 __vmw_svga_enable(dev_priv); 1433 1434 vmw_fence_fifo_up(dev_priv->fman); 1435 dev_priv->suspend_locked = false; 1436 ttm_suspend_unlock(&dev_priv->reservation_sem); 1437 if (dev_priv->suspend_state) 1438 vmw_kms_resume(dev_priv->dev); 1439 1440 if (dev_priv->enable_fb) 1441 vmw_fb_on(dev_priv); 1442 1443 return 0; 1444 } 1445 1446 static const struct dev_pm_ops vmw_pm_ops = { 1447 .freeze = vmw_pm_freeze, 1448 .thaw = vmw_pm_restore, 1449 .restore = vmw_pm_restore, 1450 .suspend = vmw_pm_suspend, 1451 .resume = vmw_pm_resume, 1452 }; 1453 1454 static const struct file_operations vmwgfx_driver_fops = { 1455 .owner = THIS_MODULE, 1456 .open = drm_open, 1457 .release = drm_release, 1458 .unlocked_ioctl = vmw_unlocked_ioctl, 1459 .mmap = vmw_mmap, 1460 .poll = vmw_fops_poll, 1461 .read = vmw_fops_read, 1462 #if defined(CONFIG_COMPAT) 1463 .compat_ioctl = vmw_compat_ioctl, 1464 #endif 1465 .llseek = noop_llseek, 1466 .get_unmapped_area = vmw_get_unmapped_area, 1467 }; 1468 1469 static struct drm_driver driver = { 1470 .driver_features = 1471 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC, 1472 .ioctls = vmw_ioctls, 1473 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1474 .master_set = vmw_master_set, 1475 .master_drop = vmw_master_drop, 1476 .open = vmw_driver_open, 1477 .postclose = vmw_postclose, 1478 1479 .dumb_create = vmw_dumb_create, 1480 .dumb_map_offset = vmw_dumb_map_offset, 1481 .dumb_destroy = vmw_dumb_destroy, 1482 1483 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1484 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1485 1486 .fops = &vmwgfx_driver_fops, 1487 .name = VMWGFX_DRIVER_NAME, 1488 .desc = VMWGFX_DRIVER_DESC, 1489 .date = VMWGFX_DRIVER_DATE, 1490 .major = VMWGFX_DRIVER_MAJOR, 1491 .minor = VMWGFX_DRIVER_MINOR, 1492 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1493 }; 1494 1495 static struct pci_driver vmw_pci_driver = { 1496 .name = VMWGFX_DRIVER_NAME, 1497 .id_table = vmw_pci_id_list, 1498 .probe = vmw_probe, 1499 .remove = vmw_remove, 1500 .driver = { 1501 .pm = &vmw_pm_ops 1502 } 1503 }; 1504 1505 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1506 { 1507 struct drm_device *dev; 1508 int ret; 1509 1510 ret = pci_enable_device(pdev); 1511 if (ret) 1512 return ret; 1513 1514 dev = drm_dev_alloc(&driver, &pdev->dev); 1515 if (IS_ERR(dev)) { 1516 ret = PTR_ERR(dev); 1517 goto err_pci_disable_device; 1518 } 1519 1520 dev->pdev = pdev; 1521 pci_set_drvdata(pdev, dev); 1522 1523 ret = vmw_driver_load(dev, ent->driver_data); 1524 if (ret) 1525 goto err_drm_dev_put; 1526 1527 ret = drm_dev_register(dev, ent->driver_data); 1528 if (ret) 1529 goto err_vmw_driver_unload; 1530 1531 return 0; 1532 1533 err_vmw_driver_unload: 1534 vmw_driver_unload(dev); 1535 err_drm_dev_put: 1536 drm_dev_put(dev); 1537 err_pci_disable_device: 1538 pci_disable_device(pdev); 1539 return ret; 1540 } 1541 1542 static int __init vmwgfx_init(void) 1543 { 1544 int ret; 1545 1546 if (vgacon_text_force()) 1547 return -EINVAL; 1548 1549 ret = pci_register_driver(&vmw_pci_driver); 1550 if (ret) 1551 DRM_ERROR("Failed initializing DRM.\n"); 1552 return ret; 1553 } 1554 1555 static void __exit vmwgfx_exit(void) 1556 { 1557 pci_unregister_driver(&vmw_pci_driver); 1558 } 1559 1560 module_init(vmwgfx_init); 1561 module_exit(vmwgfx_exit); 1562 1563 MODULE_AUTHOR("VMware Inc. and others"); 1564 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1565 MODULE_LICENSE("GPL and additional rights"); 1566 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1567 __stringify(VMWGFX_DRIVER_MINOR) "." 1568 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1569 "0"); 1570