1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include <linux/dma-mapping.h> 29 #include <linux/module.h> 30 #include <linux/pci.h> 31 #include <linux/cc_platform.h> 32 33 #include <drm/drm_aperture.h> 34 #include <drm/drm_drv.h> 35 #include <drm/drm_ioctl.h> 36 #include <drm/drm_sysfs.h> 37 #include <drm/drm_gem_ttm_helper.h> 38 #include <drm/ttm/ttm_bo_driver.h> 39 #include <drm/ttm/ttm_range_manager.h> 40 #include <drm/ttm/ttm_placement.h> 41 #include <generated/utsrelease.h> 42 43 #include "ttm_object.h" 44 #include "vmwgfx_binding.h" 45 #include "vmwgfx_devcaps.h" 46 #include "vmwgfx_drv.h" 47 #include "vmwgfx_mksstat.h" 48 49 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 50 51 #define VMW_MIN_INITIAL_WIDTH 800 52 #define VMW_MIN_INITIAL_HEIGHT 600 53 54 /* 55 * Fully encoded drm commands. Might move to vmw_drm.h 56 */ 57 58 #define DRM_IOCTL_VMW_GET_PARAM \ 59 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 60 struct drm_vmw_getparam_arg) 61 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 62 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 63 union drm_vmw_alloc_dmabuf_arg) 64 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 65 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 66 struct drm_vmw_unref_dmabuf_arg) 67 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 68 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 69 struct drm_vmw_cursor_bypass_arg) 70 71 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 72 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 73 struct drm_vmw_control_stream_arg) 74 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 75 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 76 struct drm_vmw_stream_arg) 77 #define DRM_IOCTL_VMW_UNREF_STREAM \ 78 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 79 struct drm_vmw_stream_arg) 80 81 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 82 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 83 struct drm_vmw_context_arg) 84 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 86 struct drm_vmw_context_arg) 87 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 88 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 89 union drm_vmw_surface_create_arg) 90 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 91 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 92 struct drm_vmw_surface_arg) 93 #define DRM_IOCTL_VMW_REF_SURFACE \ 94 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 95 union drm_vmw_surface_reference_arg) 96 #define DRM_IOCTL_VMW_EXECBUF \ 97 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 98 struct drm_vmw_execbuf_arg) 99 #define DRM_IOCTL_VMW_GET_3D_CAP \ 100 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 101 struct drm_vmw_get_3d_cap_arg) 102 #define DRM_IOCTL_VMW_FENCE_WAIT \ 103 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 104 struct drm_vmw_fence_wait_arg) 105 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 106 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 107 struct drm_vmw_fence_signaled_arg) 108 #define DRM_IOCTL_VMW_FENCE_UNREF \ 109 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 110 struct drm_vmw_fence_arg) 111 #define DRM_IOCTL_VMW_FENCE_EVENT \ 112 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 113 struct drm_vmw_fence_event_arg) 114 #define DRM_IOCTL_VMW_PRESENT \ 115 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 116 struct drm_vmw_present_arg) 117 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 118 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 119 struct drm_vmw_present_readback_arg) 120 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 121 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 122 struct drm_vmw_update_layout_arg) 123 #define DRM_IOCTL_VMW_CREATE_SHADER \ 124 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 125 struct drm_vmw_shader_create_arg) 126 #define DRM_IOCTL_VMW_UNREF_SHADER \ 127 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 128 struct drm_vmw_shader_arg) 129 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 130 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 131 union drm_vmw_gb_surface_create_arg) 132 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 133 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 134 union drm_vmw_gb_surface_reference_arg) 135 #define DRM_IOCTL_VMW_SYNCCPU \ 136 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 137 struct drm_vmw_synccpu_arg) 138 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 139 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 140 struct drm_vmw_context_arg) 141 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 142 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 143 union drm_vmw_gb_surface_create_ext_arg) 144 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 145 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 146 union drm_vmw_gb_surface_reference_ext_arg) 147 #define DRM_IOCTL_VMW_MSG \ 148 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 149 struct drm_vmw_msg_arg) 150 #define DRM_IOCTL_VMW_MKSSTAT_RESET \ 151 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) 152 #define DRM_IOCTL_VMW_MKSSTAT_ADD \ 153 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ 154 struct drm_vmw_mksstat_add_arg) 155 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ 156 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ 157 struct drm_vmw_mksstat_remove_arg) 158 159 /* 160 * Ioctl definitions. 161 */ 162 163 static const struct drm_ioctl_desc vmw_ioctls[] = { 164 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, 165 DRM_RENDER_ALLOW), 166 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, 167 DRM_RENDER_ALLOW), 168 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 169 DRM_RENDER_ALLOW), 170 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, 171 vmw_kms_cursor_bypass_ioctl, 172 DRM_MASTER), 173 174 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 175 DRM_MASTER), 176 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 177 DRM_MASTER), 178 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 179 DRM_MASTER), 180 181 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 182 DRM_RENDER_ALLOW), 183 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 184 DRM_RENDER_ALLOW), 185 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 186 DRM_RENDER_ALLOW), 187 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 188 DRM_RENDER_ALLOW), 189 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 190 DRM_RENDER_ALLOW), 191 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, 192 DRM_RENDER_ALLOW), 193 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 194 DRM_RENDER_ALLOW), 195 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, 196 vmw_fence_obj_signaled_ioctl, 197 DRM_RENDER_ALLOW), 198 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 199 DRM_RENDER_ALLOW), 200 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 201 DRM_RENDER_ALLOW), 202 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 203 DRM_RENDER_ALLOW), 204 205 /* these allow direct access to the framebuffers mark as master only */ 206 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, 207 DRM_MASTER | DRM_AUTH), 208 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, 209 vmw_present_readback_ioctl, 210 DRM_MASTER | DRM_AUTH), 211 /* 212 * The permissions of the below ioctl are overridden in 213 * vmw_generic_ioctl(). We require either 214 * DRM_MASTER or capable(CAP_SYS_ADMIN). 215 */ 216 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, 217 vmw_kms_update_layout_ioctl, 218 DRM_RENDER_ALLOW), 219 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, 220 vmw_shader_define_ioctl, 221 DRM_RENDER_ALLOW), 222 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, 223 vmw_shader_destroy_ioctl, 224 DRM_RENDER_ALLOW), 225 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, 226 vmw_gb_surface_define_ioctl, 227 DRM_RENDER_ALLOW), 228 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, 229 vmw_gb_surface_reference_ioctl, 230 DRM_RENDER_ALLOW), 231 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, 232 vmw_user_bo_synccpu_ioctl, 233 DRM_RENDER_ALLOW), 234 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, 235 vmw_extended_context_define_ioctl, 236 DRM_RENDER_ALLOW), 237 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, 238 vmw_gb_surface_define_ext_ioctl, 239 DRM_RENDER_ALLOW), 240 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, 241 vmw_gb_surface_reference_ext_ioctl, 242 DRM_RENDER_ALLOW), 243 DRM_IOCTL_DEF_DRV(VMW_MSG, 244 vmw_msg_ioctl, 245 DRM_RENDER_ALLOW), 246 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, 247 vmw_mksstat_reset_ioctl, 248 DRM_RENDER_ALLOW), 249 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, 250 vmw_mksstat_add_ioctl, 251 DRM_RENDER_ALLOW), 252 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, 253 vmw_mksstat_remove_ioctl, 254 DRM_RENDER_ALLOW), 255 }; 256 257 static const struct pci_device_id vmw_pci_id_list[] = { 258 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, 259 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, 260 { } 261 }; 262 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 263 264 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 265 static int vmw_restrict_iommu; 266 static int vmw_force_coherent; 267 static int vmw_restrict_dma_mask; 268 static int vmw_assume_16bpp; 269 270 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 271 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 272 void *ptr); 273 274 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 275 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 276 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 277 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 278 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 279 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 280 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 281 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 282 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 283 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 284 285 286 struct bitmap_name { 287 uint32 value; 288 const char *name; 289 }; 290 291 static const struct bitmap_name cap1_names[] = { 292 { SVGA_CAP_RECT_COPY, "rect copy" }, 293 { SVGA_CAP_CURSOR, "cursor" }, 294 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, 295 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, 296 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, 297 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, 298 { SVGA_CAP_3D, "3D" }, 299 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, 300 { SVGA_CAP_MULTIMON, "multimon" }, 301 { SVGA_CAP_PITCHLOCK, "pitchlock" }, 302 { SVGA_CAP_IRQMASK, "irq mask" }, 303 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, 304 { SVGA_CAP_GMR, "gmr" }, 305 { SVGA_CAP_TRACES, "traces" }, 306 { SVGA_CAP_GMR2, "gmr2" }, 307 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, 308 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, 309 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, 310 { SVGA_CAP_GBOBJECTS, "gbobject" }, 311 { SVGA_CAP_DX, "dx" }, 312 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, 313 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, 314 { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, 315 }; 316 317 318 static const struct bitmap_name cap2_names[] = { 319 { SVGA_CAP2_GROW_OTABLE, "grow otable" }, 320 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, 321 { SVGA_CAP2_DX2, "dx2" }, 322 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, 323 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, 324 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, 325 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, 326 { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, 327 { SVGA_CAP2_MSHINT, "mshint" }, 328 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, 329 { SVGA_CAP2_DX3, "dx3" }, 330 { SVGA_CAP2_FRAME_TYPE, "frame type" }, 331 { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, 332 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, 333 { SVGA_CAP2_EXTRA_REGS, "extra regs" }, 334 { SVGA_CAP2_LO_STAGING, "lo staging" }, 335 }; 336 337 static void vmw_print_bitmap(struct drm_device *drm, 338 const char *prefix, uint32_t bitmap, 339 const struct bitmap_name *bnames, 340 uint32_t num_names) 341 { 342 char buf[512]; 343 uint32_t i; 344 uint32_t offset = 0; 345 for (i = 0; i < num_names; ++i) { 346 if ((bitmap & bnames[i].value) != 0) { 347 offset += snprintf(buf + offset, 348 ARRAY_SIZE(buf) - offset, 349 "%s, ", bnames[i].name); 350 bitmap &= ~bnames[i].value; 351 } 352 } 353 354 drm_info(drm, "%s: %s\n", prefix, buf); 355 if (bitmap != 0) 356 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap); 357 } 358 359 360 static void vmw_print_sm_type(struct vmw_private *dev_priv) 361 { 362 static const char *names[] = { 363 [VMW_SM_LEGACY] = "Legacy", 364 [VMW_SM_4] = "SM4", 365 [VMW_SM_4_1] = "SM4_1", 366 [VMW_SM_5] = "SM_5", 367 [VMW_SM_5_1X] = "SM_5_1X", 368 [VMW_SM_MAX] = "Invalid" 369 }; 370 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); 371 drm_info(&dev_priv->drm, "Available shader model: %s.\n", 372 names[dev_priv->sm_type]); 373 } 374 375 /** 376 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 377 * 378 * @dev_priv: A device private structure. 379 * 380 * This function creates a small buffer object that holds the query 381 * result for dummy queries emitted as query barriers. 382 * The function will then map the first page and initialize a pending 383 * occlusion query result structure, Finally it will unmap the buffer. 384 * No interruptible waits are done within this function. 385 * 386 * Returns an error if bo creation or initialization fails. 387 */ 388 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 389 { 390 int ret; 391 struct vmw_buffer_object *vbo; 392 struct ttm_bo_kmap_obj map; 393 volatile SVGA3dQueryResult *result; 394 bool dummy; 395 396 /* 397 * Create the vbo as pinned, so that a tryreserve will 398 * immediately succeed. This is because we're the only 399 * user of the bo currently. 400 */ 401 ret = vmw_bo_create(dev_priv, PAGE_SIZE, 402 &vmw_sys_placement, false, true, 403 &vmw_bo_bo_free, &vbo); 404 if (unlikely(ret != 0)) 405 return ret; 406 407 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 408 BUG_ON(ret != 0); 409 vmw_bo_pin_reserved(vbo, true); 410 411 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 412 if (likely(ret == 0)) { 413 result = ttm_kmap_obj_virtual(&map, &dummy); 414 result->totalSize = sizeof(*result); 415 result->state = SVGA3D_QUERYSTATE_PENDING; 416 result->result32 = 0xff; 417 ttm_bo_kunmap(&map); 418 } 419 vmw_bo_pin_reserved(vbo, false); 420 ttm_bo_unreserve(&vbo->base); 421 422 if (unlikely(ret != 0)) { 423 DRM_ERROR("Dummy query buffer map failed.\n"); 424 vmw_bo_unreference(&vbo); 425 } else 426 dev_priv->dummy_query_bo = vbo; 427 428 return ret; 429 } 430 431 static int vmw_device_init(struct vmw_private *dev_priv) 432 { 433 bool uses_fb_traces = false; 434 435 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 436 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 437 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 438 439 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | 440 SVGA_REG_ENABLE_HIDE); 441 442 uses_fb_traces = !vmw_cmd_supported(dev_priv) && 443 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; 444 445 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); 446 dev_priv->fifo = vmw_fifo_create(dev_priv); 447 if (IS_ERR(dev_priv->fifo)) { 448 int err = PTR_ERR(dev_priv->fifo); 449 dev_priv->fifo = NULL; 450 return err; 451 } else if (!dev_priv->fifo) { 452 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); 453 } 454 455 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); 456 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); 457 return 0; 458 } 459 460 static void vmw_device_fini(struct vmw_private *vmw) 461 { 462 /* 463 * Legacy sync 464 */ 465 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 466 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) 467 ; 468 469 vmw->last_read_seqno = vmw_fence_read(vmw); 470 471 vmw_write(vmw, SVGA_REG_CONFIG_DONE, 472 vmw->config_done_state); 473 vmw_write(vmw, SVGA_REG_ENABLE, 474 vmw->enable_state); 475 vmw_write(vmw, SVGA_REG_TRACES, 476 vmw->traces_state); 477 478 vmw_fifo_destroy(vmw); 479 } 480 481 /** 482 * vmw_request_device_late - Perform late device setup 483 * 484 * @dev_priv: Pointer to device private. 485 * 486 * This function performs setup of otables and enables large command 487 * buffer submission. These tasks are split out to a separate function 488 * because it reverts vmw_release_device_early and is intended to be used 489 * by an error path in the hibernation code. 490 */ 491 static int vmw_request_device_late(struct vmw_private *dev_priv) 492 { 493 int ret; 494 495 if (dev_priv->has_mob) { 496 ret = vmw_otables_setup(dev_priv); 497 if (unlikely(ret != 0)) { 498 DRM_ERROR("Unable to initialize " 499 "guest Memory OBjects.\n"); 500 return ret; 501 } 502 } 503 504 if (dev_priv->cman) { 505 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096); 506 if (ret) { 507 struct vmw_cmdbuf_man *man = dev_priv->cman; 508 509 dev_priv->cman = NULL; 510 vmw_cmdbuf_man_destroy(man); 511 } 512 } 513 514 return 0; 515 } 516 517 static int vmw_request_device(struct vmw_private *dev_priv) 518 { 519 int ret; 520 521 ret = vmw_device_init(dev_priv); 522 if (unlikely(ret != 0)) { 523 DRM_ERROR("Unable to initialize the device.\n"); 524 return ret; 525 } 526 vmw_fence_fifo_up(dev_priv->fman); 527 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 528 if (IS_ERR(dev_priv->cman)) { 529 dev_priv->cman = NULL; 530 dev_priv->sm_type = VMW_SM_LEGACY; 531 } 532 533 ret = vmw_request_device_late(dev_priv); 534 if (ret) 535 goto out_no_mob; 536 537 ret = vmw_dummy_query_bo_create(dev_priv); 538 if (unlikely(ret != 0)) 539 goto out_no_query_bo; 540 541 return 0; 542 543 out_no_query_bo: 544 if (dev_priv->cman) 545 vmw_cmdbuf_remove_pool(dev_priv->cman); 546 if (dev_priv->has_mob) { 547 struct ttm_resource_manager *man; 548 549 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 550 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 551 vmw_otables_takedown(dev_priv); 552 } 553 if (dev_priv->cman) 554 vmw_cmdbuf_man_destroy(dev_priv->cman); 555 out_no_mob: 556 vmw_fence_fifo_down(dev_priv->fman); 557 vmw_device_fini(dev_priv); 558 return ret; 559 } 560 561 /** 562 * vmw_release_device_early - Early part of fifo takedown. 563 * 564 * @dev_priv: Pointer to device private struct. 565 * 566 * This is the first part of command submission takedown, to be called before 567 * buffer management is taken down. 568 */ 569 static void vmw_release_device_early(struct vmw_private *dev_priv) 570 { 571 /* 572 * Previous destructions should've released 573 * the pinned bo. 574 */ 575 576 BUG_ON(dev_priv->pinned_bo != NULL); 577 578 vmw_bo_unreference(&dev_priv->dummy_query_bo); 579 if (dev_priv->cman) 580 vmw_cmdbuf_remove_pool(dev_priv->cman); 581 582 if (dev_priv->has_mob) { 583 struct ttm_resource_manager *man; 584 585 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 586 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 587 vmw_otables_takedown(dev_priv); 588 } 589 } 590 591 /** 592 * vmw_release_device_late - Late part of fifo takedown. 593 * 594 * @dev_priv: Pointer to device private struct. 595 * 596 * This is the last part of the command submission takedown, to be called when 597 * command submission is no longer needed. It may wait on pending fences. 598 */ 599 static void vmw_release_device_late(struct vmw_private *dev_priv) 600 { 601 vmw_fence_fifo_down(dev_priv->fman); 602 if (dev_priv->cman) 603 vmw_cmdbuf_man_destroy(dev_priv->cman); 604 605 vmw_device_fini(dev_priv); 606 } 607 608 /* 609 * Sets the initial_[width|height] fields on the given vmw_private. 610 * 611 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 612 * clamping the value to fb_max_[width|height] fields and the 613 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 614 * If the values appear to be invalid, set them to 615 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 616 */ 617 static void vmw_get_initial_size(struct vmw_private *dev_priv) 618 { 619 uint32_t width; 620 uint32_t height; 621 622 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 623 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 624 625 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 626 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 627 628 if (width > dev_priv->fb_max_width || 629 height > dev_priv->fb_max_height) { 630 631 /* 632 * This is a host error and shouldn't occur. 633 */ 634 635 width = VMW_MIN_INITIAL_WIDTH; 636 height = VMW_MIN_INITIAL_HEIGHT; 637 } 638 639 dev_priv->initial_width = width; 640 dev_priv->initial_height = height; 641 } 642 643 /** 644 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 645 * system. 646 * 647 * @dev_priv: Pointer to a struct vmw_private 648 * 649 * This functions tries to determine what actions need to be taken by the 650 * driver to make system pages visible to the device. 651 * If this function decides that DMA is not possible, it returns -EINVAL. 652 * The driver may then try to disable features of the device that require 653 * DMA. 654 */ 655 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 656 { 657 static const char *names[vmw_dma_map_max] = { 658 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 659 [vmw_dma_map_populate] = "Caching DMA mappings.", 660 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 661 662 /* TTM currently doesn't fully support SEV encryption. */ 663 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT)) 664 return -EINVAL; 665 666 if (vmw_force_coherent) 667 dev_priv->map_mode = vmw_dma_alloc_coherent; 668 else if (vmw_restrict_iommu) 669 dev_priv->map_mode = vmw_dma_map_bind; 670 else 671 dev_priv->map_mode = vmw_dma_map_populate; 672 673 drm_info(&dev_priv->drm, 674 "DMA map mode: %s\n", names[dev_priv->map_mode]); 675 return 0; 676 } 677 678 /** 679 * vmw_dma_masks - set required page- and dma masks 680 * 681 * @dev_priv: Pointer to struct drm-device 682 * 683 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 684 * restriction also for 64-bit systems. 685 */ 686 static int vmw_dma_masks(struct vmw_private *dev_priv) 687 { 688 struct drm_device *dev = &dev_priv->drm; 689 int ret = 0; 690 691 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 692 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { 693 drm_info(&dev_priv->drm, 694 "Restricting DMA addresses to 44 bits.\n"); 695 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 696 } 697 698 return ret; 699 } 700 701 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 702 { 703 int ret; 704 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 705 dev_priv->vram_size >> PAGE_SHIFT); 706 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 707 return ret; 708 } 709 710 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 711 { 712 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 713 } 714 715 static int vmw_setup_pci_resources(struct vmw_private *dev, 716 u32 pci_id) 717 { 718 resource_size_t rmmio_start; 719 resource_size_t rmmio_size; 720 resource_size_t fifo_start; 721 resource_size_t fifo_size; 722 int ret; 723 struct pci_dev *pdev = to_pci_dev(dev->drm.dev); 724 725 pci_set_master(pdev); 726 727 ret = pci_request_regions(pdev, "vmwgfx probe"); 728 if (ret) 729 return ret; 730 731 dev->pci_id = pci_id; 732 if (pci_id == VMWGFX_PCI_ID_SVGA3) { 733 rmmio_start = pci_resource_start(pdev, 0); 734 rmmio_size = pci_resource_len(pdev, 0); 735 dev->vram_start = pci_resource_start(pdev, 2); 736 dev->vram_size = pci_resource_len(pdev, 2); 737 738 drm_info(&dev->drm, 739 "Register MMIO at 0x%pa size is %llu kiB\n", 740 &rmmio_start, (uint64_t)rmmio_size / 1024); 741 dev->rmmio = devm_ioremap(dev->drm.dev, 742 rmmio_start, 743 rmmio_size); 744 if (!dev->rmmio) { 745 drm_err(&dev->drm, 746 "Failed mapping registers mmio memory.\n"); 747 pci_release_regions(pdev); 748 return -ENOMEM; 749 } 750 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { 751 dev->io_start = pci_resource_start(pdev, 0); 752 dev->vram_start = pci_resource_start(pdev, 1); 753 dev->vram_size = pci_resource_len(pdev, 1); 754 fifo_start = pci_resource_start(pdev, 2); 755 fifo_size = pci_resource_len(pdev, 2); 756 757 drm_info(&dev->drm, 758 "FIFO at %pa size is %llu kiB\n", 759 &fifo_start, (uint64_t)fifo_size / 1024); 760 dev->fifo_mem = devm_memremap(dev->drm.dev, 761 fifo_start, 762 fifo_size, 763 MEMREMAP_WB); 764 765 if (IS_ERR(dev->fifo_mem)) { 766 drm_err(&dev->drm, 767 "Failed mapping FIFO memory.\n"); 768 pci_release_regions(pdev); 769 return PTR_ERR(dev->fifo_mem); 770 } 771 } else { 772 pci_release_regions(pdev); 773 return -EINVAL; 774 } 775 776 /* 777 * This is approximate size of the vram, the exact size will only 778 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource 779 * size will be equal to or bigger than the size reported by 780 * SVGA_REG_VRAM_SIZE. 781 */ 782 drm_info(&dev->drm, 783 "VRAM at %pa size is %llu kiB\n", 784 &dev->vram_start, (uint64_t)dev->vram_size / 1024); 785 786 return 0; 787 } 788 789 static int vmw_detect_version(struct vmw_private *dev) 790 { 791 uint32_t svga_id; 792 793 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? 794 SVGA_ID_3 : SVGA_ID_2); 795 svga_id = vmw_read(dev, SVGA_REG_ID); 796 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { 797 drm_err(&dev->drm, 798 "Unsupported SVGA ID 0x%x on chipset 0x%x\n", 799 svga_id, dev->pci_id); 800 return -ENOSYS; 801 } 802 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); 803 drm_info(&dev->drm, 804 "Running on SVGA version %d.\n", (svga_id & 0xff)); 805 return 0; 806 } 807 808 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 809 { 810 int ret; 811 enum vmw_res_type i; 812 bool refuse_dma = false; 813 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 814 815 dev_priv->drm.dev_private = dev_priv; 816 817 mutex_init(&dev_priv->cmdbuf_mutex); 818 mutex_init(&dev_priv->binding_mutex); 819 spin_lock_init(&dev_priv->resource_lock); 820 spin_lock_init(&dev_priv->hw_lock); 821 spin_lock_init(&dev_priv->waiter_lock); 822 spin_lock_init(&dev_priv->cursor_lock); 823 824 ret = vmw_setup_pci_resources(dev_priv, pci_id); 825 if (ret) 826 return ret; 827 ret = vmw_detect_version(dev_priv); 828 if (ret) 829 goto out_no_pci_or_version; 830 831 832 for (i = vmw_res_context; i < vmw_res_max; ++i) { 833 idr_init_base(&dev_priv->res_idr[i], 1); 834 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 835 } 836 837 init_waitqueue_head(&dev_priv->fence_queue); 838 init_waitqueue_head(&dev_priv->fifo_queue); 839 dev_priv->fence_queue_waiters = 0; 840 dev_priv->fifo_queue_waiters = 0; 841 842 dev_priv->used_memory_size = 0; 843 844 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 845 846 dev_priv->enable_fb = enable_fbdev; 847 848 849 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 850 851 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 852 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 853 } 854 855 856 ret = vmw_dma_select_mode(dev_priv); 857 if (unlikely(ret != 0)) { 858 drm_info(&dev_priv->drm, 859 "Restricting capabilities since DMA not available.\n"); 860 refuse_dma = true; 861 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 862 drm_info(&dev_priv->drm, 863 "Disabling 3D acceleration.\n"); 864 } 865 866 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 867 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 868 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 869 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 870 871 vmw_get_initial_size(dev_priv); 872 873 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 874 dev_priv->max_gmr_ids = 875 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 876 dev_priv->max_gmr_pages = 877 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 878 dev_priv->memory_size = 879 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 880 dev_priv->memory_size -= dev_priv->vram_size; 881 } else { 882 /* 883 * An arbitrary limit of 512MiB on surface 884 * memory. But all HWV8 hardware supports GMR2. 885 */ 886 dev_priv->memory_size = 512*1024*1024; 887 } 888 dev_priv->max_mob_pages = 0; 889 dev_priv->max_mob_size = 0; 890 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 891 uint64_t mem_size; 892 893 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 894 mem_size = vmw_read(dev_priv, 895 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 896 else 897 mem_size = 898 vmw_read(dev_priv, 899 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 900 901 /* 902 * Workaround for low memory 2D VMs to compensate for the 903 * allocation taken by fbdev 904 */ 905 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 906 mem_size *= 3; 907 908 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 909 dev_priv->max_primary_mem = 910 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM); 911 dev_priv->max_mob_size = 912 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 913 dev_priv->stdu_max_width = 914 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 915 dev_priv->stdu_max_height = 916 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 917 918 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 919 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 920 dev_priv->texture_max_width = vmw_read(dev_priv, 921 SVGA_REG_DEV_CAP); 922 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 923 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 924 dev_priv->texture_max_height = vmw_read(dev_priv, 925 SVGA_REG_DEV_CAP); 926 } else { 927 dev_priv->texture_max_width = 8192; 928 dev_priv->texture_max_height = 8192; 929 dev_priv->max_primary_mem = dev_priv->vram_size; 930 } 931 drm_info(&dev_priv->drm, 932 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n", 933 (u64)dev_priv->vram_size / 1024, 934 (u64)dev_priv->fifo_mem_size / 1024, 935 dev_priv->memory_size / 1024); 936 937 drm_info(&dev_priv->drm, 938 "MOB limits: max mob size = %u kB, max mob pages = %u\n", 939 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); 940 941 vmw_print_bitmap(&dev_priv->drm, "Capabilities", 942 dev_priv->capabilities, 943 cap1_names, ARRAY_SIZE(cap1_names)); 944 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 945 vmw_print_bitmap(&dev_priv->drm, "Capabilities2", 946 dev_priv->capabilities2, 947 cap2_names, ARRAY_SIZE(cap2_names)); 948 949 ret = vmw_dma_masks(dev_priv); 950 if (unlikely(ret != 0)) 951 goto out_err0; 952 953 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX); 954 955 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 956 drm_info(&dev_priv->drm, 957 "Max GMR ids is %u\n", 958 (unsigned)dev_priv->max_gmr_ids); 959 drm_info(&dev_priv->drm, 960 "Max number of GMR pages is %u\n", 961 (unsigned)dev_priv->max_gmr_pages); 962 } 963 drm_info(&dev_priv->drm, 964 "Maximum display memory size is %llu kiB\n", 965 (uint64_t)dev_priv->max_primary_mem / 1024); 966 967 /* Need mmio memory to check for fifo pitchlock cap. */ 968 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 969 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 970 !vmw_fifo_have_pitchlock(dev_priv)) { 971 ret = -ENOSYS; 972 DRM_ERROR("Hardware has no pitchlock\n"); 973 goto out_err0; 974 } 975 976 dev_priv->tdev = ttm_object_device_init(12, &vmw_prime_dmabuf_ops); 977 978 if (unlikely(dev_priv->tdev == NULL)) { 979 drm_err(&dev_priv->drm, 980 "Unable to initialize TTM object management.\n"); 981 ret = -ENOMEM; 982 goto out_err0; 983 } 984 985 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 986 ret = vmw_irq_install(&dev_priv->drm, pdev->irq); 987 if (ret != 0) { 988 drm_err(&dev_priv->drm, 989 "Failed installing irq: %d\n", ret); 990 goto out_no_irq; 991 } 992 } 993 994 dev_priv->fman = vmw_fence_manager_init(dev_priv); 995 if (unlikely(dev_priv->fman == NULL)) { 996 ret = -ENOMEM; 997 goto out_no_fman; 998 } 999 1000 drm_vma_offset_manager_init(&dev_priv->vma_manager, 1001 DRM_FILE_PAGE_OFFSET_START, 1002 DRM_FILE_PAGE_OFFSET_SIZE); 1003 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver, 1004 dev_priv->drm.dev, 1005 dev_priv->drm.anon_inode->i_mapping, 1006 &dev_priv->vma_manager, 1007 dev_priv->map_mode == vmw_dma_alloc_coherent, 1008 false); 1009 if (unlikely(ret != 0)) { 1010 drm_err(&dev_priv->drm, 1011 "Failed initializing TTM buffer object driver.\n"); 1012 goto out_no_bdev; 1013 } 1014 1015 /* 1016 * Enable VRAM, but initially don't use it until SVGA is enabled and 1017 * unhidden. 1018 */ 1019 1020 ret = vmw_vram_manager_init(dev_priv); 1021 if (unlikely(ret != 0)) { 1022 drm_err(&dev_priv->drm, 1023 "Failed initializing memory manager for VRAM.\n"); 1024 goto out_no_vram; 1025 } 1026 1027 ret = vmw_devcaps_create(dev_priv); 1028 if (unlikely(ret != 0)) { 1029 drm_err(&dev_priv->drm, 1030 "Failed initializing device caps.\n"); 1031 goto out_no_vram; 1032 } 1033 1034 /* 1035 * "Guest Memory Regions" is an aperture like feature with 1036 * one slot per bo. There is an upper limit of the number of 1037 * slots as well as the bo size. 1038 */ 1039 dev_priv->has_gmr = true; 1040 /* TODO: This is most likely not correct */ 1041 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 1042 refuse_dma || 1043 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 1044 drm_info(&dev_priv->drm, 1045 "No GMR memory available. " 1046 "Graphics memory resources are very limited.\n"); 1047 dev_priv->has_gmr = false; 1048 } 1049 1050 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 1051 dev_priv->has_mob = true; 1052 1053 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 1054 drm_info(&dev_priv->drm, 1055 "No MOB memory available. " 1056 "3D will be disabled.\n"); 1057 dev_priv->has_mob = false; 1058 } 1059 if (vmw_sys_man_init(dev_priv) != 0) { 1060 drm_info(&dev_priv->drm, 1061 "No MOB page table memory available. " 1062 "3D will be disabled.\n"); 1063 dev_priv->has_mob = false; 1064 } 1065 } 1066 1067 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 1068 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) 1069 dev_priv->sm_type = VMW_SM_4; 1070 } 1071 1072 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 1073 if (has_sm4_context(dev_priv) && 1074 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 1075 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41)) 1076 dev_priv->sm_type = VMW_SM_4_1; 1077 if (has_sm4_1_context(dev_priv) && 1078 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 1079 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) { 1080 dev_priv->sm_type = VMW_SM_5; 1081 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43)) 1082 dev_priv->sm_type = VMW_SM_5_1X; 1083 } 1084 } 1085 } 1086 1087 ret = vmw_kms_init(dev_priv); 1088 if (unlikely(ret != 0)) 1089 goto out_no_kms; 1090 vmw_overlay_init(dev_priv); 1091 1092 ret = vmw_request_device(dev_priv); 1093 if (ret) 1094 goto out_no_fifo; 1095 1096 vmw_print_sm_type(dev_priv); 1097 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)", 1098 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 1099 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); 1100 1101 if (dev_priv->enable_fb) { 1102 vmw_fifo_resource_inc(dev_priv); 1103 vmw_svga_enable(dev_priv); 1104 vmw_fb_init(dev_priv); 1105 } 1106 1107 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 1108 register_pm_notifier(&dev_priv->pm_nb); 1109 1110 return 0; 1111 1112 out_no_fifo: 1113 vmw_overlay_close(dev_priv); 1114 vmw_kms_close(dev_priv); 1115 out_no_kms: 1116 if (dev_priv->has_mob) { 1117 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1118 vmw_sys_man_fini(dev_priv); 1119 } 1120 if (dev_priv->has_gmr) 1121 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1122 vmw_devcaps_destroy(dev_priv); 1123 vmw_vram_manager_fini(dev_priv); 1124 out_no_vram: 1125 ttm_device_fini(&dev_priv->bdev); 1126 out_no_bdev: 1127 vmw_fence_manager_takedown(dev_priv->fman); 1128 out_no_fman: 1129 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1130 vmw_irq_uninstall(&dev_priv->drm); 1131 out_no_irq: 1132 ttm_object_device_release(&dev_priv->tdev); 1133 out_err0: 1134 for (i = vmw_res_context; i < vmw_res_max; ++i) 1135 idr_destroy(&dev_priv->res_idr[i]); 1136 1137 if (dev_priv->ctx.staged_bindings) 1138 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1139 out_no_pci_or_version: 1140 pci_release_regions(pdev); 1141 return ret; 1142 } 1143 1144 static void vmw_driver_unload(struct drm_device *dev) 1145 { 1146 struct vmw_private *dev_priv = vmw_priv(dev); 1147 struct pci_dev *pdev = to_pci_dev(dev->dev); 1148 enum vmw_res_type i; 1149 1150 unregister_pm_notifier(&dev_priv->pm_nb); 1151 1152 if (dev_priv->ctx.res_ht_initialized) 1153 vmwgfx_ht_remove(&dev_priv->ctx.res_ht); 1154 vfree(dev_priv->ctx.cmd_bounce); 1155 if (dev_priv->enable_fb) { 1156 vmw_fb_off(dev_priv); 1157 vmw_fb_close(dev_priv); 1158 vmw_fifo_resource_dec(dev_priv); 1159 vmw_svga_disable(dev_priv); 1160 } 1161 1162 vmw_kms_close(dev_priv); 1163 vmw_overlay_close(dev_priv); 1164 1165 if (dev_priv->has_gmr) 1166 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1167 1168 vmw_release_device_early(dev_priv); 1169 if (dev_priv->has_mob) { 1170 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1171 vmw_sys_man_fini(dev_priv); 1172 } 1173 vmw_devcaps_destroy(dev_priv); 1174 vmw_vram_manager_fini(dev_priv); 1175 ttm_device_fini(&dev_priv->bdev); 1176 drm_vma_offset_manager_destroy(&dev_priv->vma_manager); 1177 vmw_release_device_late(dev_priv); 1178 vmw_fence_manager_takedown(dev_priv->fman); 1179 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1180 vmw_irq_uninstall(&dev_priv->drm); 1181 1182 ttm_object_device_release(&dev_priv->tdev); 1183 if (dev_priv->ctx.staged_bindings) 1184 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1185 1186 for (i = vmw_res_context; i < vmw_res_max; ++i) 1187 idr_destroy(&dev_priv->res_idr[i]); 1188 1189 vmw_mksstat_remove_all(dev_priv); 1190 1191 pci_release_regions(pdev); 1192 } 1193 1194 static void vmw_postclose(struct drm_device *dev, 1195 struct drm_file *file_priv) 1196 { 1197 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1198 1199 ttm_object_file_release(&vmw_fp->tfile); 1200 kfree(vmw_fp); 1201 } 1202 1203 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1204 { 1205 struct vmw_private *dev_priv = vmw_priv(dev); 1206 struct vmw_fpriv *vmw_fp; 1207 int ret = -ENOMEM; 1208 1209 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1210 if (unlikely(!vmw_fp)) 1211 return ret; 1212 1213 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1214 if (unlikely(vmw_fp->tfile == NULL)) 1215 goto out_no_tfile; 1216 1217 file_priv->driver_priv = vmw_fp; 1218 1219 return 0; 1220 1221 out_no_tfile: 1222 kfree(vmw_fp); 1223 return ret; 1224 } 1225 1226 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1227 unsigned long arg, 1228 long (*ioctl_func)(struct file *, unsigned int, 1229 unsigned long)) 1230 { 1231 struct drm_file *file_priv = filp->private_data; 1232 struct drm_device *dev = file_priv->minor->dev; 1233 unsigned int nr = DRM_IOCTL_NR(cmd); 1234 unsigned int flags; 1235 1236 /* 1237 * Do extra checking on driver private ioctls. 1238 */ 1239 1240 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1241 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1242 const struct drm_ioctl_desc *ioctl = 1243 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1244 1245 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1246 return ioctl_func(filp, cmd, arg); 1247 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1248 if (!drm_is_current_master(file_priv) && 1249 !capable(CAP_SYS_ADMIN)) 1250 return -EACCES; 1251 } 1252 1253 if (unlikely(ioctl->cmd != cmd)) 1254 goto out_io_encoding; 1255 1256 flags = ioctl->flags; 1257 } else if (!drm_ioctl_flags(nr, &flags)) 1258 return -EINVAL; 1259 1260 return ioctl_func(filp, cmd, arg); 1261 1262 out_io_encoding: 1263 DRM_ERROR("Invalid command format, ioctl %d\n", 1264 nr - DRM_COMMAND_BASE); 1265 1266 return -EINVAL; 1267 } 1268 1269 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1270 unsigned long arg) 1271 { 1272 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1273 } 1274 1275 #ifdef CONFIG_COMPAT 1276 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1277 unsigned long arg) 1278 { 1279 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1280 } 1281 #endif 1282 1283 static void vmw_master_set(struct drm_device *dev, 1284 struct drm_file *file_priv, 1285 bool from_open) 1286 { 1287 /* 1288 * Inform a new master that the layout may have changed while 1289 * it was gone. 1290 */ 1291 if (!from_open) 1292 drm_sysfs_hotplug_event(dev); 1293 } 1294 1295 static void vmw_master_drop(struct drm_device *dev, 1296 struct drm_file *file_priv) 1297 { 1298 struct vmw_private *dev_priv = vmw_priv(dev); 1299 1300 vmw_kms_legacy_hotspot_clear(dev_priv); 1301 if (!dev_priv->enable_fb) 1302 vmw_svga_disable(dev_priv); 1303 } 1304 1305 /** 1306 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1307 * 1308 * @dev_priv: Pointer to device private struct. 1309 * Needs the reservation sem to be held in non-exclusive mode. 1310 */ 1311 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1312 { 1313 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1314 1315 if (!ttm_resource_manager_used(man)) { 1316 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE); 1317 ttm_resource_manager_set_used(man, true); 1318 } 1319 } 1320 1321 /** 1322 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1323 * 1324 * @dev_priv: Pointer to device private struct. 1325 */ 1326 void vmw_svga_enable(struct vmw_private *dev_priv) 1327 { 1328 __vmw_svga_enable(dev_priv); 1329 } 1330 1331 /** 1332 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1333 * 1334 * @dev_priv: Pointer to device private struct. 1335 * Needs the reservation sem to be held in exclusive mode. 1336 * Will not empty VRAM. VRAM must be emptied by caller. 1337 */ 1338 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1339 { 1340 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1341 1342 if (ttm_resource_manager_used(man)) { 1343 ttm_resource_manager_set_used(man, false); 1344 vmw_write(dev_priv, SVGA_REG_ENABLE, 1345 SVGA_REG_ENABLE_HIDE | 1346 SVGA_REG_ENABLE_ENABLE); 1347 } 1348 } 1349 1350 /** 1351 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1352 * running. 1353 * 1354 * @dev_priv: Pointer to device private struct. 1355 * Will empty VRAM. 1356 */ 1357 void vmw_svga_disable(struct vmw_private *dev_priv) 1358 { 1359 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1360 /* 1361 * Disabling SVGA will turn off device modesetting capabilities, so 1362 * notify KMS about that so that it doesn't cache atomic state that 1363 * isn't valid anymore, for example crtcs turned on. 1364 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1365 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1366 * end up with lock order reversal. Thus, a master may actually perform 1367 * a new modeset just after we call vmw_kms_lost_device() and race with 1368 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1369 * to be inconsistent with the device, causing modesetting problems. 1370 * 1371 */ 1372 vmw_kms_lost_device(&dev_priv->drm); 1373 if (ttm_resource_manager_used(man)) { 1374 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1375 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1376 ttm_resource_manager_set_used(man, false); 1377 vmw_write(dev_priv, SVGA_REG_ENABLE, 1378 SVGA_REG_ENABLE_HIDE | 1379 SVGA_REG_ENABLE_ENABLE); 1380 } 1381 } 1382 1383 static void vmw_remove(struct pci_dev *pdev) 1384 { 1385 struct drm_device *dev = pci_get_drvdata(pdev); 1386 1387 drm_dev_unregister(dev); 1388 vmw_driver_unload(dev); 1389 } 1390 1391 static unsigned long 1392 vmw_get_unmapped_area(struct file *file, unsigned long uaddr, 1393 unsigned long len, unsigned long pgoff, 1394 unsigned long flags) 1395 { 1396 struct drm_file *file_priv = file->private_data; 1397 struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev); 1398 1399 return drm_get_unmapped_area(file, uaddr, len, pgoff, flags, 1400 &dev_priv->vma_manager); 1401 } 1402 1403 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1404 void *ptr) 1405 { 1406 struct vmw_private *dev_priv = 1407 container_of(nb, struct vmw_private, pm_nb); 1408 1409 switch (val) { 1410 case PM_HIBERNATION_PREPARE: 1411 /* 1412 * Take the reservation sem in write mode, which will make sure 1413 * there are no other processes holding a buffer object 1414 * reservation, meaning we should be able to evict all buffer 1415 * objects if needed. 1416 * Once user-space processes have been frozen, we can release 1417 * the lock again. 1418 */ 1419 dev_priv->suspend_locked = true; 1420 break; 1421 case PM_POST_HIBERNATION: 1422 case PM_POST_RESTORE: 1423 if (READ_ONCE(dev_priv->suspend_locked)) { 1424 dev_priv->suspend_locked = false; 1425 } 1426 break; 1427 default: 1428 break; 1429 } 1430 return 0; 1431 } 1432 1433 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1434 { 1435 struct drm_device *dev = pci_get_drvdata(pdev); 1436 struct vmw_private *dev_priv = vmw_priv(dev); 1437 1438 if (dev_priv->refuse_hibernation) 1439 return -EBUSY; 1440 1441 pci_save_state(pdev); 1442 pci_disable_device(pdev); 1443 pci_set_power_state(pdev, PCI_D3hot); 1444 return 0; 1445 } 1446 1447 static int vmw_pci_resume(struct pci_dev *pdev) 1448 { 1449 pci_set_power_state(pdev, PCI_D0); 1450 pci_restore_state(pdev); 1451 return pci_enable_device(pdev); 1452 } 1453 1454 static int vmw_pm_suspend(struct device *kdev) 1455 { 1456 struct pci_dev *pdev = to_pci_dev(kdev); 1457 struct pm_message dummy; 1458 1459 dummy.event = 0; 1460 1461 return vmw_pci_suspend(pdev, dummy); 1462 } 1463 1464 static int vmw_pm_resume(struct device *kdev) 1465 { 1466 struct pci_dev *pdev = to_pci_dev(kdev); 1467 1468 return vmw_pci_resume(pdev); 1469 } 1470 1471 static int vmw_pm_freeze(struct device *kdev) 1472 { 1473 struct pci_dev *pdev = to_pci_dev(kdev); 1474 struct drm_device *dev = pci_get_drvdata(pdev); 1475 struct vmw_private *dev_priv = vmw_priv(dev); 1476 struct ttm_operation_ctx ctx = { 1477 .interruptible = false, 1478 .no_wait_gpu = false 1479 }; 1480 int ret; 1481 1482 /* 1483 * No user-space processes should be running now. 1484 */ 1485 ret = vmw_kms_suspend(&dev_priv->drm); 1486 if (ret) { 1487 DRM_ERROR("Failed to freeze modesetting.\n"); 1488 return ret; 1489 } 1490 if (dev_priv->enable_fb) 1491 vmw_fb_off(dev_priv); 1492 1493 vmw_execbuf_release_pinned_bo(dev_priv); 1494 vmw_resource_evict_all(dev_priv); 1495 vmw_release_device_early(dev_priv); 1496 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0); 1497 if (dev_priv->enable_fb) 1498 vmw_fifo_resource_dec(dev_priv); 1499 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1500 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1501 if (dev_priv->enable_fb) 1502 vmw_fifo_resource_inc(dev_priv); 1503 WARN_ON(vmw_request_device_late(dev_priv)); 1504 dev_priv->suspend_locked = false; 1505 if (dev_priv->suspend_state) 1506 vmw_kms_resume(dev); 1507 if (dev_priv->enable_fb) 1508 vmw_fb_on(dev_priv); 1509 return -EBUSY; 1510 } 1511 1512 vmw_fence_fifo_down(dev_priv->fman); 1513 __vmw_svga_disable(dev_priv); 1514 1515 vmw_release_device_late(dev_priv); 1516 return 0; 1517 } 1518 1519 static int vmw_pm_restore(struct device *kdev) 1520 { 1521 struct pci_dev *pdev = to_pci_dev(kdev); 1522 struct drm_device *dev = pci_get_drvdata(pdev); 1523 struct vmw_private *dev_priv = vmw_priv(dev); 1524 int ret; 1525 1526 vmw_detect_version(dev_priv); 1527 1528 if (dev_priv->enable_fb) 1529 vmw_fifo_resource_inc(dev_priv); 1530 1531 ret = vmw_request_device(dev_priv); 1532 if (ret) 1533 return ret; 1534 1535 if (dev_priv->enable_fb) 1536 __vmw_svga_enable(dev_priv); 1537 1538 vmw_fence_fifo_up(dev_priv->fman); 1539 dev_priv->suspend_locked = false; 1540 if (dev_priv->suspend_state) 1541 vmw_kms_resume(&dev_priv->drm); 1542 1543 if (dev_priv->enable_fb) 1544 vmw_fb_on(dev_priv); 1545 1546 return 0; 1547 } 1548 1549 static const struct dev_pm_ops vmw_pm_ops = { 1550 .freeze = vmw_pm_freeze, 1551 .thaw = vmw_pm_restore, 1552 .restore = vmw_pm_restore, 1553 .suspend = vmw_pm_suspend, 1554 .resume = vmw_pm_resume, 1555 }; 1556 1557 static const struct file_operations vmwgfx_driver_fops = { 1558 .owner = THIS_MODULE, 1559 .open = drm_open, 1560 .release = drm_release, 1561 .unlocked_ioctl = vmw_unlocked_ioctl, 1562 .mmap = vmw_mmap, 1563 .poll = drm_poll, 1564 .read = drm_read, 1565 #if defined(CONFIG_COMPAT) 1566 .compat_ioctl = vmw_compat_ioctl, 1567 #endif 1568 .llseek = noop_llseek, 1569 .get_unmapped_area = vmw_get_unmapped_area, 1570 }; 1571 1572 static const struct drm_driver driver = { 1573 .driver_features = 1574 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM, 1575 .ioctls = vmw_ioctls, 1576 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1577 .master_set = vmw_master_set, 1578 .master_drop = vmw_master_drop, 1579 .open = vmw_driver_open, 1580 .postclose = vmw_postclose, 1581 1582 .dumb_create = vmw_dumb_create, 1583 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1584 1585 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1586 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1587 1588 .fops = &vmwgfx_driver_fops, 1589 .name = VMWGFX_DRIVER_NAME, 1590 .desc = VMWGFX_DRIVER_DESC, 1591 .date = VMWGFX_DRIVER_DATE, 1592 .major = VMWGFX_DRIVER_MAJOR, 1593 .minor = VMWGFX_DRIVER_MINOR, 1594 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1595 }; 1596 1597 static struct pci_driver vmw_pci_driver = { 1598 .name = VMWGFX_DRIVER_NAME, 1599 .id_table = vmw_pci_id_list, 1600 .probe = vmw_probe, 1601 .remove = vmw_remove, 1602 .driver = { 1603 .pm = &vmw_pm_ops 1604 } 1605 }; 1606 1607 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1608 { 1609 struct vmw_private *vmw; 1610 int ret; 1611 1612 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver); 1613 if (ret) 1614 goto out_error; 1615 1616 ret = pcim_enable_device(pdev); 1617 if (ret) 1618 goto out_error; 1619 1620 vmw = devm_drm_dev_alloc(&pdev->dev, &driver, 1621 struct vmw_private, drm); 1622 if (IS_ERR(vmw)) { 1623 ret = PTR_ERR(vmw); 1624 goto out_error; 1625 } 1626 1627 pci_set_drvdata(pdev, &vmw->drm); 1628 1629 ret = vmw_driver_load(vmw, ent->device); 1630 if (ret) 1631 goto out_error; 1632 1633 ret = drm_dev_register(&vmw->drm, 0); 1634 if (ret) 1635 goto out_unload; 1636 1637 vmw_debugfs_gem_init(vmw); 1638 1639 return 0; 1640 out_unload: 1641 vmw_driver_unload(&vmw->drm); 1642 out_error: 1643 return ret; 1644 } 1645 1646 static int __init vmwgfx_init(void) 1647 { 1648 int ret; 1649 1650 if (drm_firmware_drivers_only()) 1651 return -EINVAL; 1652 1653 ret = pci_register_driver(&vmw_pci_driver); 1654 if (ret) 1655 DRM_ERROR("Failed initializing DRM.\n"); 1656 return ret; 1657 } 1658 1659 static void __exit vmwgfx_exit(void) 1660 { 1661 pci_unregister_driver(&vmw_pci_driver); 1662 } 1663 1664 module_init(vmwgfx_init); 1665 module_exit(vmwgfx_exit); 1666 1667 MODULE_AUTHOR("VMware Inc. and others"); 1668 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1669 MODULE_LICENSE("GPL and additional rights"); 1670 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1671 __stringify(VMWGFX_DRIVER_MINOR) "." 1672 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1673 "0"); 1674