1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2023 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29 #include "vmwgfx_drv.h" 30 31 #include "vmwgfx_bo.h" 32 #include "vmwgfx_binding.h" 33 #include "vmwgfx_devcaps.h" 34 #include "vmwgfx_mksstat.h" 35 #include "ttm_object.h" 36 37 #include <drm/drm_aperture.h> 38 #include <drm/drm_drv.h> 39 #include <drm/drm_fbdev_generic.h> 40 #include <drm/drm_gem_ttm_helper.h> 41 #include <drm/drm_ioctl.h> 42 #include <drm/drm_module.h> 43 #include <drm/drm_sysfs.h> 44 #include <drm/ttm/ttm_range_manager.h> 45 #include <drm/ttm/ttm_placement.h> 46 #include <generated/utsrelease.h> 47 48 #include <linux/cc_platform.h> 49 #include <linux/dma-mapping.h> 50 #include <linux/module.h> 51 #include <linux/pci.h> 52 #include <linux/version.h> 53 54 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 55 56 /* 57 * Fully encoded drm commands. Might move to vmw_drm.h 58 */ 59 60 #define DRM_IOCTL_VMW_GET_PARAM \ 61 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 62 struct drm_vmw_getparam_arg) 63 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 64 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 65 union drm_vmw_alloc_dmabuf_arg) 66 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 67 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 68 struct drm_vmw_unref_dmabuf_arg) 69 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 70 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 71 struct drm_vmw_cursor_bypass_arg) 72 73 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 74 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 75 struct drm_vmw_control_stream_arg) 76 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 77 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 78 struct drm_vmw_stream_arg) 79 #define DRM_IOCTL_VMW_UNREF_STREAM \ 80 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 81 struct drm_vmw_stream_arg) 82 83 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 84 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 85 struct drm_vmw_context_arg) 86 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 87 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 88 struct drm_vmw_context_arg) 89 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 90 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 91 union drm_vmw_surface_create_arg) 92 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 93 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 94 struct drm_vmw_surface_arg) 95 #define DRM_IOCTL_VMW_REF_SURFACE \ 96 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 97 union drm_vmw_surface_reference_arg) 98 #define DRM_IOCTL_VMW_EXECBUF \ 99 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 100 struct drm_vmw_execbuf_arg) 101 #define DRM_IOCTL_VMW_GET_3D_CAP \ 102 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 103 struct drm_vmw_get_3d_cap_arg) 104 #define DRM_IOCTL_VMW_FENCE_WAIT \ 105 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 106 struct drm_vmw_fence_wait_arg) 107 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 108 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 109 struct drm_vmw_fence_signaled_arg) 110 #define DRM_IOCTL_VMW_FENCE_UNREF \ 111 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 112 struct drm_vmw_fence_arg) 113 #define DRM_IOCTL_VMW_FENCE_EVENT \ 114 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 115 struct drm_vmw_fence_event_arg) 116 #define DRM_IOCTL_VMW_PRESENT \ 117 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 118 struct drm_vmw_present_arg) 119 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 120 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 121 struct drm_vmw_present_readback_arg) 122 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 123 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 124 struct drm_vmw_update_layout_arg) 125 #define DRM_IOCTL_VMW_CREATE_SHADER \ 126 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 127 struct drm_vmw_shader_create_arg) 128 #define DRM_IOCTL_VMW_UNREF_SHADER \ 129 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 130 struct drm_vmw_shader_arg) 131 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 132 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 133 union drm_vmw_gb_surface_create_arg) 134 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 135 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 136 union drm_vmw_gb_surface_reference_arg) 137 #define DRM_IOCTL_VMW_SYNCCPU \ 138 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 139 struct drm_vmw_synccpu_arg) 140 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 141 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 142 struct drm_vmw_context_arg) 143 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 144 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 145 union drm_vmw_gb_surface_create_ext_arg) 146 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 147 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 148 union drm_vmw_gb_surface_reference_ext_arg) 149 #define DRM_IOCTL_VMW_MSG \ 150 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 151 struct drm_vmw_msg_arg) 152 #define DRM_IOCTL_VMW_MKSSTAT_RESET \ 153 DRM_IO(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_RESET) 154 #define DRM_IOCTL_VMW_MKSSTAT_ADD \ 155 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_ADD, \ 156 struct drm_vmw_mksstat_add_arg) 157 #define DRM_IOCTL_VMW_MKSSTAT_REMOVE \ 158 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_MKSSTAT_REMOVE, \ 159 struct drm_vmw_mksstat_remove_arg) 160 161 /* 162 * Ioctl definitions. 163 */ 164 165 static const struct drm_ioctl_desc vmw_ioctls[] = { 166 DRM_IOCTL_DEF_DRV(VMW_GET_PARAM, vmw_getparam_ioctl, 167 DRM_RENDER_ALLOW), 168 DRM_IOCTL_DEF_DRV(VMW_ALLOC_DMABUF, vmw_gem_object_create_ioctl, 169 DRM_RENDER_ALLOW), 170 DRM_IOCTL_DEF_DRV(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 171 DRM_RENDER_ALLOW), 172 DRM_IOCTL_DEF_DRV(VMW_CURSOR_BYPASS, 173 vmw_kms_cursor_bypass_ioctl, 174 DRM_MASTER), 175 176 DRM_IOCTL_DEF_DRV(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 177 DRM_MASTER), 178 DRM_IOCTL_DEF_DRV(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 179 DRM_MASTER), 180 DRM_IOCTL_DEF_DRV(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 181 DRM_MASTER), 182 183 DRM_IOCTL_DEF_DRV(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 184 DRM_RENDER_ALLOW), 185 DRM_IOCTL_DEF_DRV(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 186 DRM_RENDER_ALLOW), 187 DRM_IOCTL_DEF_DRV(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 188 DRM_RENDER_ALLOW), 189 DRM_IOCTL_DEF_DRV(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 190 DRM_RENDER_ALLOW), 191 DRM_IOCTL_DEF_DRV(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 192 DRM_RENDER_ALLOW), 193 DRM_IOCTL_DEF_DRV(VMW_EXECBUF, vmw_execbuf_ioctl, 194 DRM_RENDER_ALLOW), 195 DRM_IOCTL_DEF_DRV(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 196 DRM_RENDER_ALLOW), 197 DRM_IOCTL_DEF_DRV(VMW_FENCE_SIGNALED, 198 vmw_fence_obj_signaled_ioctl, 199 DRM_RENDER_ALLOW), 200 DRM_IOCTL_DEF_DRV(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 201 DRM_RENDER_ALLOW), 202 DRM_IOCTL_DEF_DRV(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 203 DRM_RENDER_ALLOW), 204 DRM_IOCTL_DEF_DRV(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 205 DRM_RENDER_ALLOW), 206 207 /* these allow direct access to the framebuffers mark as master only */ 208 DRM_IOCTL_DEF_DRV(VMW_PRESENT, vmw_present_ioctl, 209 DRM_MASTER | DRM_AUTH), 210 DRM_IOCTL_DEF_DRV(VMW_PRESENT_READBACK, 211 vmw_present_readback_ioctl, 212 DRM_MASTER | DRM_AUTH), 213 /* 214 * The permissions of the below ioctl are overridden in 215 * vmw_generic_ioctl(). We require either 216 * DRM_MASTER or capable(CAP_SYS_ADMIN). 217 */ 218 DRM_IOCTL_DEF_DRV(VMW_UPDATE_LAYOUT, 219 vmw_kms_update_layout_ioctl, 220 DRM_RENDER_ALLOW), 221 DRM_IOCTL_DEF_DRV(VMW_CREATE_SHADER, 222 vmw_shader_define_ioctl, 223 DRM_RENDER_ALLOW), 224 DRM_IOCTL_DEF_DRV(VMW_UNREF_SHADER, 225 vmw_shader_destroy_ioctl, 226 DRM_RENDER_ALLOW), 227 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE, 228 vmw_gb_surface_define_ioctl, 229 DRM_RENDER_ALLOW), 230 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF, 231 vmw_gb_surface_reference_ioctl, 232 DRM_RENDER_ALLOW), 233 DRM_IOCTL_DEF_DRV(VMW_SYNCCPU, 234 vmw_user_bo_synccpu_ioctl, 235 DRM_RENDER_ALLOW), 236 DRM_IOCTL_DEF_DRV(VMW_CREATE_EXTENDED_CONTEXT, 237 vmw_extended_context_define_ioctl, 238 DRM_RENDER_ALLOW), 239 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_CREATE_EXT, 240 vmw_gb_surface_define_ext_ioctl, 241 DRM_RENDER_ALLOW), 242 DRM_IOCTL_DEF_DRV(VMW_GB_SURFACE_REF_EXT, 243 vmw_gb_surface_reference_ext_ioctl, 244 DRM_RENDER_ALLOW), 245 DRM_IOCTL_DEF_DRV(VMW_MSG, 246 vmw_msg_ioctl, 247 DRM_RENDER_ALLOW), 248 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_RESET, 249 vmw_mksstat_reset_ioctl, 250 DRM_RENDER_ALLOW), 251 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_ADD, 252 vmw_mksstat_add_ioctl, 253 DRM_RENDER_ALLOW), 254 DRM_IOCTL_DEF_DRV(VMW_MKSSTAT_REMOVE, 255 vmw_mksstat_remove_ioctl, 256 DRM_RENDER_ALLOW), 257 }; 258 259 static const struct pci_device_id vmw_pci_id_list[] = { 260 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA2) }, 261 { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, VMWGFX_PCI_ID_SVGA3) }, 262 { } 263 }; 264 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 265 266 static int vmw_restrict_iommu; 267 static int vmw_force_coherent; 268 static int vmw_restrict_dma_mask; 269 static int vmw_assume_16bpp; 270 271 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 272 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 273 void *ptr); 274 275 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 276 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 277 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 278 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 279 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 280 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 281 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 282 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 283 284 285 struct bitmap_name { 286 uint32 value; 287 const char *name; 288 }; 289 290 static const struct bitmap_name cap1_names[] = { 291 { SVGA_CAP_RECT_COPY, "rect copy" }, 292 { SVGA_CAP_CURSOR, "cursor" }, 293 { SVGA_CAP_CURSOR_BYPASS, "cursor bypass" }, 294 { SVGA_CAP_CURSOR_BYPASS_2, "cursor bypass 2" }, 295 { SVGA_CAP_8BIT_EMULATION, "8bit emulation" }, 296 { SVGA_CAP_ALPHA_CURSOR, "alpha cursor" }, 297 { SVGA_CAP_3D, "3D" }, 298 { SVGA_CAP_EXTENDED_FIFO, "extended fifo" }, 299 { SVGA_CAP_MULTIMON, "multimon" }, 300 { SVGA_CAP_PITCHLOCK, "pitchlock" }, 301 { SVGA_CAP_IRQMASK, "irq mask" }, 302 { SVGA_CAP_DISPLAY_TOPOLOGY, "display topology" }, 303 { SVGA_CAP_GMR, "gmr" }, 304 { SVGA_CAP_TRACES, "traces" }, 305 { SVGA_CAP_GMR2, "gmr2" }, 306 { SVGA_CAP_SCREEN_OBJECT_2, "screen object 2" }, 307 { SVGA_CAP_COMMAND_BUFFERS, "command buffers" }, 308 { SVGA_CAP_CMD_BUFFERS_2, "command buffers 2" }, 309 { SVGA_CAP_GBOBJECTS, "gbobject" }, 310 { SVGA_CAP_DX, "dx" }, 311 { SVGA_CAP_HP_CMD_QUEUE, "hp cmd queue" }, 312 { SVGA_CAP_NO_BB_RESTRICTION, "no bb restriction" }, 313 { SVGA_CAP_CAP2_REGISTER, "cap2 register" }, 314 }; 315 316 317 static const struct bitmap_name cap2_names[] = { 318 { SVGA_CAP2_GROW_OTABLE, "grow otable" }, 319 { SVGA_CAP2_INTRA_SURFACE_COPY, "intra surface copy" }, 320 { SVGA_CAP2_DX2, "dx2" }, 321 { SVGA_CAP2_GB_MEMSIZE_2, "gb memsize 2" }, 322 { SVGA_CAP2_SCREENDMA_REG, "screendma reg" }, 323 { SVGA_CAP2_OTABLE_PTDEPTH_2, "otable ptdepth2" }, 324 { SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT, "non ms to ms stretchblt" }, 325 { SVGA_CAP2_CURSOR_MOB, "cursor mob" }, 326 { SVGA_CAP2_MSHINT, "mshint" }, 327 { SVGA_CAP2_CB_MAX_SIZE_4MB, "cb max size 4mb" }, 328 { SVGA_CAP2_DX3, "dx3" }, 329 { SVGA_CAP2_FRAME_TYPE, "frame type" }, 330 { SVGA_CAP2_COTABLE_COPY, "cotable copy" }, 331 { SVGA_CAP2_TRACE_FULL_FB, "trace full fb" }, 332 { SVGA_CAP2_EXTRA_REGS, "extra regs" }, 333 { SVGA_CAP2_LO_STAGING, "lo staging" }, 334 }; 335 336 static void vmw_print_bitmap(struct drm_device *drm, 337 const char *prefix, uint32_t bitmap, 338 const struct bitmap_name *bnames, 339 uint32_t num_names) 340 { 341 char buf[512]; 342 uint32_t i; 343 uint32_t offset = 0; 344 for (i = 0; i < num_names; ++i) { 345 if ((bitmap & bnames[i].value) != 0) { 346 offset += snprintf(buf + offset, 347 ARRAY_SIZE(buf) - offset, 348 "%s, ", bnames[i].name); 349 bitmap &= ~bnames[i].value; 350 } 351 } 352 353 drm_info(drm, "%s: %s\n", prefix, buf); 354 if (bitmap != 0) 355 drm_dbg(drm, "%s: unknown enums: %x\n", prefix, bitmap); 356 } 357 358 359 static void vmw_print_sm_type(struct vmw_private *dev_priv) 360 { 361 static const char *names[] = { 362 [VMW_SM_LEGACY] = "Legacy", 363 [VMW_SM_4] = "SM4", 364 [VMW_SM_4_1] = "SM4_1", 365 [VMW_SM_5] = "SM_5", 366 [VMW_SM_5_1X] = "SM_5_1X", 367 [VMW_SM_MAX] = "Invalid" 368 }; 369 BUILD_BUG_ON(ARRAY_SIZE(names) != (VMW_SM_MAX + 1)); 370 drm_info(&dev_priv->drm, "Available shader model: %s.\n", 371 names[dev_priv->sm_type]); 372 } 373 374 /** 375 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 376 * 377 * @dev_priv: A device private structure. 378 * 379 * This function creates a small buffer object that holds the query 380 * result for dummy queries emitted as query barriers. 381 * The function will then map the first page and initialize a pending 382 * occlusion query result structure, Finally it will unmap the buffer. 383 * No interruptible waits are done within this function. 384 * 385 * Returns an error if bo creation or initialization fails. 386 */ 387 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 388 { 389 int ret; 390 struct vmw_bo *vbo; 391 struct ttm_bo_kmap_obj map; 392 volatile SVGA3dQueryResult *result; 393 bool dummy; 394 struct vmw_bo_params bo_params = { 395 .domain = VMW_BO_DOMAIN_SYS, 396 .busy_domain = VMW_BO_DOMAIN_SYS, 397 .bo_type = ttm_bo_type_kernel, 398 .size = PAGE_SIZE, 399 .pin = true 400 }; 401 402 /* 403 * Create the vbo as pinned, so that a tryreserve will 404 * immediately succeed. This is because we're the only 405 * user of the bo currently. 406 */ 407 ret = vmw_bo_create(dev_priv, &bo_params, &vbo); 408 if (unlikely(ret != 0)) 409 return ret; 410 411 ret = ttm_bo_reserve(&vbo->tbo, false, true, NULL); 412 BUG_ON(ret != 0); 413 vmw_bo_pin_reserved(vbo, true); 414 415 ret = ttm_bo_kmap(&vbo->tbo, 0, 1, &map); 416 if (likely(ret == 0)) { 417 result = ttm_kmap_obj_virtual(&map, &dummy); 418 result->totalSize = sizeof(*result); 419 result->state = SVGA3D_QUERYSTATE_PENDING; 420 result->result32 = 0xff; 421 ttm_bo_kunmap(&map); 422 } 423 vmw_bo_pin_reserved(vbo, false); 424 ttm_bo_unreserve(&vbo->tbo); 425 426 if (unlikely(ret != 0)) { 427 DRM_ERROR("Dummy query buffer map failed.\n"); 428 vmw_bo_unreference(&vbo); 429 } else 430 dev_priv->dummy_query_bo = vbo; 431 432 return ret; 433 } 434 435 static int vmw_device_init(struct vmw_private *dev_priv) 436 { 437 bool uses_fb_traces = false; 438 439 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); 440 dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE); 441 dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES); 442 443 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE | 444 SVGA_REG_ENABLE_HIDE); 445 446 uses_fb_traces = !vmw_cmd_supported(dev_priv) && 447 (dev_priv->capabilities & SVGA_CAP_TRACES) != 0; 448 449 vmw_write(dev_priv, SVGA_REG_TRACES, uses_fb_traces); 450 dev_priv->fifo = vmw_fifo_create(dev_priv); 451 if (IS_ERR(dev_priv->fifo)) { 452 int err = PTR_ERR(dev_priv->fifo); 453 dev_priv->fifo = NULL; 454 return err; 455 } else if (!dev_priv->fifo) { 456 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); 457 } 458 459 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); 460 atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno); 461 return 0; 462 } 463 464 static void vmw_device_fini(struct vmw_private *vmw) 465 { 466 /* 467 * Legacy sync 468 */ 469 vmw_write(vmw, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); 470 while (vmw_read(vmw, SVGA_REG_BUSY) != 0) 471 ; 472 473 vmw->last_read_seqno = vmw_fence_read(vmw); 474 475 vmw_write(vmw, SVGA_REG_CONFIG_DONE, 476 vmw->config_done_state); 477 vmw_write(vmw, SVGA_REG_ENABLE, 478 vmw->enable_state); 479 vmw_write(vmw, SVGA_REG_TRACES, 480 vmw->traces_state); 481 482 vmw_fifo_destroy(vmw); 483 } 484 485 /** 486 * vmw_request_device_late - Perform late device setup 487 * 488 * @dev_priv: Pointer to device private. 489 * 490 * This function performs setup of otables and enables large command 491 * buffer submission. These tasks are split out to a separate function 492 * because it reverts vmw_release_device_early and is intended to be used 493 * by an error path in the hibernation code. 494 */ 495 static int vmw_request_device_late(struct vmw_private *dev_priv) 496 { 497 int ret; 498 499 if (dev_priv->has_mob) { 500 ret = vmw_otables_setup(dev_priv); 501 if (unlikely(ret != 0)) { 502 DRM_ERROR("Unable to initialize " 503 "guest Memory OBjects.\n"); 504 return ret; 505 } 506 } 507 508 if (dev_priv->cman) { 509 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 256*4096); 510 if (ret) { 511 struct vmw_cmdbuf_man *man = dev_priv->cman; 512 513 dev_priv->cman = NULL; 514 vmw_cmdbuf_man_destroy(man); 515 } 516 } 517 518 return 0; 519 } 520 521 static int vmw_request_device(struct vmw_private *dev_priv) 522 { 523 int ret; 524 525 ret = vmw_device_init(dev_priv); 526 if (unlikely(ret != 0)) { 527 DRM_ERROR("Unable to initialize the device.\n"); 528 return ret; 529 } 530 vmw_fence_fifo_up(dev_priv->fman); 531 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 532 if (IS_ERR(dev_priv->cman)) { 533 dev_priv->cman = NULL; 534 dev_priv->sm_type = VMW_SM_LEGACY; 535 } 536 537 ret = vmw_request_device_late(dev_priv); 538 if (ret) 539 goto out_no_mob; 540 541 ret = vmw_dummy_query_bo_create(dev_priv); 542 if (unlikely(ret != 0)) 543 goto out_no_query_bo; 544 545 return 0; 546 547 out_no_query_bo: 548 if (dev_priv->cman) 549 vmw_cmdbuf_remove_pool(dev_priv->cman); 550 if (dev_priv->has_mob) { 551 struct ttm_resource_manager *man; 552 553 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 554 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 555 vmw_otables_takedown(dev_priv); 556 } 557 if (dev_priv->cman) 558 vmw_cmdbuf_man_destroy(dev_priv->cman); 559 out_no_mob: 560 vmw_fence_fifo_down(dev_priv->fman); 561 vmw_device_fini(dev_priv); 562 return ret; 563 } 564 565 /** 566 * vmw_release_device_early - Early part of fifo takedown. 567 * 568 * @dev_priv: Pointer to device private struct. 569 * 570 * This is the first part of command submission takedown, to be called before 571 * buffer management is taken down. 572 */ 573 static void vmw_release_device_early(struct vmw_private *dev_priv) 574 { 575 /* 576 * Previous destructions should've released 577 * the pinned bo. 578 */ 579 580 BUG_ON(dev_priv->pinned_bo != NULL); 581 582 vmw_bo_unreference(&dev_priv->dummy_query_bo); 583 if (dev_priv->cman) 584 vmw_cmdbuf_remove_pool(dev_priv->cman); 585 586 if (dev_priv->has_mob) { 587 struct ttm_resource_manager *man; 588 589 man = ttm_manager_type(&dev_priv->bdev, VMW_PL_MOB); 590 ttm_resource_manager_evict_all(&dev_priv->bdev, man); 591 vmw_otables_takedown(dev_priv); 592 } 593 } 594 595 /** 596 * vmw_release_device_late - Late part of fifo takedown. 597 * 598 * @dev_priv: Pointer to device private struct. 599 * 600 * This is the last part of the command submission takedown, to be called when 601 * command submission is no longer needed. It may wait on pending fences. 602 */ 603 static void vmw_release_device_late(struct vmw_private *dev_priv) 604 { 605 vmw_fence_fifo_down(dev_priv->fman); 606 if (dev_priv->cman) 607 vmw_cmdbuf_man_destroy(dev_priv->cman); 608 609 vmw_device_fini(dev_priv); 610 } 611 612 /* 613 * Sets the initial_[width|height] fields on the given vmw_private. 614 * 615 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 616 * clamping the value to fb_max_[width|height] fields and the 617 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 618 * If the values appear to be invalid, set them to 619 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 620 */ 621 static void vmw_get_initial_size(struct vmw_private *dev_priv) 622 { 623 uint32_t width; 624 uint32_t height; 625 626 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 627 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 628 629 width = max_t(uint32_t, width, VMWGFX_MIN_INITIAL_WIDTH); 630 height = max_t(uint32_t, height, VMWGFX_MIN_INITIAL_HEIGHT); 631 632 if (width > dev_priv->fb_max_width || 633 height > dev_priv->fb_max_height) { 634 635 /* 636 * This is a host error and shouldn't occur. 637 */ 638 639 width = VMWGFX_MIN_INITIAL_WIDTH; 640 height = VMWGFX_MIN_INITIAL_HEIGHT; 641 } 642 643 dev_priv->initial_width = width; 644 dev_priv->initial_height = height; 645 } 646 647 /** 648 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 649 * system. 650 * 651 * @dev_priv: Pointer to a struct vmw_private 652 * 653 * This functions tries to determine what actions need to be taken by the 654 * driver to make system pages visible to the device. 655 * If this function decides that DMA is not possible, it returns -EINVAL. 656 * The driver may then try to disable features of the device that require 657 * DMA. 658 */ 659 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 660 { 661 static const char *names[vmw_dma_map_max] = { 662 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 663 [vmw_dma_map_populate] = "Caching DMA mappings.", 664 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 665 666 /* TTM currently doesn't fully support SEV encryption. */ 667 if (cc_platform_has(CC_ATTR_MEM_ENCRYPT)) 668 return -EINVAL; 669 670 if (vmw_force_coherent) 671 dev_priv->map_mode = vmw_dma_alloc_coherent; 672 else if (vmw_restrict_iommu) 673 dev_priv->map_mode = vmw_dma_map_bind; 674 else 675 dev_priv->map_mode = vmw_dma_map_populate; 676 677 drm_info(&dev_priv->drm, 678 "DMA map mode: %s\n", names[dev_priv->map_mode]); 679 return 0; 680 } 681 682 /** 683 * vmw_dma_masks - set required page- and dma masks 684 * 685 * @dev_priv: Pointer to struct drm-device 686 * 687 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 688 * restriction also for 64-bit systems. 689 */ 690 static int vmw_dma_masks(struct vmw_private *dev_priv) 691 { 692 struct drm_device *dev = &dev_priv->drm; 693 int ret = 0; 694 695 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 696 if (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask) { 697 drm_info(&dev_priv->drm, 698 "Restricting DMA addresses to 44 bits.\n"); 699 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 700 } 701 702 return ret; 703 } 704 705 static int vmw_vram_manager_init(struct vmw_private *dev_priv) 706 { 707 int ret; 708 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 709 dev_priv->vram_size >> PAGE_SHIFT); 710 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 711 return ret; 712 } 713 714 static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 715 { 716 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 717 } 718 719 static int vmw_setup_pci_resources(struct vmw_private *dev, 720 u32 pci_id) 721 { 722 resource_size_t rmmio_start; 723 resource_size_t rmmio_size; 724 resource_size_t fifo_start; 725 resource_size_t fifo_size; 726 int ret; 727 struct pci_dev *pdev = to_pci_dev(dev->drm.dev); 728 729 pci_set_master(pdev); 730 731 ret = pci_request_regions(pdev, "vmwgfx probe"); 732 if (ret) 733 return ret; 734 735 dev->pci_id = pci_id; 736 if (pci_id == VMWGFX_PCI_ID_SVGA3) { 737 rmmio_start = pci_resource_start(pdev, 0); 738 rmmio_size = pci_resource_len(pdev, 0); 739 dev->vram_start = pci_resource_start(pdev, 2); 740 dev->vram_size = pci_resource_len(pdev, 2); 741 742 drm_info(&dev->drm, 743 "Register MMIO at 0x%pa size is %llu kiB\n", 744 &rmmio_start, (uint64_t)rmmio_size / 1024); 745 dev->rmmio = devm_ioremap(dev->drm.dev, 746 rmmio_start, 747 rmmio_size); 748 if (!dev->rmmio) { 749 drm_err(&dev->drm, 750 "Failed mapping registers mmio memory.\n"); 751 pci_release_regions(pdev); 752 return -ENOMEM; 753 } 754 } else if (pci_id == VMWGFX_PCI_ID_SVGA2) { 755 dev->io_start = pci_resource_start(pdev, 0); 756 dev->vram_start = pci_resource_start(pdev, 1); 757 dev->vram_size = pci_resource_len(pdev, 1); 758 fifo_start = pci_resource_start(pdev, 2); 759 fifo_size = pci_resource_len(pdev, 2); 760 761 drm_info(&dev->drm, 762 "FIFO at %pa size is %llu kiB\n", 763 &fifo_start, (uint64_t)fifo_size / 1024); 764 dev->fifo_mem = devm_memremap(dev->drm.dev, 765 fifo_start, 766 fifo_size, 767 MEMREMAP_WB); 768 769 if (IS_ERR(dev->fifo_mem)) { 770 drm_err(&dev->drm, 771 "Failed mapping FIFO memory.\n"); 772 pci_release_regions(pdev); 773 return PTR_ERR(dev->fifo_mem); 774 } 775 } else { 776 pci_release_regions(pdev); 777 return -EINVAL; 778 } 779 780 /* 781 * This is approximate size of the vram, the exact size will only 782 * be known after we read SVGA_REG_VRAM_SIZE. The PCI resource 783 * size will be equal to or bigger than the size reported by 784 * SVGA_REG_VRAM_SIZE. 785 */ 786 drm_info(&dev->drm, 787 "VRAM at %pa size is %llu kiB\n", 788 &dev->vram_start, (uint64_t)dev->vram_size / 1024); 789 790 return 0; 791 } 792 793 static int vmw_detect_version(struct vmw_private *dev) 794 { 795 uint32_t svga_id; 796 797 vmw_write(dev, SVGA_REG_ID, vmw_is_svga_v3(dev) ? 798 SVGA_ID_3 : SVGA_ID_2); 799 svga_id = vmw_read(dev, SVGA_REG_ID); 800 if (svga_id != SVGA_ID_2 && svga_id != SVGA_ID_3) { 801 drm_err(&dev->drm, 802 "Unsupported SVGA ID 0x%x on chipset 0x%x\n", 803 svga_id, dev->pci_id); 804 return -ENOSYS; 805 } 806 BUG_ON(vmw_is_svga_v3(dev) && (svga_id != SVGA_ID_3)); 807 drm_info(&dev->drm, 808 "Running on SVGA version %d.\n", (svga_id & 0xff)); 809 return 0; 810 } 811 812 static void vmw_write_driver_id(struct vmw_private *dev) 813 { 814 if ((dev->capabilities2 & SVGA_CAP2_DX2) != 0) { 815 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 816 SVGA_REG_GUEST_DRIVER_ID_LINUX); 817 818 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION1, 819 LINUX_VERSION_MAJOR << 24 | 820 LINUX_VERSION_PATCHLEVEL << 16 | 821 LINUX_VERSION_SUBLEVEL); 822 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION2, 823 VMWGFX_DRIVER_MAJOR << 24 | 824 VMWGFX_DRIVER_MINOR << 16 | 825 VMWGFX_DRIVER_PATCHLEVEL); 826 vmw_write(dev, SVGA_REG_GUEST_DRIVER_VERSION3, 0); 827 828 vmw_write(dev, SVGA_REG_GUEST_DRIVER_ID, 829 SVGA_REG_GUEST_DRIVER_ID_SUBMIT); 830 } 831 } 832 833 static void vmw_sw_context_init(struct vmw_private *dev_priv) 834 { 835 struct vmw_sw_context *sw_context = &dev_priv->ctx; 836 837 hash_init(sw_context->res_ht); 838 } 839 840 static void vmw_sw_context_fini(struct vmw_private *dev_priv) 841 { 842 struct vmw_sw_context *sw_context = &dev_priv->ctx; 843 844 vfree(sw_context->cmd_bounce); 845 if (sw_context->staged_bindings) 846 vmw_binding_state_free(sw_context->staged_bindings); 847 } 848 849 static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id) 850 { 851 int ret; 852 enum vmw_res_type i; 853 bool refuse_dma = false; 854 struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); 855 856 dev_priv->drm.dev_private = dev_priv; 857 858 vmw_sw_context_init(dev_priv); 859 860 mutex_init(&dev_priv->cmdbuf_mutex); 861 mutex_init(&dev_priv->binding_mutex); 862 spin_lock_init(&dev_priv->resource_lock); 863 spin_lock_init(&dev_priv->hw_lock); 864 spin_lock_init(&dev_priv->waiter_lock); 865 spin_lock_init(&dev_priv->cursor_lock); 866 867 ret = vmw_setup_pci_resources(dev_priv, pci_id); 868 if (ret) 869 return ret; 870 ret = vmw_detect_version(dev_priv); 871 if (ret) 872 goto out_no_pci_or_version; 873 874 875 for (i = vmw_res_context; i < vmw_res_max; ++i) { 876 idr_init_base(&dev_priv->res_idr[i], 1); 877 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 878 } 879 880 init_waitqueue_head(&dev_priv->fence_queue); 881 init_waitqueue_head(&dev_priv->fifo_queue); 882 dev_priv->fence_queue_waiters = 0; 883 dev_priv->fifo_queue_waiters = 0; 884 885 dev_priv->used_memory_size = 0; 886 887 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 888 889 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 890 vmw_print_bitmap(&dev_priv->drm, "Capabilities", 891 dev_priv->capabilities, 892 cap1_names, ARRAY_SIZE(cap1_names)); 893 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 894 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 895 vmw_print_bitmap(&dev_priv->drm, "Capabilities2", 896 dev_priv->capabilities2, 897 cap2_names, ARRAY_SIZE(cap2_names)); 898 } 899 900 ret = vmw_dma_select_mode(dev_priv); 901 if (unlikely(ret != 0)) { 902 drm_info(&dev_priv->drm, 903 "Restricting capabilities since DMA not available.\n"); 904 refuse_dma = true; 905 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 906 drm_info(&dev_priv->drm, 907 "Disabling 3D acceleration.\n"); 908 } 909 910 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 911 dev_priv->fifo_mem_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 912 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 913 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 914 915 vmw_get_initial_size(dev_priv); 916 917 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 918 dev_priv->max_gmr_ids = 919 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 920 dev_priv->max_gmr_pages = 921 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 922 dev_priv->memory_size = 923 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 924 dev_priv->memory_size -= dev_priv->vram_size; 925 } else { 926 /* 927 * An arbitrary limit of 512MiB on surface 928 * memory. But all HWV8 hardware supports GMR2. 929 */ 930 dev_priv->memory_size = 512*1024*1024; 931 } 932 dev_priv->max_mob_pages = 0; 933 dev_priv->max_mob_size = 0; 934 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 935 uint64_t mem_size; 936 937 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 938 mem_size = vmw_read(dev_priv, 939 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 940 else 941 mem_size = 942 vmw_read(dev_priv, 943 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 944 945 /* 946 * Workaround for low memory 2D VMs to compensate for the 947 * allocation taken by fbdev 948 */ 949 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 950 mem_size *= 3; 951 952 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 953 dev_priv->max_primary_mem = 954 vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM); 955 dev_priv->max_mob_size = 956 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 957 dev_priv->stdu_max_width = 958 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 959 dev_priv->stdu_max_height = 960 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 961 962 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 963 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 964 dev_priv->texture_max_width = vmw_read(dev_priv, 965 SVGA_REG_DEV_CAP); 966 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 967 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 968 dev_priv->texture_max_height = vmw_read(dev_priv, 969 SVGA_REG_DEV_CAP); 970 } else { 971 dev_priv->texture_max_width = 8192; 972 dev_priv->texture_max_height = 8192; 973 dev_priv->max_primary_mem = dev_priv->vram_size; 974 } 975 drm_info(&dev_priv->drm, 976 "Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n", 977 (u64)dev_priv->vram_size / 1024, 978 (u64)dev_priv->fifo_mem_size / 1024, 979 dev_priv->memory_size / 1024); 980 981 drm_info(&dev_priv->drm, 982 "MOB limits: max mob size = %u kB, max mob pages = %u\n", 983 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); 984 985 ret = vmw_dma_masks(dev_priv); 986 if (unlikely(ret != 0)) 987 goto out_err0; 988 989 dma_set_max_seg_size(dev_priv->drm.dev, U32_MAX); 990 991 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 992 drm_info(&dev_priv->drm, 993 "Max GMR ids is %u\n", 994 (unsigned)dev_priv->max_gmr_ids); 995 drm_info(&dev_priv->drm, 996 "Max number of GMR pages is %u\n", 997 (unsigned)dev_priv->max_gmr_pages); 998 } 999 drm_info(&dev_priv->drm, 1000 "Maximum display memory size is %llu kiB\n", 1001 (uint64_t)dev_priv->max_primary_mem / 1024); 1002 1003 /* Need mmio memory to check for fifo pitchlock cap. */ 1004 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 1005 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 1006 !vmw_fifo_have_pitchlock(dev_priv)) { 1007 ret = -ENOSYS; 1008 DRM_ERROR("Hardware has no pitchlock\n"); 1009 goto out_err0; 1010 } 1011 1012 dev_priv->tdev = ttm_object_device_init(&vmw_prime_dmabuf_ops); 1013 1014 if (unlikely(dev_priv->tdev == NULL)) { 1015 drm_err(&dev_priv->drm, 1016 "Unable to initialize TTM object management.\n"); 1017 ret = -ENOMEM; 1018 goto out_err0; 1019 } 1020 1021 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 1022 ret = vmw_irq_install(dev_priv); 1023 if (ret != 0) { 1024 drm_err(&dev_priv->drm, 1025 "Failed installing irq: %d\n", ret); 1026 goto out_no_irq; 1027 } 1028 } 1029 1030 dev_priv->fman = vmw_fence_manager_init(dev_priv); 1031 if (unlikely(dev_priv->fman == NULL)) { 1032 ret = -ENOMEM; 1033 goto out_no_fman; 1034 } 1035 1036 ret = ttm_device_init(&dev_priv->bdev, &vmw_bo_driver, 1037 dev_priv->drm.dev, 1038 dev_priv->drm.anon_inode->i_mapping, 1039 dev_priv->drm.vma_offset_manager, 1040 dev_priv->map_mode == vmw_dma_alloc_coherent, 1041 false); 1042 if (unlikely(ret != 0)) { 1043 drm_err(&dev_priv->drm, 1044 "Failed initializing TTM buffer object driver.\n"); 1045 goto out_no_bdev; 1046 } 1047 1048 /* 1049 * Enable VRAM, but initially don't use it until SVGA is enabled and 1050 * unhidden. 1051 */ 1052 1053 ret = vmw_vram_manager_init(dev_priv); 1054 if (unlikely(ret != 0)) { 1055 drm_err(&dev_priv->drm, 1056 "Failed initializing memory manager for VRAM.\n"); 1057 goto out_no_vram; 1058 } 1059 1060 ret = vmw_devcaps_create(dev_priv); 1061 if (unlikely(ret != 0)) { 1062 drm_err(&dev_priv->drm, 1063 "Failed initializing device caps.\n"); 1064 goto out_no_vram; 1065 } 1066 1067 /* 1068 * "Guest Memory Regions" is an aperture like feature with 1069 * one slot per bo. There is an upper limit of the number of 1070 * slots as well as the bo size. 1071 */ 1072 dev_priv->has_gmr = true; 1073 /* TODO: This is most likely not correct */ 1074 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 1075 refuse_dma || 1076 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 1077 drm_info(&dev_priv->drm, 1078 "No GMR memory available. " 1079 "Graphics memory resources are very limited.\n"); 1080 dev_priv->has_gmr = false; 1081 } 1082 1083 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 1084 dev_priv->has_mob = true; 1085 1086 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 1087 drm_info(&dev_priv->drm, 1088 "No MOB memory available. " 1089 "3D will be disabled.\n"); 1090 dev_priv->has_mob = false; 1091 } 1092 if (vmw_sys_man_init(dev_priv) != 0) { 1093 drm_info(&dev_priv->drm, 1094 "No MOB page table memory available. " 1095 "3D will be disabled.\n"); 1096 dev_priv->has_mob = false; 1097 } 1098 } 1099 1100 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 1101 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_DXCONTEXT)) 1102 dev_priv->sm_type = VMW_SM_4; 1103 } 1104 1105 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 1106 if (has_sm4_context(dev_priv) && 1107 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 1108 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM41)) 1109 dev_priv->sm_type = VMW_SM_4_1; 1110 if (has_sm4_1_context(dev_priv) && 1111 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 1112 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_SM5)) { 1113 dev_priv->sm_type = VMW_SM_5; 1114 if (vmw_devcap_get(dev_priv, SVGA3D_DEVCAP_GL43)) 1115 dev_priv->sm_type = VMW_SM_5_1X; 1116 } 1117 } 1118 } 1119 1120 ret = vmw_kms_init(dev_priv); 1121 if (unlikely(ret != 0)) 1122 goto out_no_kms; 1123 vmw_overlay_init(dev_priv); 1124 1125 ret = vmw_request_device(dev_priv); 1126 if (ret) 1127 goto out_no_fifo; 1128 1129 vmw_print_sm_type(dev_priv); 1130 vmw_host_printf("vmwgfx: Module Version: %d.%d.%d (kernel: %s)", 1131 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 1132 VMWGFX_DRIVER_PATCHLEVEL, UTS_RELEASE); 1133 vmw_write_driver_id(dev_priv); 1134 1135 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 1136 register_pm_notifier(&dev_priv->pm_nb); 1137 1138 return 0; 1139 1140 out_no_fifo: 1141 vmw_overlay_close(dev_priv); 1142 vmw_kms_close(dev_priv); 1143 out_no_kms: 1144 if (dev_priv->has_mob) { 1145 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1146 vmw_sys_man_fini(dev_priv); 1147 } 1148 if (dev_priv->has_gmr) 1149 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1150 vmw_devcaps_destroy(dev_priv); 1151 vmw_vram_manager_fini(dev_priv); 1152 out_no_vram: 1153 ttm_device_fini(&dev_priv->bdev); 1154 out_no_bdev: 1155 vmw_fence_manager_takedown(dev_priv->fman); 1156 out_no_fman: 1157 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1158 vmw_irq_uninstall(&dev_priv->drm); 1159 out_no_irq: 1160 ttm_object_device_release(&dev_priv->tdev); 1161 out_err0: 1162 for (i = vmw_res_context; i < vmw_res_max; ++i) 1163 idr_destroy(&dev_priv->res_idr[i]); 1164 1165 if (dev_priv->ctx.staged_bindings) 1166 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1167 out_no_pci_or_version: 1168 pci_release_regions(pdev); 1169 return ret; 1170 } 1171 1172 static void vmw_driver_unload(struct drm_device *dev) 1173 { 1174 struct vmw_private *dev_priv = vmw_priv(dev); 1175 struct pci_dev *pdev = to_pci_dev(dev->dev); 1176 enum vmw_res_type i; 1177 1178 unregister_pm_notifier(&dev_priv->pm_nb); 1179 1180 vmw_sw_context_fini(dev_priv); 1181 vmw_fifo_resource_dec(dev_priv); 1182 1183 vmw_svga_disable(dev_priv); 1184 1185 vmw_kms_close(dev_priv); 1186 vmw_overlay_close(dev_priv); 1187 1188 if (dev_priv->has_gmr) 1189 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1190 1191 vmw_release_device_early(dev_priv); 1192 if (dev_priv->has_mob) { 1193 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1194 vmw_sys_man_fini(dev_priv); 1195 } 1196 vmw_devcaps_destroy(dev_priv); 1197 vmw_vram_manager_fini(dev_priv); 1198 ttm_device_fini(&dev_priv->bdev); 1199 vmw_release_device_late(dev_priv); 1200 vmw_fence_manager_takedown(dev_priv->fman); 1201 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1202 vmw_irq_uninstall(&dev_priv->drm); 1203 1204 ttm_object_device_release(&dev_priv->tdev); 1205 1206 for (i = vmw_res_context; i < vmw_res_max; ++i) 1207 idr_destroy(&dev_priv->res_idr[i]); 1208 1209 vmw_mksstat_remove_all(dev_priv); 1210 1211 pci_release_regions(pdev); 1212 } 1213 1214 static void vmw_postclose(struct drm_device *dev, 1215 struct drm_file *file_priv) 1216 { 1217 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1218 1219 ttm_object_file_release(&vmw_fp->tfile); 1220 kfree(vmw_fp); 1221 } 1222 1223 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1224 { 1225 struct vmw_private *dev_priv = vmw_priv(dev); 1226 struct vmw_fpriv *vmw_fp; 1227 int ret = -ENOMEM; 1228 1229 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1230 if (unlikely(!vmw_fp)) 1231 return ret; 1232 1233 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev); 1234 if (unlikely(vmw_fp->tfile == NULL)) 1235 goto out_no_tfile; 1236 1237 file_priv->driver_priv = vmw_fp; 1238 1239 return 0; 1240 1241 out_no_tfile: 1242 kfree(vmw_fp); 1243 return ret; 1244 } 1245 1246 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1247 unsigned long arg, 1248 long (*ioctl_func)(struct file *, unsigned int, 1249 unsigned long)) 1250 { 1251 struct drm_file *file_priv = filp->private_data; 1252 struct drm_device *dev = file_priv->minor->dev; 1253 unsigned int nr = DRM_IOCTL_NR(cmd); 1254 unsigned int flags; 1255 1256 /* 1257 * Do extra checking on driver private ioctls. 1258 */ 1259 1260 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1261 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1262 const struct drm_ioctl_desc *ioctl = 1263 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1264 1265 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1266 return ioctl_func(filp, cmd, arg); 1267 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1268 if (!drm_is_current_master(file_priv) && 1269 !capable(CAP_SYS_ADMIN)) 1270 return -EACCES; 1271 } 1272 1273 if (unlikely(ioctl->cmd != cmd)) 1274 goto out_io_encoding; 1275 1276 flags = ioctl->flags; 1277 } else if (!drm_ioctl_flags(nr, &flags)) 1278 return -EINVAL; 1279 1280 return ioctl_func(filp, cmd, arg); 1281 1282 out_io_encoding: 1283 DRM_ERROR("Invalid command format, ioctl %d\n", 1284 nr - DRM_COMMAND_BASE); 1285 1286 return -EINVAL; 1287 } 1288 1289 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1290 unsigned long arg) 1291 { 1292 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1293 } 1294 1295 #ifdef CONFIG_COMPAT 1296 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1297 unsigned long arg) 1298 { 1299 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1300 } 1301 #endif 1302 1303 static void vmw_master_set(struct drm_device *dev, 1304 struct drm_file *file_priv, 1305 bool from_open) 1306 { 1307 /* 1308 * Inform a new master that the layout may have changed while 1309 * it was gone. 1310 */ 1311 if (!from_open) 1312 drm_sysfs_hotplug_event(dev); 1313 } 1314 1315 static void vmw_master_drop(struct drm_device *dev, 1316 struct drm_file *file_priv) 1317 { 1318 struct vmw_private *dev_priv = vmw_priv(dev); 1319 1320 vmw_kms_legacy_hotspot_clear(dev_priv); 1321 } 1322 1323 /** 1324 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1325 * 1326 * @dev_priv: Pointer to device private struct. 1327 * Needs the reservation sem to be held in non-exclusive mode. 1328 */ 1329 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1330 { 1331 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1332 1333 if (!ttm_resource_manager_used(man)) { 1334 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE_ENABLE); 1335 ttm_resource_manager_set_used(man, true); 1336 } 1337 } 1338 1339 /** 1340 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1341 * 1342 * @dev_priv: Pointer to device private struct. 1343 */ 1344 void vmw_svga_enable(struct vmw_private *dev_priv) 1345 { 1346 __vmw_svga_enable(dev_priv); 1347 } 1348 1349 /** 1350 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1351 * 1352 * @dev_priv: Pointer to device private struct. 1353 * Needs the reservation sem to be held in exclusive mode. 1354 * Will not empty VRAM. VRAM must be emptied by caller. 1355 */ 1356 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1357 { 1358 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1359 1360 if (ttm_resource_manager_used(man)) { 1361 ttm_resource_manager_set_used(man, false); 1362 vmw_write(dev_priv, SVGA_REG_ENABLE, 1363 SVGA_REG_ENABLE_HIDE | 1364 SVGA_REG_ENABLE_ENABLE); 1365 } 1366 } 1367 1368 /** 1369 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1370 * running. 1371 * 1372 * @dev_priv: Pointer to device private struct. 1373 * Will empty VRAM. 1374 */ 1375 void vmw_svga_disable(struct vmw_private *dev_priv) 1376 { 1377 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1378 /* 1379 * Disabling SVGA will turn off device modesetting capabilities, so 1380 * notify KMS about that so that it doesn't cache atomic state that 1381 * isn't valid anymore, for example crtcs turned on. 1382 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1383 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1384 * end up with lock order reversal. Thus, a master may actually perform 1385 * a new modeset just after we call vmw_kms_lost_device() and race with 1386 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1387 * to be inconsistent with the device, causing modesetting problems. 1388 * 1389 */ 1390 vmw_kms_lost_device(&dev_priv->drm); 1391 if (ttm_resource_manager_used(man)) { 1392 if (ttm_resource_manager_evict_all(&dev_priv->bdev, man)) 1393 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1394 ttm_resource_manager_set_used(man, false); 1395 vmw_write(dev_priv, SVGA_REG_ENABLE, 1396 SVGA_REG_ENABLE_HIDE | 1397 SVGA_REG_ENABLE_ENABLE); 1398 } 1399 } 1400 1401 static void vmw_remove(struct pci_dev *pdev) 1402 { 1403 struct drm_device *dev = pci_get_drvdata(pdev); 1404 1405 drm_dev_unregister(dev); 1406 vmw_driver_unload(dev); 1407 } 1408 1409 static void vmw_debugfs_resource_managers_init(struct vmw_private *vmw) 1410 { 1411 struct drm_minor *minor = vmw->drm.primary; 1412 struct dentry *root = minor->debugfs_root; 1413 1414 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_SYSTEM), 1415 root, "system_ttm"); 1416 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, TTM_PL_VRAM), 1417 root, "vram_ttm"); 1418 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_GMR), 1419 root, "gmr_ttm"); 1420 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_MOB), 1421 root, "mob_ttm"); 1422 ttm_resource_manager_create_debugfs(ttm_manager_type(&vmw->bdev, VMW_PL_SYSTEM), 1423 root, "system_mob_ttm"); 1424 } 1425 1426 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1427 void *ptr) 1428 { 1429 struct vmw_private *dev_priv = 1430 container_of(nb, struct vmw_private, pm_nb); 1431 1432 switch (val) { 1433 case PM_HIBERNATION_PREPARE: 1434 /* 1435 * Take the reservation sem in write mode, which will make sure 1436 * there are no other processes holding a buffer object 1437 * reservation, meaning we should be able to evict all buffer 1438 * objects if needed. 1439 * Once user-space processes have been frozen, we can release 1440 * the lock again. 1441 */ 1442 dev_priv->suspend_locked = true; 1443 break; 1444 case PM_POST_HIBERNATION: 1445 case PM_POST_RESTORE: 1446 if (READ_ONCE(dev_priv->suspend_locked)) { 1447 dev_priv->suspend_locked = false; 1448 } 1449 break; 1450 default: 1451 break; 1452 } 1453 return 0; 1454 } 1455 1456 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1457 { 1458 struct drm_device *dev = pci_get_drvdata(pdev); 1459 struct vmw_private *dev_priv = vmw_priv(dev); 1460 1461 if (dev_priv->refuse_hibernation) 1462 return -EBUSY; 1463 1464 pci_save_state(pdev); 1465 pci_disable_device(pdev); 1466 pci_set_power_state(pdev, PCI_D3hot); 1467 return 0; 1468 } 1469 1470 static int vmw_pci_resume(struct pci_dev *pdev) 1471 { 1472 pci_set_power_state(pdev, PCI_D0); 1473 pci_restore_state(pdev); 1474 return pci_enable_device(pdev); 1475 } 1476 1477 static int vmw_pm_suspend(struct device *kdev) 1478 { 1479 struct pci_dev *pdev = to_pci_dev(kdev); 1480 struct pm_message dummy; 1481 1482 dummy.event = 0; 1483 1484 return vmw_pci_suspend(pdev, dummy); 1485 } 1486 1487 static int vmw_pm_resume(struct device *kdev) 1488 { 1489 struct pci_dev *pdev = to_pci_dev(kdev); 1490 1491 return vmw_pci_resume(pdev); 1492 } 1493 1494 static int vmw_pm_freeze(struct device *kdev) 1495 { 1496 struct pci_dev *pdev = to_pci_dev(kdev); 1497 struct drm_device *dev = pci_get_drvdata(pdev); 1498 struct vmw_private *dev_priv = vmw_priv(dev); 1499 struct ttm_operation_ctx ctx = { 1500 .interruptible = false, 1501 .no_wait_gpu = false 1502 }; 1503 int ret; 1504 1505 /* 1506 * No user-space processes should be running now. 1507 */ 1508 ret = vmw_kms_suspend(&dev_priv->drm); 1509 if (ret) { 1510 DRM_ERROR("Failed to freeze modesetting.\n"); 1511 return ret; 1512 } 1513 1514 vmw_execbuf_release_pinned_bo(dev_priv); 1515 vmw_resource_evict_all(dev_priv); 1516 vmw_release_device_early(dev_priv); 1517 while (ttm_device_swapout(&dev_priv->bdev, &ctx, GFP_KERNEL) > 0); 1518 vmw_fifo_resource_dec(dev_priv); 1519 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1520 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1521 vmw_fifo_resource_inc(dev_priv); 1522 WARN_ON(vmw_request_device_late(dev_priv)); 1523 dev_priv->suspend_locked = false; 1524 if (dev_priv->suspend_state) 1525 vmw_kms_resume(dev); 1526 return -EBUSY; 1527 } 1528 1529 vmw_fence_fifo_down(dev_priv->fman); 1530 __vmw_svga_disable(dev_priv); 1531 1532 vmw_release_device_late(dev_priv); 1533 return 0; 1534 } 1535 1536 static int vmw_pm_restore(struct device *kdev) 1537 { 1538 struct pci_dev *pdev = to_pci_dev(kdev); 1539 struct drm_device *dev = pci_get_drvdata(pdev); 1540 struct vmw_private *dev_priv = vmw_priv(dev); 1541 int ret; 1542 1543 vmw_detect_version(dev_priv); 1544 1545 vmw_fifo_resource_inc(dev_priv); 1546 1547 ret = vmw_request_device(dev_priv); 1548 if (ret) 1549 return ret; 1550 1551 __vmw_svga_enable(dev_priv); 1552 1553 vmw_fence_fifo_up(dev_priv->fman); 1554 dev_priv->suspend_locked = false; 1555 if (dev_priv->suspend_state) 1556 vmw_kms_resume(&dev_priv->drm); 1557 1558 return 0; 1559 } 1560 1561 static const struct dev_pm_ops vmw_pm_ops = { 1562 .freeze = vmw_pm_freeze, 1563 .thaw = vmw_pm_restore, 1564 .restore = vmw_pm_restore, 1565 .suspend = vmw_pm_suspend, 1566 .resume = vmw_pm_resume, 1567 }; 1568 1569 static const struct file_operations vmwgfx_driver_fops = { 1570 .owner = THIS_MODULE, 1571 .open = drm_open, 1572 .release = drm_release, 1573 .unlocked_ioctl = vmw_unlocked_ioctl, 1574 .mmap = drm_gem_mmap, 1575 .poll = drm_poll, 1576 .read = drm_read, 1577 #if defined(CONFIG_COMPAT) 1578 .compat_ioctl = vmw_compat_ioctl, 1579 #endif 1580 .llseek = noop_llseek, 1581 }; 1582 1583 static const struct drm_driver driver = { 1584 .driver_features = 1585 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC | DRIVER_GEM, 1586 .ioctls = vmw_ioctls, 1587 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1588 .master_set = vmw_master_set, 1589 .master_drop = vmw_master_drop, 1590 .open = vmw_driver_open, 1591 .postclose = vmw_postclose, 1592 1593 .dumb_create = vmw_dumb_create, 1594 .dumb_map_offset = drm_gem_ttm_dumb_map_offset, 1595 1596 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1597 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1598 1599 .fops = &vmwgfx_driver_fops, 1600 .name = VMWGFX_DRIVER_NAME, 1601 .desc = VMWGFX_DRIVER_DESC, 1602 .date = VMWGFX_DRIVER_DATE, 1603 .major = VMWGFX_DRIVER_MAJOR, 1604 .minor = VMWGFX_DRIVER_MINOR, 1605 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1606 }; 1607 1608 static struct pci_driver vmw_pci_driver = { 1609 .name = VMWGFX_DRIVER_NAME, 1610 .id_table = vmw_pci_id_list, 1611 .probe = vmw_probe, 1612 .remove = vmw_remove, 1613 .driver = { 1614 .pm = &vmw_pm_ops 1615 } 1616 }; 1617 1618 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1619 { 1620 struct vmw_private *vmw; 1621 int ret; 1622 1623 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &driver); 1624 if (ret) 1625 goto out_error; 1626 1627 ret = pcim_enable_device(pdev); 1628 if (ret) 1629 goto out_error; 1630 1631 vmw = devm_drm_dev_alloc(&pdev->dev, &driver, 1632 struct vmw_private, drm); 1633 if (IS_ERR(vmw)) { 1634 ret = PTR_ERR(vmw); 1635 goto out_error; 1636 } 1637 1638 pci_set_drvdata(pdev, &vmw->drm); 1639 1640 ret = vmw_driver_load(vmw, ent->device); 1641 if (ret) 1642 goto out_error; 1643 1644 ret = drm_dev_register(&vmw->drm, 0); 1645 if (ret) 1646 goto out_unload; 1647 1648 vmw_fifo_resource_inc(vmw); 1649 vmw_svga_enable(vmw); 1650 drm_fbdev_generic_setup(&vmw->drm, 0); 1651 1652 vmw_debugfs_gem_init(vmw); 1653 vmw_debugfs_resource_managers_init(vmw); 1654 1655 return 0; 1656 out_unload: 1657 vmw_driver_unload(&vmw->drm); 1658 out_error: 1659 return ret; 1660 } 1661 1662 drm_module_pci_driver(vmw_pci_driver); 1663 1664 MODULE_AUTHOR("VMware Inc. and others"); 1665 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1666 MODULE_LICENSE("GPL and additional rights"); 1667 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1668 __stringify(VMWGFX_DRIVER_MINOR) "." 1669 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1670 "0"); 1671