1 // SPDX-License-Identifier: GPL-2.0 OR MIT 2 /************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 #include <linux/console.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/module.h> 31 #include <linux/pci.h> 32 #include <linux/mem_encrypt.h> 33 34 #include <drm/drm_drv.h> 35 #include <drm/drm_ioctl.h> 36 #include <drm/drm_sysfs.h> 37 #include <drm/ttm/ttm_bo_driver.h> 38 #include <drm/ttm/ttm_module.h> 39 #include <drm/ttm/ttm_placement.h> 40 41 #include "ttm_object.h" 42 #include "vmwgfx_binding.h" 43 #include "vmwgfx_drv.h" 44 45 #define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 46 #define VMWGFX_CHIP_SVGAII 0 47 #define VMW_FB_RESERVATION 0 48 49 #define VMW_MIN_INITIAL_WIDTH 800 50 #define VMW_MIN_INITIAL_HEIGHT 600 51 52 #ifndef VMWGFX_GIT_VERSION 53 #define VMWGFX_GIT_VERSION "Unknown" 54 #endif 55 56 #define VMWGFX_REPO "In Tree" 57 58 #define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 59 60 61 /** 62 * Fully encoded drm commands. Might move to vmw_drm.h 63 */ 64 65 #define DRM_IOCTL_VMW_GET_PARAM \ 66 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 67 struct drm_vmw_getparam_arg) 68 #define DRM_IOCTL_VMW_ALLOC_DMABUF \ 69 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 70 union drm_vmw_alloc_dmabuf_arg) 71 #define DRM_IOCTL_VMW_UNREF_DMABUF \ 72 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 73 struct drm_vmw_unref_dmabuf_arg) 74 #define DRM_IOCTL_VMW_CURSOR_BYPASS \ 75 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 76 struct drm_vmw_cursor_bypass_arg) 77 78 #define DRM_IOCTL_VMW_CONTROL_STREAM \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 80 struct drm_vmw_control_stream_arg) 81 #define DRM_IOCTL_VMW_CLAIM_STREAM \ 82 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 83 struct drm_vmw_stream_arg) 84 #define DRM_IOCTL_VMW_UNREF_STREAM \ 85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 86 struct drm_vmw_stream_arg) 87 88 #define DRM_IOCTL_VMW_CREATE_CONTEXT \ 89 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 90 struct drm_vmw_context_arg) 91 #define DRM_IOCTL_VMW_UNREF_CONTEXT \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 93 struct drm_vmw_context_arg) 94 #define DRM_IOCTL_VMW_CREATE_SURFACE \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 96 union drm_vmw_surface_create_arg) 97 #define DRM_IOCTL_VMW_UNREF_SURFACE \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 99 struct drm_vmw_surface_arg) 100 #define DRM_IOCTL_VMW_REF_SURFACE \ 101 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 102 union drm_vmw_surface_reference_arg) 103 #define DRM_IOCTL_VMW_EXECBUF \ 104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 105 struct drm_vmw_execbuf_arg) 106 #define DRM_IOCTL_VMW_GET_3D_CAP \ 107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 108 struct drm_vmw_get_3d_cap_arg) 109 #define DRM_IOCTL_VMW_FENCE_WAIT \ 110 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 111 struct drm_vmw_fence_wait_arg) 112 #define DRM_IOCTL_VMW_FENCE_SIGNALED \ 113 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 114 struct drm_vmw_fence_signaled_arg) 115 #define DRM_IOCTL_VMW_FENCE_UNREF \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 117 struct drm_vmw_fence_arg) 118 #define DRM_IOCTL_VMW_FENCE_EVENT \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 120 struct drm_vmw_fence_event_arg) 121 #define DRM_IOCTL_VMW_PRESENT \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 123 struct drm_vmw_present_arg) 124 #define DRM_IOCTL_VMW_PRESENT_READBACK \ 125 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 126 struct drm_vmw_present_readback_arg) 127 #define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 129 struct drm_vmw_update_layout_arg) 130 #define DRM_IOCTL_VMW_CREATE_SHADER \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 132 struct drm_vmw_shader_create_arg) 133 #define DRM_IOCTL_VMW_UNREF_SHADER \ 134 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 135 struct drm_vmw_shader_arg) 136 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 137 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 138 union drm_vmw_gb_surface_create_arg) 139 #define DRM_IOCTL_VMW_GB_SURFACE_REF \ 140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 141 union drm_vmw_gb_surface_reference_arg) 142 #define DRM_IOCTL_VMW_SYNCCPU \ 143 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 144 struct drm_vmw_synccpu_arg) 145 #define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 147 struct drm_vmw_context_arg) 148 #define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 149 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 150 union drm_vmw_gb_surface_create_ext_arg) 151 #define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 152 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 153 union drm_vmw_gb_surface_reference_ext_arg) 154 #define DRM_IOCTL_VMW_MSG \ 155 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 156 struct drm_vmw_msg_arg) 157 158 /** 159 * The core DRM version of this macro doesn't account for 160 * DRM_COMMAND_BASE. 161 */ 162 163 #define VMW_IOCTL_DEF(ioctl, func, flags) \ 164 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 165 166 /** 167 * Ioctl definitions. 168 */ 169 170 static const struct drm_ioctl_desc vmw_ioctls[] = { 171 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 172 DRM_RENDER_ALLOW), 173 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 174 DRM_RENDER_ALLOW), 175 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 176 DRM_RENDER_ALLOW), 177 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 178 vmw_kms_cursor_bypass_ioctl, 179 DRM_MASTER), 180 181 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 182 DRM_MASTER), 183 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 184 DRM_MASTER), 185 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 186 DRM_MASTER), 187 188 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 189 DRM_RENDER_ALLOW), 190 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 191 DRM_RENDER_ALLOW), 192 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 193 DRM_RENDER_ALLOW), 194 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 197 DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, 199 DRM_RENDER_ALLOW), 200 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 201 DRM_RENDER_ALLOW), 202 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 203 vmw_fence_obj_signaled_ioctl, 204 DRM_RENDER_ALLOW), 205 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 206 DRM_RENDER_ALLOW), 207 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 208 DRM_RENDER_ALLOW), 209 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 210 DRM_RENDER_ALLOW), 211 212 /* these allow direct access to the framebuffers mark as master only */ 213 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 214 DRM_MASTER | DRM_AUTH), 215 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 216 vmw_present_readback_ioctl, 217 DRM_MASTER | DRM_AUTH), 218 /* 219 * The permissions of the below ioctl are overridden in 220 * vmw_generic_ioctl(). We require either 221 * DRM_MASTER or capable(CAP_SYS_ADMIN). 222 */ 223 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 224 vmw_kms_update_layout_ioctl, 225 DRM_RENDER_ALLOW), 226 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 227 vmw_shader_define_ioctl, 228 DRM_RENDER_ALLOW), 229 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 230 vmw_shader_destroy_ioctl, 231 DRM_RENDER_ALLOW), 232 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 233 vmw_gb_surface_define_ioctl, 234 DRM_RENDER_ALLOW), 235 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 236 vmw_gb_surface_reference_ioctl, 237 DRM_RENDER_ALLOW), 238 VMW_IOCTL_DEF(VMW_SYNCCPU, 239 vmw_user_bo_synccpu_ioctl, 240 DRM_RENDER_ALLOW), 241 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 242 vmw_extended_context_define_ioctl, 243 DRM_RENDER_ALLOW), 244 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 245 vmw_gb_surface_define_ext_ioctl, 246 DRM_RENDER_ALLOW), 247 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 248 vmw_gb_surface_reference_ext_ioctl, 249 DRM_RENDER_ALLOW), 250 VMW_IOCTL_DEF(VMW_MSG, 251 vmw_msg_ioctl, 252 DRM_RENDER_ALLOW), 253 }; 254 255 static const struct pci_device_id vmw_pci_id_list[] = { 256 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 257 {0, 0, 0} 258 }; 259 MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 260 261 static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 262 static int vmw_force_iommu; 263 static int vmw_restrict_iommu; 264 static int vmw_force_coherent; 265 static int vmw_restrict_dma_mask; 266 static int vmw_assume_16bpp; 267 268 static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 269 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 270 void *ptr); 271 272 MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 273 module_param_named(enable_fbdev, enable_fbdev, int, 0600); 274 MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 275 module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 276 MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 277 module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 278 MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 279 module_param_named(force_coherent, vmw_force_coherent, int, 0600); 280 MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 281 module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 282 MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 283 module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 284 285 286 static void vmw_print_capabilities2(uint32_t capabilities2) 287 { 288 DRM_INFO("Capabilities2:\n"); 289 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 290 DRM_INFO(" Grow oTable.\n"); 291 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 292 DRM_INFO(" IntraSurface copy.\n"); 293 if (capabilities2 & SVGA_CAP2_DX3) 294 DRM_INFO(" DX3.\n"); 295 } 296 297 static void vmw_print_capabilities(uint32_t capabilities) 298 { 299 DRM_INFO("Capabilities:\n"); 300 if (capabilities & SVGA_CAP_RECT_COPY) 301 DRM_INFO(" Rect copy.\n"); 302 if (capabilities & SVGA_CAP_CURSOR) 303 DRM_INFO(" Cursor.\n"); 304 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 305 DRM_INFO(" Cursor bypass.\n"); 306 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 307 DRM_INFO(" Cursor bypass 2.\n"); 308 if (capabilities & SVGA_CAP_8BIT_EMULATION) 309 DRM_INFO(" 8bit emulation.\n"); 310 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 311 DRM_INFO(" Alpha cursor.\n"); 312 if (capabilities & SVGA_CAP_3D) 313 DRM_INFO(" 3D.\n"); 314 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 315 DRM_INFO(" Extended Fifo.\n"); 316 if (capabilities & SVGA_CAP_MULTIMON) 317 DRM_INFO(" Multimon.\n"); 318 if (capabilities & SVGA_CAP_PITCHLOCK) 319 DRM_INFO(" Pitchlock.\n"); 320 if (capabilities & SVGA_CAP_IRQMASK) 321 DRM_INFO(" Irq mask.\n"); 322 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 323 DRM_INFO(" Display Topology.\n"); 324 if (capabilities & SVGA_CAP_GMR) 325 DRM_INFO(" GMR.\n"); 326 if (capabilities & SVGA_CAP_TRACES) 327 DRM_INFO(" Traces.\n"); 328 if (capabilities & SVGA_CAP_GMR2) 329 DRM_INFO(" GMR2.\n"); 330 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 331 DRM_INFO(" Screen Object 2.\n"); 332 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 333 DRM_INFO(" Command Buffers.\n"); 334 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 335 DRM_INFO(" Command Buffers 2.\n"); 336 if (capabilities & SVGA_CAP_GBOBJECTS) 337 DRM_INFO(" Guest Backed Resources.\n"); 338 if (capabilities & SVGA_CAP_DX) 339 DRM_INFO(" DX Features.\n"); 340 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 341 DRM_INFO(" HP Command Queue.\n"); 342 } 343 344 /** 345 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 346 * 347 * @dev_priv: A device private structure. 348 * 349 * This function creates a small buffer object that holds the query 350 * result for dummy queries emitted as query barriers. 351 * The function will then map the first page and initialize a pending 352 * occlusion query result structure, Finally it will unmap the buffer. 353 * No interruptible waits are done within this function. 354 * 355 * Returns an error if bo creation or initialization fails. 356 */ 357 static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 358 { 359 int ret; 360 struct vmw_buffer_object *vbo; 361 struct ttm_bo_kmap_obj map; 362 volatile SVGA3dQueryResult *result; 363 bool dummy; 364 365 /* 366 * Create the vbo as pinned, so that a tryreserve will 367 * immediately succeed. This is because we're the only 368 * user of the bo currently. 369 */ 370 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 371 if (!vbo) 372 return -ENOMEM; 373 374 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 375 &vmw_sys_ne_placement, false, 376 &vmw_bo_bo_free); 377 if (unlikely(ret != 0)) 378 return ret; 379 380 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 381 BUG_ON(ret != 0); 382 vmw_bo_pin_reserved(vbo, true); 383 384 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 385 if (likely(ret == 0)) { 386 result = ttm_kmap_obj_virtual(&map, &dummy); 387 result->totalSize = sizeof(*result); 388 result->state = SVGA3D_QUERYSTATE_PENDING; 389 result->result32 = 0xff; 390 ttm_bo_kunmap(&map); 391 } 392 vmw_bo_pin_reserved(vbo, false); 393 ttm_bo_unreserve(&vbo->base); 394 395 if (unlikely(ret != 0)) { 396 DRM_ERROR("Dummy query buffer map failed.\n"); 397 vmw_bo_unreference(&vbo); 398 } else 399 dev_priv->dummy_query_bo = vbo; 400 401 return ret; 402 } 403 404 /** 405 * vmw_request_device_late - Perform late device setup 406 * 407 * @dev_priv: Pointer to device private. 408 * 409 * This function performs setup of otables and enables large command 410 * buffer submission. These tasks are split out to a separate function 411 * because it reverts vmw_release_device_early and is intended to be used 412 * by an error path in the hibernation code. 413 */ 414 static int vmw_request_device_late(struct vmw_private *dev_priv) 415 { 416 int ret; 417 418 if (dev_priv->has_mob) { 419 ret = vmw_otables_setup(dev_priv); 420 if (unlikely(ret != 0)) { 421 DRM_ERROR("Unable to initialize " 422 "guest Memory OBjects.\n"); 423 return ret; 424 } 425 } 426 427 if (dev_priv->cman) { 428 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 429 256*4096, 2*4096); 430 if (ret) { 431 struct vmw_cmdbuf_man *man = dev_priv->cman; 432 433 dev_priv->cman = NULL; 434 vmw_cmdbuf_man_destroy(man); 435 } 436 } 437 438 return 0; 439 } 440 441 static int vmw_request_device(struct vmw_private *dev_priv) 442 { 443 int ret; 444 445 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 446 if (unlikely(ret != 0)) { 447 DRM_ERROR("Unable to initialize FIFO.\n"); 448 return ret; 449 } 450 vmw_fence_fifo_up(dev_priv->fman); 451 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 452 if (IS_ERR(dev_priv->cman)) { 453 dev_priv->cman = NULL; 454 dev_priv->sm_type = VMW_SM_LEGACY; 455 } 456 457 ret = vmw_request_device_late(dev_priv); 458 if (ret) 459 goto out_no_mob; 460 461 ret = vmw_dummy_query_bo_create(dev_priv); 462 if (unlikely(ret != 0)) 463 goto out_no_query_bo; 464 465 return 0; 466 467 out_no_query_bo: 468 if (dev_priv->cman) 469 vmw_cmdbuf_remove_pool(dev_priv->cman); 470 if (dev_priv->has_mob) { 471 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 472 vmw_otables_takedown(dev_priv); 473 } 474 if (dev_priv->cman) 475 vmw_cmdbuf_man_destroy(dev_priv->cman); 476 out_no_mob: 477 vmw_fence_fifo_down(dev_priv->fman); 478 vmw_fifo_release(dev_priv, &dev_priv->fifo); 479 return ret; 480 } 481 482 /** 483 * vmw_release_device_early - Early part of fifo takedown. 484 * 485 * @dev_priv: Pointer to device private struct. 486 * 487 * This is the first part of command submission takedown, to be called before 488 * buffer management is taken down. 489 */ 490 static void vmw_release_device_early(struct vmw_private *dev_priv) 491 { 492 /* 493 * Previous destructions should've released 494 * the pinned bo. 495 */ 496 497 BUG_ON(dev_priv->pinned_bo != NULL); 498 499 vmw_bo_unreference(&dev_priv->dummy_query_bo); 500 if (dev_priv->cman) 501 vmw_cmdbuf_remove_pool(dev_priv->cman); 502 503 if (dev_priv->has_mob) { 504 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 505 vmw_otables_takedown(dev_priv); 506 } 507 } 508 509 /** 510 * vmw_release_device_late - Late part of fifo takedown. 511 * 512 * @dev_priv: Pointer to device private struct. 513 * 514 * This is the last part of the command submission takedown, to be called when 515 * command submission is no longer needed. It may wait on pending fences. 516 */ 517 static void vmw_release_device_late(struct vmw_private *dev_priv) 518 { 519 vmw_fence_fifo_down(dev_priv->fman); 520 if (dev_priv->cman) 521 vmw_cmdbuf_man_destroy(dev_priv->cman); 522 523 vmw_fifo_release(dev_priv, &dev_priv->fifo); 524 } 525 526 /** 527 * Sets the initial_[width|height] fields on the given vmw_private. 528 * 529 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 530 * clamping the value to fb_max_[width|height] fields and the 531 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 532 * If the values appear to be invalid, set them to 533 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 534 */ 535 static void vmw_get_initial_size(struct vmw_private *dev_priv) 536 { 537 uint32_t width; 538 uint32_t height; 539 540 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 541 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 542 543 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 544 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 545 546 if (width > dev_priv->fb_max_width || 547 height > dev_priv->fb_max_height) { 548 549 /* 550 * This is a host error and shouldn't occur. 551 */ 552 553 width = VMW_MIN_INITIAL_WIDTH; 554 height = VMW_MIN_INITIAL_HEIGHT; 555 } 556 557 dev_priv->initial_width = width; 558 dev_priv->initial_height = height; 559 } 560 561 /** 562 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 563 * system. 564 * 565 * @dev_priv: Pointer to a struct vmw_private 566 * 567 * This functions tries to determine what actions need to be taken by the 568 * driver to make system pages visible to the device. 569 * If this function decides that DMA is not possible, it returns -EINVAL. 570 * The driver may then try to disable features of the device that require 571 * DMA. 572 */ 573 static int vmw_dma_select_mode(struct vmw_private *dev_priv) 574 { 575 static const char *names[vmw_dma_map_max] = { 576 [vmw_dma_phys] = "Using physical TTM page addresses.", 577 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 578 [vmw_dma_map_populate] = "Caching DMA mappings.", 579 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 580 581 /* TTM currently doesn't fully support SEV encryption. */ 582 if (mem_encrypt_active()) 583 return -EINVAL; 584 585 if (vmw_force_coherent) 586 dev_priv->map_mode = vmw_dma_alloc_coherent; 587 else if (vmw_restrict_iommu) 588 dev_priv->map_mode = vmw_dma_map_bind; 589 else 590 dev_priv->map_mode = vmw_dma_map_populate; 591 592 if (!IS_ENABLED(CONFIG_DRM_TTM_DMA_PAGE_POOL) && 593 (dev_priv->map_mode == vmw_dma_alloc_coherent)) 594 return -EINVAL; 595 596 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 597 return 0; 598 } 599 600 /** 601 * vmw_dma_masks - set required page- and dma masks 602 * 603 * @dev: Pointer to struct drm-device 604 * 605 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 606 * restriction also for 64-bit systems. 607 */ 608 static int vmw_dma_masks(struct vmw_private *dev_priv) 609 { 610 struct drm_device *dev = dev_priv->dev; 611 int ret = 0; 612 613 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 614 if (dev_priv->map_mode != vmw_dma_phys && 615 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 616 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 617 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 618 } 619 620 return ret; 621 } 622 623 static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 624 { 625 struct vmw_private *dev_priv; 626 int ret; 627 uint32_t svga_id; 628 enum vmw_res_type i; 629 bool refuse_dma = false; 630 char host_log[100] = {0}; 631 632 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 633 if (unlikely(!dev_priv)) { 634 DRM_ERROR("Failed allocating a device private struct.\n"); 635 return -ENOMEM; 636 } 637 638 pci_set_master(dev->pdev); 639 640 dev_priv->dev = dev; 641 dev_priv->vmw_chipset = chipset; 642 dev_priv->last_read_seqno = (uint32_t) -100; 643 mutex_init(&dev_priv->cmdbuf_mutex); 644 mutex_init(&dev_priv->release_mutex); 645 mutex_init(&dev_priv->binding_mutex); 646 mutex_init(&dev_priv->global_kms_state_mutex); 647 ttm_lock_init(&dev_priv->reservation_sem); 648 spin_lock_init(&dev_priv->resource_lock); 649 spin_lock_init(&dev_priv->hw_lock); 650 spin_lock_init(&dev_priv->waiter_lock); 651 spin_lock_init(&dev_priv->cap_lock); 652 spin_lock_init(&dev_priv->svga_lock); 653 spin_lock_init(&dev_priv->cursor_lock); 654 655 for (i = vmw_res_context; i < vmw_res_max; ++i) { 656 idr_init(&dev_priv->res_idr[i]); 657 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 658 } 659 660 init_waitqueue_head(&dev_priv->fence_queue); 661 init_waitqueue_head(&dev_priv->fifo_queue); 662 dev_priv->fence_queue_waiters = 0; 663 dev_priv->fifo_queue_waiters = 0; 664 665 dev_priv->used_memory_size = 0; 666 667 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 668 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 669 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 670 671 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 672 673 dev_priv->enable_fb = enable_fbdev; 674 675 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 676 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 677 if (svga_id != SVGA_ID_2) { 678 ret = -ENOSYS; 679 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 680 goto out_err0; 681 } 682 683 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 684 685 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 686 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 687 } 688 689 690 ret = vmw_dma_select_mode(dev_priv); 691 if (unlikely(ret != 0)) { 692 DRM_INFO("Restricting capabilities since DMA not available.\n"); 693 refuse_dma = true; 694 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 695 DRM_INFO("Disabling 3D acceleration.\n"); 696 } 697 698 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 699 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 700 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 701 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 702 703 vmw_get_initial_size(dev_priv); 704 705 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 706 dev_priv->max_gmr_ids = 707 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 708 dev_priv->max_gmr_pages = 709 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 710 dev_priv->memory_size = 711 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 712 dev_priv->memory_size -= dev_priv->vram_size; 713 } else { 714 /* 715 * An arbitrary limit of 512MiB on surface 716 * memory. But all HWV8 hardware supports GMR2. 717 */ 718 dev_priv->memory_size = 512*1024*1024; 719 } 720 dev_priv->max_mob_pages = 0; 721 dev_priv->max_mob_size = 0; 722 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 723 uint64_t mem_size; 724 725 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 726 mem_size = vmw_read(dev_priv, 727 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 728 else 729 mem_size = 730 vmw_read(dev_priv, 731 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 732 733 /* 734 * Workaround for low memory 2D VMs to compensate for the 735 * allocation taken by fbdev 736 */ 737 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 738 mem_size *= 3; 739 740 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 741 dev_priv->prim_bb_mem = 742 vmw_read(dev_priv, 743 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 744 dev_priv->max_mob_size = 745 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 746 dev_priv->stdu_max_width = 747 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 748 dev_priv->stdu_max_height = 749 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 750 751 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 752 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 753 dev_priv->texture_max_width = vmw_read(dev_priv, 754 SVGA_REG_DEV_CAP); 755 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 756 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 757 dev_priv->texture_max_height = vmw_read(dev_priv, 758 SVGA_REG_DEV_CAP); 759 } else { 760 dev_priv->texture_max_width = 8192; 761 dev_priv->texture_max_height = 8192; 762 dev_priv->prim_bb_mem = dev_priv->vram_size; 763 } 764 765 vmw_print_capabilities(dev_priv->capabilities); 766 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 767 vmw_print_capabilities2(dev_priv->capabilities2); 768 769 ret = vmw_dma_masks(dev_priv); 770 if (unlikely(ret != 0)) 771 goto out_err0; 772 773 dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK, 774 SCATTERLIST_MAX_SEGMENT)); 775 776 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 777 DRM_INFO("Max GMR ids is %u\n", 778 (unsigned)dev_priv->max_gmr_ids); 779 DRM_INFO("Max number of GMR pages is %u\n", 780 (unsigned)dev_priv->max_gmr_pages); 781 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 782 (unsigned)dev_priv->memory_size / 1024); 783 } 784 DRM_INFO("Maximum display memory size is %u kiB\n", 785 dev_priv->prim_bb_mem / 1024); 786 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 787 dev_priv->vram_start, dev_priv->vram_size / 1024); 788 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 789 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 790 791 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 792 dev_priv->mmio_size, MEMREMAP_WB); 793 794 if (unlikely(dev_priv->mmio_virt == NULL)) { 795 ret = -ENOMEM; 796 DRM_ERROR("Failed mapping MMIO.\n"); 797 goto out_err0; 798 } 799 800 /* Need mmio memory to check for fifo pitchlock cap. */ 801 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 802 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 803 !vmw_fifo_have_pitchlock(dev_priv)) { 804 ret = -ENOSYS; 805 DRM_ERROR("Hardware has no pitchlock\n"); 806 goto out_err4; 807 } 808 809 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 810 &vmw_prime_dmabuf_ops); 811 812 if (unlikely(dev_priv->tdev == NULL)) { 813 DRM_ERROR("Unable to initialize TTM object management.\n"); 814 ret = -ENOMEM; 815 goto out_err4; 816 } 817 818 dev->dev_private = dev_priv; 819 820 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 821 dev_priv->stealth = (ret != 0); 822 if (dev_priv->stealth) { 823 /** 824 * Request at least the mmio PCI resource. 825 */ 826 827 DRM_INFO("It appears like vesafb is loaded. " 828 "Ignore above error if any.\n"); 829 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 830 if (unlikely(ret != 0)) { 831 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 832 goto out_no_device; 833 } 834 } 835 836 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 837 ret = vmw_irq_install(dev, dev->pdev->irq); 838 if (ret != 0) { 839 DRM_ERROR("Failed installing irq: %d\n", ret); 840 goto out_no_irq; 841 } 842 } 843 844 dev_priv->fman = vmw_fence_manager_init(dev_priv); 845 if (unlikely(dev_priv->fman == NULL)) { 846 ret = -ENOMEM; 847 goto out_no_fman; 848 } 849 850 drm_vma_offset_manager_init(&dev_priv->vma_manager, 851 DRM_FILE_PAGE_OFFSET_START, 852 DRM_FILE_PAGE_OFFSET_SIZE); 853 ret = ttm_bo_device_init(&dev_priv->bdev, 854 &vmw_bo_driver, 855 dev->anon_inode->i_mapping, 856 &dev_priv->vma_manager, 857 false); 858 if (unlikely(ret != 0)) { 859 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 860 goto out_no_bdev; 861 } 862 863 /* 864 * Enable VRAM, but initially don't use it until SVGA is enabled and 865 * unhidden. 866 */ 867 ret = ttm_bo_init_mm(&dev_priv->bdev, TTM_PL_VRAM, 868 (dev_priv->vram_size >> PAGE_SHIFT)); 869 if (unlikely(ret != 0)) { 870 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 871 goto out_no_vram; 872 } 873 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 874 875 dev_priv->has_gmr = true; 876 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 877 refuse_dma || ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_GMR, 878 VMW_PL_GMR) != 0) { 879 DRM_INFO("No GMR memory available. " 880 "Graphics memory resources are very limited.\n"); 881 dev_priv->has_gmr = false; 882 } 883 884 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 885 dev_priv->has_mob = true; 886 if (ttm_bo_init_mm(&dev_priv->bdev, VMW_PL_MOB, 887 VMW_PL_MOB) != 0) { 888 DRM_INFO("No MOB memory available. " 889 "3D will be disabled.\n"); 890 dev_priv->has_mob = false; 891 } 892 } 893 894 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 895 spin_lock(&dev_priv->cap_lock); 896 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 897 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 898 dev_priv->sm_type = VMW_SM_4; 899 spin_unlock(&dev_priv->cap_lock); 900 } 901 902 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 903 904 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 905 if (has_sm4_context(dev_priv) && 906 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 907 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM41); 908 909 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 910 dev_priv->sm_type = VMW_SM_4_1; 911 912 if (has_sm4_1_context(dev_priv) && 913 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 914 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM5); 915 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 916 dev_priv->sm_type = VMW_SM_5; 917 } 918 } 919 920 ret = vmw_kms_init(dev_priv); 921 if (unlikely(ret != 0)) 922 goto out_no_kms; 923 vmw_overlay_init(dev_priv); 924 925 ret = vmw_request_device(dev_priv); 926 if (ret) 927 goto out_no_fifo; 928 929 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 930 ? "yes." : "no."); 931 if (dev_priv->sm_type == VMW_SM_5) 932 DRM_INFO("SM5 support available.\n"); 933 if (dev_priv->sm_type == VMW_SM_4_1) 934 DRM_INFO("SM4_1 support available.\n"); 935 if (dev_priv->sm_type == VMW_SM_4) 936 DRM_INFO("SM4 support available.\n"); 937 938 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 939 VMWGFX_REPO, VMWGFX_GIT_VERSION); 940 vmw_host_log(host_log); 941 942 memset(host_log, 0, sizeof(host_log)); 943 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 944 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 945 VMWGFX_DRIVER_PATCHLEVEL); 946 vmw_host_log(host_log); 947 948 if (dev_priv->enable_fb) { 949 vmw_fifo_resource_inc(dev_priv); 950 vmw_svga_enable(dev_priv); 951 vmw_fb_init(dev_priv); 952 } 953 954 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 955 register_pm_notifier(&dev_priv->pm_nb); 956 957 return 0; 958 959 out_no_fifo: 960 vmw_overlay_close(dev_priv); 961 vmw_kms_close(dev_priv); 962 out_no_kms: 963 if (dev_priv->has_mob) 964 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 965 if (dev_priv->has_gmr) 966 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 967 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 968 out_no_vram: 969 (void)ttm_bo_device_release(&dev_priv->bdev); 970 out_no_bdev: 971 vmw_fence_manager_takedown(dev_priv->fman); 972 out_no_fman: 973 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 974 vmw_irq_uninstall(dev_priv->dev); 975 out_no_irq: 976 if (dev_priv->stealth) 977 pci_release_region(dev->pdev, 2); 978 else 979 pci_release_regions(dev->pdev); 980 out_no_device: 981 ttm_object_device_release(&dev_priv->tdev); 982 out_err4: 983 memunmap(dev_priv->mmio_virt); 984 out_err0: 985 for (i = vmw_res_context; i < vmw_res_max; ++i) 986 idr_destroy(&dev_priv->res_idr[i]); 987 988 if (dev_priv->ctx.staged_bindings) 989 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 990 kfree(dev_priv); 991 return ret; 992 } 993 994 static void vmw_driver_unload(struct drm_device *dev) 995 { 996 struct vmw_private *dev_priv = vmw_priv(dev); 997 enum vmw_res_type i; 998 999 unregister_pm_notifier(&dev_priv->pm_nb); 1000 1001 if (dev_priv->ctx.res_ht_initialized) 1002 drm_ht_remove(&dev_priv->ctx.res_ht); 1003 vfree(dev_priv->ctx.cmd_bounce); 1004 if (dev_priv->enable_fb) { 1005 vmw_fb_off(dev_priv); 1006 vmw_fb_close(dev_priv); 1007 vmw_fifo_resource_dec(dev_priv); 1008 vmw_svga_disable(dev_priv); 1009 } 1010 1011 vmw_kms_close(dev_priv); 1012 vmw_overlay_close(dev_priv); 1013 1014 if (dev_priv->has_gmr) 1015 (void)ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_GMR); 1016 (void)ttm_bo_clean_mm(&dev_priv->bdev, TTM_PL_VRAM); 1017 1018 vmw_release_device_early(dev_priv); 1019 if (dev_priv->has_mob) 1020 (void) ttm_bo_clean_mm(&dev_priv->bdev, VMW_PL_MOB); 1021 (void) ttm_bo_device_release(&dev_priv->bdev); 1022 drm_vma_offset_manager_destroy(&dev_priv->vma_manager); 1023 vmw_release_device_late(dev_priv); 1024 vmw_fence_manager_takedown(dev_priv->fman); 1025 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1026 vmw_irq_uninstall(dev_priv->dev); 1027 if (dev_priv->stealth) 1028 pci_release_region(dev->pdev, 2); 1029 else 1030 pci_release_regions(dev->pdev); 1031 1032 ttm_object_device_release(&dev_priv->tdev); 1033 memunmap(dev_priv->mmio_virt); 1034 if (dev_priv->ctx.staged_bindings) 1035 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1036 1037 for (i = vmw_res_context; i < vmw_res_max; ++i) 1038 idr_destroy(&dev_priv->res_idr[i]); 1039 1040 kfree(dev_priv); 1041 } 1042 1043 static void vmw_postclose(struct drm_device *dev, 1044 struct drm_file *file_priv) 1045 { 1046 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1047 1048 ttm_object_file_release(&vmw_fp->tfile); 1049 kfree(vmw_fp); 1050 } 1051 1052 static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1053 { 1054 struct vmw_private *dev_priv = vmw_priv(dev); 1055 struct vmw_fpriv *vmw_fp; 1056 int ret = -ENOMEM; 1057 1058 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1059 if (unlikely(!vmw_fp)) 1060 return ret; 1061 1062 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1063 if (unlikely(vmw_fp->tfile == NULL)) 1064 goto out_no_tfile; 1065 1066 file_priv->driver_priv = vmw_fp; 1067 1068 return 0; 1069 1070 out_no_tfile: 1071 kfree(vmw_fp); 1072 return ret; 1073 } 1074 1075 static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1076 unsigned long arg, 1077 long (*ioctl_func)(struct file *, unsigned int, 1078 unsigned long)) 1079 { 1080 struct drm_file *file_priv = filp->private_data; 1081 struct drm_device *dev = file_priv->minor->dev; 1082 unsigned int nr = DRM_IOCTL_NR(cmd); 1083 unsigned int flags; 1084 1085 /* 1086 * Do extra checking on driver private ioctls. 1087 */ 1088 1089 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1090 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1091 const struct drm_ioctl_desc *ioctl = 1092 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1093 1094 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1095 return ioctl_func(filp, cmd, arg); 1096 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1097 if (!drm_is_current_master(file_priv) && 1098 !capable(CAP_SYS_ADMIN)) 1099 return -EACCES; 1100 } 1101 1102 if (unlikely(ioctl->cmd != cmd)) 1103 goto out_io_encoding; 1104 1105 flags = ioctl->flags; 1106 } else if (!drm_ioctl_flags(nr, &flags)) 1107 return -EINVAL; 1108 1109 return ioctl_func(filp, cmd, arg); 1110 1111 out_io_encoding: 1112 DRM_ERROR("Invalid command format, ioctl %d\n", 1113 nr - DRM_COMMAND_BASE); 1114 1115 return -EINVAL; 1116 } 1117 1118 static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1119 unsigned long arg) 1120 { 1121 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1122 } 1123 1124 #ifdef CONFIG_COMPAT 1125 static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1126 unsigned long arg) 1127 { 1128 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1129 } 1130 #endif 1131 1132 static int vmw_master_set(struct drm_device *dev, 1133 struct drm_file *file_priv, 1134 bool from_open) 1135 { 1136 /* 1137 * Inform a new master that the layout may have changed while 1138 * it was gone. 1139 */ 1140 if (!from_open) 1141 drm_sysfs_hotplug_event(dev); 1142 1143 return 0; 1144 } 1145 1146 static void vmw_master_drop(struct drm_device *dev, 1147 struct drm_file *file_priv) 1148 { 1149 struct vmw_private *dev_priv = vmw_priv(dev); 1150 1151 vmw_kms_legacy_hotspot_clear(dev_priv); 1152 if (!dev_priv->enable_fb) 1153 vmw_svga_disable(dev_priv); 1154 } 1155 1156 /** 1157 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1158 * 1159 * @dev_priv: Pointer to device private struct. 1160 * Needs the reservation sem to be held in non-exclusive mode. 1161 */ 1162 static void __vmw_svga_enable(struct vmw_private *dev_priv) 1163 { 1164 spin_lock(&dev_priv->svga_lock); 1165 if (!dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1166 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1167 dev_priv->bdev.man[TTM_PL_VRAM].use_type = true; 1168 } 1169 spin_unlock(&dev_priv->svga_lock); 1170 } 1171 1172 /** 1173 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1174 * 1175 * @dev_priv: Pointer to device private struct. 1176 */ 1177 void vmw_svga_enable(struct vmw_private *dev_priv) 1178 { 1179 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1180 __vmw_svga_enable(dev_priv); 1181 ttm_read_unlock(&dev_priv->reservation_sem); 1182 } 1183 1184 /** 1185 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1186 * 1187 * @dev_priv: Pointer to device private struct. 1188 * Needs the reservation sem to be held in exclusive mode. 1189 * Will not empty VRAM. VRAM must be emptied by caller. 1190 */ 1191 static void __vmw_svga_disable(struct vmw_private *dev_priv) 1192 { 1193 spin_lock(&dev_priv->svga_lock); 1194 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1195 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1196 vmw_write(dev_priv, SVGA_REG_ENABLE, 1197 SVGA_REG_ENABLE_HIDE | 1198 SVGA_REG_ENABLE_ENABLE); 1199 } 1200 spin_unlock(&dev_priv->svga_lock); 1201 } 1202 1203 /** 1204 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1205 * running. 1206 * 1207 * @dev_priv: Pointer to device private struct. 1208 * Will empty VRAM. 1209 */ 1210 void vmw_svga_disable(struct vmw_private *dev_priv) 1211 { 1212 /* 1213 * Disabling SVGA will turn off device modesetting capabilities, so 1214 * notify KMS about that so that it doesn't cache atomic state that 1215 * isn't valid anymore, for example crtcs turned on. 1216 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1217 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1218 * end up with lock order reversal. Thus, a master may actually perform 1219 * a new modeset just after we call vmw_kms_lost_device() and race with 1220 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1221 * to be inconsistent with the device, causing modesetting problems. 1222 * 1223 */ 1224 vmw_kms_lost_device(dev_priv->dev); 1225 ttm_write_lock(&dev_priv->reservation_sem, false); 1226 spin_lock(&dev_priv->svga_lock); 1227 if (dev_priv->bdev.man[TTM_PL_VRAM].use_type) { 1228 dev_priv->bdev.man[TTM_PL_VRAM].use_type = false; 1229 spin_unlock(&dev_priv->svga_lock); 1230 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1231 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1232 vmw_write(dev_priv, SVGA_REG_ENABLE, 1233 SVGA_REG_ENABLE_HIDE | 1234 SVGA_REG_ENABLE_ENABLE); 1235 } else 1236 spin_unlock(&dev_priv->svga_lock); 1237 ttm_write_unlock(&dev_priv->reservation_sem); 1238 } 1239 1240 static void vmw_remove(struct pci_dev *pdev) 1241 { 1242 struct drm_device *dev = pci_get_drvdata(pdev); 1243 1244 drm_dev_unregister(dev); 1245 vmw_driver_unload(dev); 1246 drm_dev_put(dev); 1247 pci_disable_device(pdev); 1248 } 1249 1250 static unsigned long 1251 vmw_get_unmapped_area(struct file *file, unsigned long uaddr, 1252 unsigned long len, unsigned long pgoff, 1253 unsigned long flags) 1254 { 1255 struct drm_file *file_priv = file->private_data; 1256 struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev); 1257 1258 return drm_get_unmapped_area(file, uaddr, len, pgoff, flags, 1259 &dev_priv->vma_manager); 1260 } 1261 1262 static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1263 void *ptr) 1264 { 1265 struct vmw_private *dev_priv = 1266 container_of(nb, struct vmw_private, pm_nb); 1267 1268 switch (val) { 1269 case PM_HIBERNATION_PREPARE: 1270 /* 1271 * Take the reservation sem in write mode, which will make sure 1272 * there are no other processes holding a buffer object 1273 * reservation, meaning we should be able to evict all buffer 1274 * objects if needed. 1275 * Once user-space processes have been frozen, we can release 1276 * the lock again. 1277 */ 1278 ttm_suspend_lock(&dev_priv->reservation_sem); 1279 dev_priv->suspend_locked = true; 1280 break; 1281 case PM_POST_HIBERNATION: 1282 case PM_POST_RESTORE: 1283 if (READ_ONCE(dev_priv->suspend_locked)) { 1284 dev_priv->suspend_locked = false; 1285 ttm_suspend_unlock(&dev_priv->reservation_sem); 1286 } 1287 break; 1288 default: 1289 break; 1290 } 1291 return 0; 1292 } 1293 1294 static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1295 { 1296 struct drm_device *dev = pci_get_drvdata(pdev); 1297 struct vmw_private *dev_priv = vmw_priv(dev); 1298 1299 if (dev_priv->refuse_hibernation) 1300 return -EBUSY; 1301 1302 pci_save_state(pdev); 1303 pci_disable_device(pdev); 1304 pci_set_power_state(pdev, PCI_D3hot); 1305 return 0; 1306 } 1307 1308 static int vmw_pci_resume(struct pci_dev *pdev) 1309 { 1310 pci_set_power_state(pdev, PCI_D0); 1311 pci_restore_state(pdev); 1312 return pci_enable_device(pdev); 1313 } 1314 1315 static int vmw_pm_suspend(struct device *kdev) 1316 { 1317 struct pci_dev *pdev = to_pci_dev(kdev); 1318 struct pm_message dummy; 1319 1320 dummy.event = 0; 1321 1322 return vmw_pci_suspend(pdev, dummy); 1323 } 1324 1325 static int vmw_pm_resume(struct device *kdev) 1326 { 1327 struct pci_dev *pdev = to_pci_dev(kdev); 1328 1329 return vmw_pci_resume(pdev); 1330 } 1331 1332 static int vmw_pm_freeze(struct device *kdev) 1333 { 1334 struct pci_dev *pdev = to_pci_dev(kdev); 1335 struct drm_device *dev = pci_get_drvdata(pdev); 1336 struct vmw_private *dev_priv = vmw_priv(dev); 1337 int ret; 1338 1339 /* 1340 * Unlock for vmw_kms_suspend. 1341 * No user-space processes should be running now. 1342 */ 1343 ttm_suspend_unlock(&dev_priv->reservation_sem); 1344 ret = vmw_kms_suspend(dev_priv->dev); 1345 if (ret) { 1346 ttm_suspend_lock(&dev_priv->reservation_sem); 1347 DRM_ERROR("Failed to freeze modesetting.\n"); 1348 return ret; 1349 } 1350 if (dev_priv->enable_fb) 1351 vmw_fb_off(dev_priv); 1352 1353 ttm_suspend_lock(&dev_priv->reservation_sem); 1354 vmw_execbuf_release_pinned_bo(dev_priv); 1355 vmw_resource_evict_all(dev_priv); 1356 vmw_release_device_early(dev_priv); 1357 ttm_bo_swapout_all(&dev_priv->bdev); 1358 if (dev_priv->enable_fb) 1359 vmw_fifo_resource_dec(dev_priv); 1360 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1361 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1362 if (dev_priv->enable_fb) 1363 vmw_fifo_resource_inc(dev_priv); 1364 WARN_ON(vmw_request_device_late(dev_priv)); 1365 dev_priv->suspend_locked = false; 1366 ttm_suspend_unlock(&dev_priv->reservation_sem); 1367 if (dev_priv->suspend_state) 1368 vmw_kms_resume(dev); 1369 if (dev_priv->enable_fb) 1370 vmw_fb_on(dev_priv); 1371 return -EBUSY; 1372 } 1373 1374 vmw_fence_fifo_down(dev_priv->fman); 1375 __vmw_svga_disable(dev_priv); 1376 1377 vmw_release_device_late(dev_priv); 1378 return 0; 1379 } 1380 1381 static int vmw_pm_restore(struct device *kdev) 1382 { 1383 struct pci_dev *pdev = to_pci_dev(kdev); 1384 struct drm_device *dev = pci_get_drvdata(pdev); 1385 struct vmw_private *dev_priv = vmw_priv(dev); 1386 int ret; 1387 1388 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1389 (void) vmw_read(dev_priv, SVGA_REG_ID); 1390 1391 if (dev_priv->enable_fb) 1392 vmw_fifo_resource_inc(dev_priv); 1393 1394 ret = vmw_request_device(dev_priv); 1395 if (ret) 1396 return ret; 1397 1398 if (dev_priv->enable_fb) 1399 __vmw_svga_enable(dev_priv); 1400 1401 vmw_fence_fifo_up(dev_priv->fman); 1402 dev_priv->suspend_locked = false; 1403 ttm_suspend_unlock(&dev_priv->reservation_sem); 1404 if (dev_priv->suspend_state) 1405 vmw_kms_resume(dev_priv->dev); 1406 1407 if (dev_priv->enable_fb) 1408 vmw_fb_on(dev_priv); 1409 1410 return 0; 1411 } 1412 1413 static const struct dev_pm_ops vmw_pm_ops = { 1414 .freeze = vmw_pm_freeze, 1415 .thaw = vmw_pm_restore, 1416 .restore = vmw_pm_restore, 1417 .suspend = vmw_pm_suspend, 1418 .resume = vmw_pm_resume, 1419 }; 1420 1421 static const struct file_operations vmwgfx_driver_fops = { 1422 .owner = THIS_MODULE, 1423 .open = drm_open, 1424 .release = drm_release, 1425 .unlocked_ioctl = vmw_unlocked_ioctl, 1426 .mmap = vmw_mmap, 1427 .poll = vmw_fops_poll, 1428 .read = vmw_fops_read, 1429 #if defined(CONFIG_COMPAT) 1430 .compat_ioctl = vmw_compat_ioctl, 1431 #endif 1432 .llseek = noop_llseek, 1433 .get_unmapped_area = vmw_get_unmapped_area, 1434 }; 1435 1436 static struct drm_driver driver = { 1437 .driver_features = 1438 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC, 1439 .ioctls = vmw_ioctls, 1440 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1441 .master_set = vmw_master_set, 1442 .master_drop = vmw_master_drop, 1443 .open = vmw_driver_open, 1444 .postclose = vmw_postclose, 1445 1446 .dumb_create = vmw_dumb_create, 1447 .dumb_map_offset = vmw_dumb_map_offset, 1448 .dumb_destroy = vmw_dumb_destroy, 1449 1450 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1451 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1452 1453 .fops = &vmwgfx_driver_fops, 1454 .name = VMWGFX_DRIVER_NAME, 1455 .desc = VMWGFX_DRIVER_DESC, 1456 .date = VMWGFX_DRIVER_DATE, 1457 .major = VMWGFX_DRIVER_MAJOR, 1458 .minor = VMWGFX_DRIVER_MINOR, 1459 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1460 }; 1461 1462 static struct pci_driver vmw_pci_driver = { 1463 .name = VMWGFX_DRIVER_NAME, 1464 .id_table = vmw_pci_id_list, 1465 .probe = vmw_probe, 1466 .remove = vmw_remove, 1467 .driver = { 1468 .pm = &vmw_pm_ops 1469 } 1470 }; 1471 1472 static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1473 { 1474 struct drm_device *dev; 1475 int ret; 1476 1477 ret = pci_enable_device(pdev); 1478 if (ret) 1479 return ret; 1480 1481 dev = drm_dev_alloc(&driver, &pdev->dev); 1482 if (IS_ERR(dev)) { 1483 ret = PTR_ERR(dev); 1484 goto err_pci_disable_device; 1485 } 1486 1487 dev->pdev = pdev; 1488 pci_set_drvdata(pdev, dev); 1489 1490 ret = vmw_driver_load(dev, ent->driver_data); 1491 if (ret) 1492 goto err_drm_dev_put; 1493 1494 ret = drm_dev_register(dev, ent->driver_data); 1495 if (ret) 1496 goto err_vmw_driver_unload; 1497 1498 return 0; 1499 1500 err_vmw_driver_unload: 1501 vmw_driver_unload(dev); 1502 err_drm_dev_put: 1503 drm_dev_put(dev); 1504 err_pci_disable_device: 1505 pci_disable_device(pdev); 1506 return ret; 1507 } 1508 1509 static int __init vmwgfx_init(void) 1510 { 1511 int ret; 1512 1513 if (vgacon_text_force()) 1514 return -EINVAL; 1515 1516 ret = pci_register_driver(&vmw_pci_driver); 1517 if (ret) 1518 DRM_ERROR("Failed initializing DRM.\n"); 1519 return ret; 1520 } 1521 1522 static void __exit vmwgfx_exit(void) 1523 { 1524 pci_unregister_driver(&vmw_pci_driver); 1525 } 1526 1527 module_init(vmwgfx_init); 1528 module_exit(vmwgfx_exit); 1529 1530 MODULE_AUTHOR("VMware Inc. and others"); 1531 MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1532 MODULE_LICENSE("GPL and additional rights"); 1533 MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1534 __stringify(VMWGFX_DRIVER_MINOR) "." 1535 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1536 "0"); 1537