1 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
2 /**********************************************************
3  * Copyright 1998-2015 VMware, Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person
6  * obtaining a copy of this software and associated documentation
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10  * of the Software, and to permit persons to whom the Software is
11  * furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
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15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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22  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23  * SOFTWARE.
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25  **********************************************************/
26 
27 /*
28  * svga_reg.h --
29  *
30  *    Virtual hardware definitions for the VMware SVGA II device.
31  */
32 
33 #ifndef _SVGA_REG_H_
34 #define _SVGA_REG_H_
35 #include <linux/pci_ids.h>
36 
37 #define INCLUDE_ALLOW_MODULE
38 #define INCLUDE_ALLOW_USERLEVEL
39 
40 #define INCLUDE_ALLOW_VMCORE
41 #include "includeCheck.h"
42 
43 #include "svga_types.h"
44 
45 /*
46  * SVGA_REG_ENABLE bit definitions.
47  */
48 typedef enum {
49    SVGA_REG_ENABLE_DISABLE = 0,
50    SVGA_REG_ENABLE_ENABLE = (1 << 0),
51    SVGA_REG_ENABLE_HIDE = (1 << 1),
52 } SvgaRegEnable;
53 
54 typedef uint32 SVGAMobId;
55 
56 /*
57  * Arbitrary and meaningless limits. Please ignore these when writing
58  * new drivers.
59  */
60 #define SVGA_MAX_WIDTH                  2560
61 #define SVGA_MAX_HEIGHT                 1600
62 
63 
64 #define SVGA_MAX_BITS_PER_PIXEL         32
65 #define SVGA_MAX_DEPTH                  24
66 #define SVGA_MAX_DISPLAYS               10
67 #define SVGA_MAX_SCREEN_SIZE            8192
68 #define SVGA_SCREEN_ROOT_LIMIT (SVGA_MAX_SCREEN_SIZE * SVGA_MAX_DISPLAYS)
69 
70 
71 /*
72  * Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
73  * cursor bypass mode. This is still supported, but no new guest
74  * drivers should use it.
75  */
76 #define SVGA_CURSOR_ON_HIDE            0x0
77 #define SVGA_CURSOR_ON_SHOW            0x1
78 
79 /*
80  * Remove the cursor from the framebuffer
81  * because we need to see what's under it
82  */
83 #define SVGA_CURSOR_ON_REMOVE_FROM_FB  0x2
84 
85 /* Put the cursor back in the framebuffer so the user can see it */
86 #define SVGA_CURSOR_ON_RESTORE_TO_FB   0x3
87 
88 /*
89  * The maximum framebuffer size that can traced for guests unless the
90  * SVGA_CAP_GBOBJECTS is set in SVGA_REG_CAPABILITIES.  In that case
91  * the full framebuffer can be traced independent of this limit.
92  */
93 #define SVGA_FB_MAX_TRACEABLE_SIZE      0x1000000
94 
95 #define SVGA_MAX_PSEUDOCOLOR_DEPTH      8
96 #define SVGA_MAX_PSEUDOCOLORS           (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
97 #define SVGA_NUM_PALETTE_REGS           (3 * SVGA_MAX_PSEUDOCOLORS)
98 
99 #define SVGA_MAGIC         0x900000UL
100 #define SVGA_MAKE_ID(ver)  (SVGA_MAGIC << 8 | (ver))
101 
102 /* Version 2 let the address of the frame buffer be unsigned on Win32 */
103 #define SVGA_VERSION_2     2
104 #define SVGA_ID_2          SVGA_MAKE_ID(SVGA_VERSION_2)
105 
106 /* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
107    PALETTE_BASE has moved */
108 #define SVGA_VERSION_1     1
109 #define SVGA_ID_1          SVGA_MAKE_ID(SVGA_VERSION_1)
110 
111 /* Version 0 is the initial version */
112 #define SVGA_VERSION_0     0
113 #define SVGA_ID_0          SVGA_MAKE_ID(SVGA_VERSION_0)
114 
115 /*
116  * "Invalid" value for all SVGA IDs.
117  * (Version ID, screen object ID, surface ID...)
118  */
119 #define SVGA_ID_INVALID    0xFFFFFFFF
120 
121 /* Port offsets, relative to BAR0 */
122 #define SVGA_INDEX_PORT         0x0
123 #define SVGA_VALUE_PORT         0x1
124 #define SVGA_BIOS_PORT          0x2
125 #define SVGA_IRQSTATUS_PORT     0x8
126 
127 /*
128  * Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
129  *
130  * Interrupts are only supported when the
131  * SVGA_CAP_IRQMASK capability is present.
132  */
133 #define SVGA_IRQFLAG_ANY_FENCE            0x1    /* Any fence was passed */
134 #define SVGA_IRQFLAG_FIFO_PROGRESS        0x2    /* Made forward progress in the FIFO */
135 #define SVGA_IRQFLAG_FENCE_GOAL           0x4    /* SVGA_FIFO_FENCE_GOAL reached */
136 #define SVGA_IRQFLAG_COMMAND_BUFFER       0x8    /* Command buffer completed */
137 #define SVGA_IRQFLAG_ERROR                0x10   /* Error while processing commands */
138 
139 /*
140  * Registers
141  */
142 
143 enum {
144    SVGA_REG_ID = 0,
145    SVGA_REG_ENABLE = 1,
146    SVGA_REG_WIDTH = 2,
147    SVGA_REG_HEIGHT = 3,
148    SVGA_REG_MAX_WIDTH = 4,
149    SVGA_REG_MAX_HEIGHT = 5,
150    SVGA_REG_DEPTH = 6,
151    SVGA_REG_BITS_PER_PIXEL = 7,       /* Current bpp in the guest */
152    SVGA_REG_PSEUDOCOLOR = 8,
153    SVGA_REG_RED_MASK = 9,
154    SVGA_REG_GREEN_MASK = 10,
155    SVGA_REG_BLUE_MASK = 11,
156    SVGA_REG_BYTES_PER_LINE = 12,
157    SVGA_REG_FB_START = 13,            /* (Deprecated) */
158    SVGA_REG_FB_OFFSET = 14,
159    SVGA_REG_VRAM_SIZE = 15,
160    SVGA_REG_FB_SIZE = 16,
161 
162    /* ID 0 implementation only had the above registers, then the palette */
163    SVGA_REG_ID_0_TOP = 17,
164 
165    SVGA_REG_CAPABILITIES = 17,
166    SVGA_REG_MEM_START = 18,           /* (Deprecated) */
167    SVGA_REG_MEM_SIZE = 19,
168    SVGA_REG_CONFIG_DONE = 20,         /* Set when memory area configured */
169    SVGA_REG_SYNC = 21,                /* See "FIFO Synchronization Registers" */
170    SVGA_REG_BUSY = 22,                /* See "FIFO Synchronization Registers" */
171    SVGA_REG_GUEST_ID = 23,            /* (Deprecated) */
172    SVGA_REG_CURSOR_ID = 24,           /* (Deprecated) */
173    SVGA_REG_CURSOR_X = 25,            /* (Deprecated) */
174    SVGA_REG_CURSOR_Y = 26,            /* (Deprecated) */
175    SVGA_REG_CURSOR_ON = 27,           /* (Deprecated) */
176    SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */
177    SVGA_REG_SCRATCH_SIZE = 29,        /* Number of scratch registers */
178    SVGA_REG_MEM_REGS = 30,            /* Number of FIFO registers */
179    SVGA_REG_NUM_DISPLAYS = 31,        /* (Deprecated) */
180    SVGA_REG_PITCHLOCK = 32,           /* Fixed pitch for all modes */
181    SVGA_REG_IRQMASK = 33,             /* Interrupt mask */
182 
183    /* Legacy multi-monitor support */
184    SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */
185    SVGA_REG_DISPLAY_ID = 35,        /* Display ID for the following display attributes */
186    SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */
187    SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */
188    SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */
189    SVGA_REG_DISPLAY_WIDTH = 39,     /* The display's width */
190    SVGA_REG_DISPLAY_HEIGHT = 40,    /* The display's height */
191 
192    /* See "Guest memory regions" below. */
193    SVGA_REG_GMR_ID = 41,
194    SVGA_REG_GMR_DESCRIPTOR = 42,
195    SVGA_REG_GMR_MAX_IDS = 43,
196    SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44,
197 
198    SVGA_REG_TRACES = 45,            /* Enable trace-based updates even when FIFO is on */
199    SVGA_REG_GMRS_MAX_PAGES = 46,    /* Maximum number of 4KB pages for all GMRs */
200    SVGA_REG_MEMORY_SIZE = 47,       /* Total dedicated device memory excluding FIFO */
201    SVGA_REG_COMMAND_LOW = 48,       /* Lower 32 bits and submits commands */
202    SVGA_REG_COMMAND_HIGH = 49,      /* Upper 32 bits of command buffer PA */
203 
204    /*
205     * Max primary memory.
206     * See SVGA_CAP_NO_BB_RESTRICTION.
207     */
208    SVGA_REG_MAX_PRIMARY_MEM = 50,
209    SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50,
210 
211    SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */
212    SVGA_REG_DEV_CAP = 52,           /* Write dev cap index, read value */
213    SVGA_REG_CMD_PREPEND_LOW = 53,
214    SVGA_REG_CMD_PREPEND_HIGH = 54,
215    SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
216    SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
217    SVGA_REG_MOB_MAX_SIZE = 57,
218    SVGA_REG_BLANK_SCREEN_TARGETS = 58,
219    SVGA_REG_CAP2 = 59,
220    SVGA_REG_DEVEL_CAP = 60,
221    SVGA_REG_TOP = 61,               /* Must be 1 more than the last register */
222 
223    SVGA_PALETTE_BASE = 1024,        /* Base of SVGA color map */
224    /* Next 768 (== 256*3) registers exist for colormap */
225    SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
226                                     /* Base of scratch registers */
227    /* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
228       First 4 are reserved for VESA BIOS Extension; any remaining are for
229       the use of the current SVGA driver. */
230 };
231 
232 /*
233  * Guest memory regions (GMRs):
234  *
235  * This is a new memory mapping feature available in SVGA devices
236  * which have the SVGA_CAP_GMR bit set. Previously, there were two
237  * fixed memory regions available with which to share data between the
238  * device and the driver: the FIFO ('MEM') and the framebuffer. GMRs
239  * are our name for an extensible way of providing arbitrary DMA
240  * buffers for use between the driver and the SVGA device. They are a
241  * new alternative to framebuffer memory, usable for both 2D and 3D
242  * graphics operations.
243  *
244  * Since GMR mapping must be done synchronously with guest CPU
245  * execution, we use a new pair of SVGA registers:
246  *
247  *   SVGA_REG_GMR_ID --
248  *
249  *     Read/write.
250  *     This register holds the 32-bit ID (a small positive integer)
251  *     of a GMR to create, delete, or redefine. Writing this register
252  *     has no side-effects.
253  *
254  *   SVGA_REG_GMR_DESCRIPTOR --
255  *
256  *     Write-only.
257  *     Writing this register will create, delete, or redefine the GMR
258  *     specified by the above ID register. If this register is zero,
259  *     the GMR is deleted. Any pointers into this GMR (including those
260  *     currently being processed by FIFO commands) will be
261  *     synchronously invalidated.
262  *
263  *     If this register is nonzero, it must be the physical page
264  *     number (PPN) of a data structure which describes the physical
265  *     layout of the memory region this GMR should describe. The
266  *     descriptor structure will be read synchronously by the SVGA
267  *     device when this register is written. The descriptor need not
268  *     remain allocated for the lifetime of the GMR.
269  *
270  *     The guest driver should write SVGA_REG_GMR_ID first, then
271  *     SVGA_REG_GMR_DESCRIPTOR.
272  *
273  *   SVGA_REG_GMR_MAX_IDS --
274  *
275  *     Read-only.
276  *     The SVGA device may choose to support a maximum number of
277  *     user-defined GMR IDs. This register holds the number of supported
278  *     IDs. (The maximum supported ID plus 1)
279  *
280  *   SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH --
281  *
282  *     Read-only.
283  *     The SVGA device may choose to put a limit on the total number
284  *     of SVGAGuestMemDescriptor structures it will read when defining
285  *     a single GMR.
286  *
287  * The descriptor structure is an array of SVGAGuestMemDescriptor
288  * structures. Each structure may do one of three things:
289  *
290  *   - Terminate the GMR descriptor list.
291  *     (ppn==0, numPages==0)
292  *
293  *   - Add a PPN or range of PPNs to the GMR's virtual address space.
294  *     (ppn != 0, numPages != 0)
295  *
296  *   - Provide the PPN of the next SVGAGuestMemDescriptor, in order to
297  *     support multi-page GMR descriptor tables without forcing the
298  *     driver to allocate physically contiguous memory.
299  *     (ppn != 0, numPages == 0)
300  *
301  * Note that each physical page of SVGAGuestMemDescriptor structures
302  * can describe at least 2MB of guest memory. If the driver needs to
303  * use more than one page of descriptor structures, it must use one of
304  * its SVGAGuestMemDescriptors to point to an additional page.  The
305  * device will never automatically cross a page boundary.
306  *
307  * Once the driver has described a GMR, it is immediately available
308  * for use via any FIFO command that uses an SVGAGuestPtr structure.
309  * These pointers include a GMR identifier plus an offset into that
310  * GMR.
311  *
312  * The driver must check the SVGA_CAP_GMR bit before using the GMR
313  * registers.
314  */
315 
316 /*
317  * Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer
318  * memory as well.  In the future, these IDs could even be used to
319  * allow legacy memory regions to be redefined by the guest as GMRs.
320  *
321  * Using the guest framebuffer (GFB) at BAR1 for general purpose DMA
322  * is being phased out. Please try to use user-defined GMRs whenever
323  * possible.
324  */
325 #define SVGA_GMR_NULL         ((uint32) -1)
326 #define SVGA_GMR_FRAMEBUFFER  ((uint32) -2)  /* Guest Framebuffer (GFB) */
327 
328 typedef
329 #include "vmware_pack_begin.h"
330 struct SVGAGuestMemDescriptor {
331    uint32 ppn;
332    uint32 numPages;
333 }
334 #include "vmware_pack_end.h"
335 SVGAGuestMemDescriptor;
336 
337 typedef
338 #include "vmware_pack_begin.h"
339 struct SVGAGuestPtr {
340    uint32 gmrId;
341    uint32 offset;
342 }
343 #include "vmware_pack_end.h"
344 SVGAGuestPtr;
345 
346 /*
347  * Register based command buffers --
348  *
349  * Provide an SVGA device interface that allows the guest to submit
350  * command buffers to the SVGA device through an SVGA device register.
351  * The metadata for each command buffer is contained in the
352  * SVGACBHeader structure along with the return status codes.
353  *
354  * The SVGA device supports command buffers if
355  * SVGA_CAP_COMMAND_BUFFERS is set in the device caps register.  The
356  * fifo must be enabled for command buffers to be submitted.
357  *
358  * Command buffers are submitted when the guest writing the 64 byte
359  * aligned physical address into the SVGA_REG_COMMAND_LOW and
360  * SVGA_REG_COMMAND_HIGH.  SVGA_REG_COMMAND_HIGH contains the upper 32
361  * bits of the physical address.  SVGA_REG_COMMAND_LOW contains the
362  * lower 32 bits of the physical address, since the command buffer
363  * headers are required to be 64 byte aligned the lower 6 bits are
364  * used for the SVGACBContext value.  Writing to SVGA_REG_COMMAND_LOW
365  * submits the command buffer to the device and queues it for
366  * execution.  The SVGA device supports at least
367  * SVGA_CB_MAX_QUEUED_PER_CONTEXT command buffers that can be queued
368  * per context and if that limit is reached the device will write the
369  * status SVGA_CB_STATUS_QUEUE_FULL to the status value of the command
370  * buffer header synchronously and not raise any IRQs.
371  *
372  * It is invalid to submit a command buffer without a valid physical
373  * address and results are undefined.
374  *
375  * The device guarantees that command buffers of size SVGA_CB_MAX_SIZE
376  * will be supported.  If a larger command buffer is submitted results
377  * are unspecified and the device will either complete the command
378  * buffer or return an error.
379  *
380  * The device guarantees that any individual command in a command
381  * buffer can be up to SVGA_CB_MAX_COMMAND_SIZE in size which is
382  * enough to fit a 64x64 color-cursor definition.  If the command is
383  * too large the device is allowed to process the command or return an
384  * error.
385  *
386  * The device context is a special SVGACBContext that allows for
387  * synchronous register like accesses with the flexibility of
388  * commands.  There is a different command set defined by
389  * SVGADeviceContextCmdId.  The commands in each command buffer is not
390  * allowed to straddle physical pages.
391  *
392  * The offset field which is available starting with the
393  * SVGA_CAP_CMD_BUFFERS_2 cap bit can be set by the guest to bias the
394  * start of command processing into the buffer.  If an error is
395  * encountered the errorOffset will still be relative to the specific
396  * PA, not biased by the offset.  When the command buffer is finished
397  * the guest should not read the offset field as there is no guarantee
398  * what it will set to.
399  *
400  * When the SVGA_CAP_HP_CMD_QUEUE cap bit is set a new command queue
401  * SVGA_CB_CONTEXT_1 is available.  Commands submitted to this queue
402  * will be executed as quickly as possible by the SVGA device
403  * potentially before already queued commands on SVGA_CB_CONTEXT_0.
404  * The SVGA device guarantees that any command buffers submitted to
405  * SVGA_CB_CONTEXT_0 will be executed after any _already_ submitted
406  * command buffers to SVGA_CB_CONTEXT_1.
407  */
408 
409 #define SVGA_CB_MAX_SIZE (512 * 1024)  /* 512 KB */
410 #define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32
411 #define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) /* 32 KB */
412 
413 #define SVGA_CB_CONTEXT_MASK 0x3f
414 typedef enum {
415    SVGA_CB_CONTEXT_DEVICE = 0x3f,
416    SVGA_CB_CONTEXT_0      = 0x0,
417    SVGA_CB_CONTEXT_1      = 0x1, /* Supported with SVGA_CAP_HP_CMD_QUEUE */
418    SVGA_CB_CONTEXT_MAX    = 0x2,
419    SVGA_CB_CONTEXT_HP_MAX = 0x2,
420 } SVGACBContext;
421 
422 
423 typedef enum {
424    /*
425     * The guest is supposed to write SVGA_CB_STATUS_NONE to the status
426     * field before submitting the command buffer header, the host will
427     * change the value when it is done with the command buffer.
428     */
429    SVGA_CB_STATUS_NONE             = 0,
430 
431    /*
432     * Written by the host when a command buffer completes successfully.
433     * The device raises an IRQ with SVGA_IRQFLAG_COMMAND_BUFFER unless
434     * the SVGA_CB_FLAG_NO_IRQ flag is set.
435     */
436    SVGA_CB_STATUS_COMPLETED        = 1,
437 
438    /*
439     * Written by the host synchronously with the command buffer
440     * submission to indicate the command buffer was not submitted.  No
441     * IRQ is raised.
442     */
443    SVGA_CB_STATUS_QUEUE_FULL       = 2,
444 
445    /*
446     * Written by the host when an error was detected parsing a command
447     * in the command buffer, errorOffset is written to contain the
448     * offset to the first byte of the failing command.  The device
449     * raises the IRQ with both SVGA_IRQFLAG_ERROR and
450     * SVGA_IRQFLAG_COMMAND_BUFFER.  Some of the commands may have been
451     * processed.
452     */
453    SVGA_CB_STATUS_COMMAND_ERROR    = 3,
454 
455    /*
456     * Written by the host if there is an error parsing the command
457     * buffer header.  The device raises the IRQ with both
458     * SVGA_IRQFLAG_ERROR and SVGA_IRQFLAG_COMMAND_BUFFER.  The device
459     * did not processes any of the command buffer.
460     */
461    SVGA_CB_STATUS_CB_HEADER_ERROR  = 4,
462 
463    /*
464     * Written by the host if the guest requested the host to preempt
465     * the command buffer.  The device will not raise any IRQs and the
466     * command buffer was not processed.
467     */
468    SVGA_CB_STATUS_PREEMPTED        = 5,
469 
470    /*
471     * Written by the host synchronously with the command buffer
472     * submission to indicate the the command buffer was not submitted
473     * due to an error.  No IRQ is raised.
474     */
475    SVGA_CB_STATUS_SUBMISSION_ERROR = 6,
476 
477    /*
478     * Written by the host when the host finished a
479     * SVGA_DC_CMD_ASYNC_STOP_QUEUE request for this command buffer
480     * queue.  The offset of the first byte not processed is stored in
481     * the errorOffset field of the command buffer header.  All guest
482     * visible side effects of commands till that point are guaranteed
483     * to be finished before this is written.  The
484     * SVGA_IRQFLAG_COMMAND_BUFFER IRQ is raised as long as the
485     * SVGA_CB_FLAG_NO_IRQ is not set.
486     */
487    SVGA_CB_STATUS_PARTIAL_COMPLETE = 7,
488 } SVGACBStatus;
489 
490 typedef enum {
491    SVGA_CB_FLAG_NONE       = 0,
492    SVGA_CB_FLAG_NO_IRQ     = 1 << 0,
493    SVGA_CB_FLAG_DX_CONTEXT = 1 << 1,
494    SVGA_CB_FLAG_MOB        = 1 << 2,
495 } SVGACBFlags;
496 
497 typedef
498 #include "vmware_pack_begin.h"
499 struct {
500    volatile SVGACBStatus status; /* Modified by device. */
501    volatile uint32 errorOffset;  /* Modified by device. */
502    uint64 id;
503    SVGACBFlags flags;
504    uint32 length;
505    union {
506       PA pa;
507       struct {
508          SVGAMobId mobid;
509          uint32 mobOffset;
510       } mob;
511    } ptr;
512    uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise,
513                    * modified by device.
514                    */
515    uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */
516    uint32 mustBeZero[6];
517 }
518 #include "vmware_pack_end.h"
519 SVGACBHeader;
520 
521 typedef enum {
522    SVGA_DC_CMD_NOP                   = 0,
523    SVGA_DC_CMD_START_STOP_CONTEXT    = 1,
524    SVGA_DC_CMD_PREEMPT               = 2,
525    SVGA_DC_CMD_START_QUEUE           = 3, /* Requires SVGA_CAP_HP_CMD_QUEUE */
526    SVGA_DC_CMD_ASYNC_STOP_QUEUE      = 4, /* Requires SVGA_CAP_HP_CMD_QUEUE */
527    SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE   = 5, /* Requires SVGA_CAP_HP_CMD_QUEUE */
528    SVGA_DC_CMD_MAX                   = 6,
529 } SVGADeviceContextCmdId;
530 
531 /*
532  * Starts or stops both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1.
533  */
534 
535 typedef struct SVGADCCmdStartStop {
536    uint32 enable;
537    SVGACBContext context; /* Must be zero */
538 } SVGADCCmdStartStop;
539 
540 /*
541  * SVGADCCmdPreempt --
542  *
543  * This command allows the guest to request that all command buffers
544  * on SVGA_CB_CONTEXT_0 be preempted that can be.  After execution
545  * of this command all command buffers that were preempted will
546  * already have SVGA_CB_STATUS_PREEMPTED written into the status
547  * field.  The device might still be processing a command buffer,
548  * assuming execution of it started before the preemption request was
549  * received.  Specifying the ignoreIDZero flag to TRUE will cause the
550  * device to not preempt command buffers with the id field in the
551  * command buffer header set to zero.
552  */
553 
554 typedef struct SVGADCCmdPreempt {
555    SVGACBContext context; /* Must be zero */
556    uint32 ignoreIDZero;
557 } SVGADCCmdPreempt;
558 
559 /*
560  * Starts the requested command buffer processing queue.  Valid only
561  * if the SVGA_CAP_HP_CMD_QUEUE cap is set.
562  *
563  * For a command queue to be considered runnable it must be enabled
564  * and any corresponding higher priority queues must also be enabled.
565  * For example in order for command buffers to be processed on
566  * SVGA_CB_CONTEXT_0 both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1 must
567  * be enabled.  But for commands to be runnable on SVGA_CB_CONTEXT_1
568  * only that queue must be enabled.
569  */
570 
571 typedef struct SVGADCCmdStartQueue {
572    SVGACBContext context;
573 } SVGADCCmdStartQueue;
574 
575 /*
576  * Requests the SVGA device to stop processing the requested command
577  * buffer queue as soon as possible.  The guest knows the stop has
578  * completed when one of the following happens.
579  *
580  * 1) A command buffer status of SVGA_CB_STATUS_PARTIAL_COMPLETE is returned
581  * 2) A command buffer error is encountered with would stop the queue
582  *    regardless of the async stop request.
583  * 3) All command buffers that have been submitted complete successfully.
584  * 4) The stop completes synchronously if no command buffers are
585  *    active on the queue when it is issued.
586  *
587  * If the command queue is not in a runnable state there is no
588  * guarentee this async stop will finish.  For instance if the high
589  * priority queue is not enabled and a stop is requested on the low
590  * priority queue, the high priority queue must be reenabled to
591  * guarantee that the async stop will finish.
592  *
593  * This command along with SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE can be used
594  * to implement mid command buffer preemption.
595  *
596  * Valid only if the SVGA_CAP_HP_CMD_QUEUE cap is set.
597  */
598 
599 typedef struct SVGADCCmdAsyncStopQueue {
600    SVGACBContext context;
601 } SVGADCCmdAsyncStopQueue;
602 
603 /*
604  * Requests the SVGA device to throw away any full command buffers on
605  * the requested command queue that have not been started.  For a
606  * driver to know which command buffers were thrown away a driver
607  * should only issue this command when the queue is stopped, for
608  * whatever reason.
609  */
610 
611 typedef struct SVGADCCmdEmptyQueue {
612    SVGACBContext context;
613 } SVGADCCmdEmptyQueue;
614 
615 
616 /*
617  * SVGAGMRImageFormat --
618  *
619  *    This is a packed representation of the source 2D image format
620  *    for a GMR-to-screen blit. Currently it is defined as an encoding
621  *    of the screen's color depth and bits-per-pixel, however, 16 bits
622  *    are reserved for future use to identify other encodings (such as
623  *    RGBA or higher-precision images).
624  *
625  *    Currently supported formats:
626  *
627  *       bpp depth  Format Name
628  *       --- -----  -----------
629  *        32    24  32-bit BGRX
630  *        24    24  24-bit BGR
631  *        16    16  RGB 5-6-5
632  *        16    15  RGB 5-5-5
633  *
634  */
635 
636 typedef struct SVGAGMRImageFormat {
637    union {
638       struct {
639          uint32 bitsPerPixel : 8;
640          uint32 colorDepth   : 8;
641          uint32 reserved     : 16;  /* Must be zero */
642       };
643 
644       uint32 value;
645    };
646 } SVGAGMRImageFormat;
647 
648 typedef
649 #include "vmware_pack_begin.h"
650 struct SVGAGuestImage {
651    SVGAGuestPtr         ptr;
652 
653    /*
654     * A note on interpretation of pitch: This value of pitch is the
655     * number of bytes between vertically adjacent image
656     * blocks. Normally this is the number of bytes between the first
657     * pixel of two adjacent scanlines. With compressed textures,
658     * however, this may represent the number of bytes between
659     * compression blocks rather than between rows of pixels.
660     *
661     * XXX: Compressed textures currently must be tightly packed in guest memory.
662     *
663     * If the image is 1-dimensional, pitch is ignored.
664     *
665     * If 'pitch' is zero, the SVGA3D device calculates a pitch value
666     * assuming each row of blocks is tightly packed.
667     */
668    uint32 pitch;
669 }
670 #include "vmware_pack_end.h"
671 SVGAGuestImage;
672 
673 /*
674  * SVGAColorBGRX --
675  *
676  *    A 24-bit color format (BGRX), which does not depend on the
677  *    format of the legacy guest framebuffer (GFB) or the current
678  *    GMRFB state.
679  */
680 
681 typedef struct SVGAColorBGRX {
682    union {
683       struct {
684          uint32 b : 8;
685          uint32 g : 8;
686          uint32 r : 8;
687 	 uint32 x : 8;  /* Unused */
688       };
689 
690       uint32 value;
691    };
692 } SVGAColorBGRX;
693 
694 
695 /*
696  * SVGASignedRect --
697  * SVGASignedPoint --
698  *
699  *    Signed rectangle and point primitives. These are used by the new
700  *    2D primitives for drawing to Screen Objects, which can occupy a
701  *    signed virtual coordinate space.
702  *
703  *    SVGASignedRect specifies a half-open interval: the (left, top)
704  *    pixel is part of the rectangle, but the (right, bottom) pixel is
705  *    not.
706  */
707 
708 typedef
709 #include "vmware_pack_begin.h"
710 struct {
711    int32  left;
712    int32  top;
713    int32  right;
714    int32  bottom;
715 }
716 #include "vmware_pack_end.h"
717 SVGASignedRect;
718 
719 typedef
720 #include "vmware_pack_begin.h"
721 struct {
722    int32  x;
723    int32  y;
724 }
725 #include "vmware_pack_end.h"
726 SVGASignedPoint;
727 
728 
729 /*
730  * SVGA Device Capabilities
731  *
732  * Note the holes in the bitfield. Missing bits have been deprecated,
733  * and must not be reused. Those capabilities will never be reported
734  * by new versions of the SVGA device.
735  *
736  * XXX: Add longer descriptions for each capability, including a list
737  *      of the new features that each capability provides.
738  *
739  * SVGA_CAP_IRQMASK --
740  *    Provides device interrupts.  Adds device register SVGA_REG_IRQMASK
741  *    to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
742  *    set/clear pending interrupts.
743  *
744  * SVGA_CAP_GMR --
745  *    Provides synchronous mapping of guest memory regions (GMR).
746  *    Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR,
747  *    SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH.
748  *
749  * SVGA_CAP_TRACES --
750  *    Allows framebuffer trace-based updates even when FIFO is enabled.
751  *    Adds device register SVGA_REG_TRACES.
752  *
753  * SVGA_CAP_GMR2 --
754  *    Provides asynchronous commands to define and remap guest memory
755  *    regions.  Adds device registers SVGA_REG_GMRS_MAX_PAGES and
756  *    SVGA_REG_MEMORY_SIZE.
757  *
758  * SVGA_CAP_SCREEN_OBJECT_2 --
759  *    Allow screen object support, and require backing stores from the
760  *    guest for each screen object.
761  *
762  * SVGA_CAP_COMMAND_BUFFERS --
763  *    Enable register based command buffer submission.
764  *
765  * SVGA_CAP_DEAD1 --
766  *    This cap was incorrectly used by old drivers and should not be
767  *    reused.
768  *
769  * SVGA_CAP_CMD_BUFFERS_2 --
770  *    Enable support for the prepend command buffer submision
771  *    registers.  SVGA_REG_CMD_PREPEND_LOW and
772  *    SVGA_REG_CMD_PREPEND_HIGH.
773  *
774  * SVGA_CAP_GBOBJECTS --
775  *    Enable guest-backed objects and surfaces.
776  *
777  * SVGA_CAP_DX --
778  *    Enable support for DX commands, and command buffers in a mob.
779  *
780  * SVGA_CAP_HP_CMD_QUEUE --
781  *    Enable support for the high priority command queue, and the
782  *    ScreenCopy command.
783  *
784  * SVGA_CAP_NO_BB_RESTRICTION --
785  *    Allow ScreenTargets to be defined without regard to the 32-bpp
786  *    bounding-box memory restrictions. ie:
787  *
788  *    The summed memory usage of all screens (assuming they were defined as
789  *    32-bpp) must always be less than the value of the
790  *    SVGA_REG_MAX_PRIMARY_MEM register.
791  *
792  *    If this cap is not present, the 32-bpp bounding box around all screens
793  *    must additionally be under the value of the SVGA_REG_MAX_PRIMARY_MEM
794  *    register.
795  *
796  *    If the cap is present, the bounding box restriction is lifted (and only
797  *    the screen-sum limit applies).
798  *
799  *    (Note that this is a slight lie... there is still a sanity limit on any
800  *     dimension of the topology to be less than SVGA_SCREEN_ROOT_LIMIT, even
801  *     when SVGA_CAP_NO_BB_RESTRICTION is present, but that should be
802  *     large enough to express any possible topology without holes between
803  *     monitors.)
804  *
805  * SVGA_CAP_CAP2_REGISTER --
806  *    If this cap is present, the SVGA_REG_CAP2 register is supported.
807  */
808 
809 #define SVGA_CAP_NONE               0x00000000
810 #define SVGA_CAP_RECT_COPY          0x00000002
811 #define SVGA_CAP_CURSOR             0x00000020
812 #define SVGA_CAP_CURSOR_BYPASS      0x00000040
813 #define SVGA_CAP_CURSOR_BYPASS_2    0x00000080
814 #define SVGA_CAP_8BIT_EMULATION     0x00000100
815 #define SVGA_CAP_ALPHA_CURSOR       0x00000200
816 #define SVGA_CAP_3D                 0x00004000
817 #define SVGA_CAP_EXTENDED_FIFO      0x00008000
818 #define SVGA_CAP_MULTIMON           0x00010000
819 #define SVGA_CAP_PITCHLOCK          0x00020000
820 #define SVGA_CAP_IRQMASK            0x00040000
821 #define SVGA_CAP_DISPLAY_TOPOLOGY   0x00080000
822 #define SVGA_CAP_GMR                0x00100000
823 #define SVGA_CAP_TRACES             0x00200000
824 #define SVGA_CAP_GMR2               0x00400000
825 #define SVGA_CAP_SCREEN_OBJECT_2    0x00800000
826 #define SVGA_CAP_COMMAND_BUFFERS    0x01000000
827 #define SVGA_CAP_DEAD1              0x02000000
828 #define SVGA_CAP_CMD_BUFFERS_2      0x04000000
829 #define SVGA_CAP_GBOBJECTS          0x08000000
830 #define SVGA_CAP_DX                 0x10000000
831 #define SVGA_CAP_HP_CMD_QUEUE       0x20000000
832 #define SVGA_CAP_NO_BB_RESTRICTION  0x40000000
833 #define SVGA_CAP_CAP2_REGISTER      0x80000000
834 
835 /*
836  * The SVGA_REG_CAP2 register is an additional set of SVGA capability bits.
837  *
838  * SVGA_CAP2_GROW_OTABLE --
839  *      Allow the GrowOTable/DXGrowCOTable commands.
840  *
841  * SVGA_CAP2_INTRA_SURFACE_COPY --
842  *      Allow the IntraSurfaceCopy command.
843  *
844  * SVGA_CAP2_DX2 --
845  *      Allow the DefineGBSurface_v3, WholeSurfaceCopy.
846  *
847  * SVGA_CAP2_RESERVED --
848  *      Reserve the last bit for extending the SVGA capabilities to some
849  *      future mechanisms.
850  */
851 #define SVGA_CAP2_NONE               0x00000000
852 #define SVGA_CAP2_GROW_OTABLE        0x00000001
853 #define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
854 #define SVGA_CAP2_DX2                0x00000004
855 #define SVGA_CAP2_RESERVED           0x80000000
856 
857 
858 /*
859  * The Guest can optionally read some SVGA device capabilities through
860  * the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before
861  * the SVGA device is initialized.  The type of capability the guest
862  * is requesting from the SVGABackdoorCapType enum should be placed in
863  * the upper 16 bits of the backdoor command id (ECX).  On success the
864  * the value of EBX will be set to BDOOR_MAGIC and EAX will be set to
865  * the requested capability.  If the command is not supported then EBX
866  * will be left unchanged and EAX will be set to -1.  Because it is
867  * possible that -1 is the value of the requested cap the correct way
868  * to check if the command was successful is to check if EBX was changed
869  * to BDOOR_MAGIC making sure to initialize the register to something
870  * else first.
871  */
872 
873 typedef enum {
874    SVGABackdoorCapDeviceCaps = 0,
875    SVGABackdoorCapFifoCaps = 1,
876    SVGABackdoorCap3dHWVersion = 2,
877    SVGABackdoorCapDeviceCaps2 = 3,
878    SVGABackdoorCapMax = 4,
879 } SVGABackdoorCapType;
880 
881 
882 /*
883  * FIFO register indices.
884  *
885  * The FIFO is a chunk of device memory mapped into guest physmem.  It
886  * is always treated as 32-bit words.
887  *
888  * The guest driver gets to decide how to partition it between
889  * - FIFO registers (there are always at least 4, specifying where the
890  *   following data area is and how much data it contains; there may be
891  *   more registers following these, depending on the FIFO protocol
892  *   version in use)
893  * - FIFO data, written by the guest and slurped out by the VMX.
894  * These indices are 32-bit word offsets into the FIFO.
895  */
896 
897 enum {
898    /*
899     * Block 1 (basic registers): The originally defined FIFO registers.
900     * These exist and are valid for all versions of the FIFO protocol.
901     */
902 
903    SVGA_FIFO_MIN = 0,
904    SVGA_FIFO_MAX,       /* The distance from MIN to MAX must be at least 10K */
905    SVGA_FIFO_NEXT_CMD,
906    SVGA_FIFO_STOP,
907 
908    /*
909     * Block 2 (extended registers): Mandatory registers for the extended
910     * FIFO.  These exist if the SVGA caps register includes
911     * SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their
912     * associated capability bit is enabled.
913     *
914     * Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied
915     * support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE.
916     * This means that the guest has to test individually (in most cases
917     * using FIFO caps) for the presence of registers after this; the VMX
918     * can define "extended FIFO" to mean whatever it wants, and currently
919     * won't enable it unless there's room for that set and much more.
920     */
921 
922    SVGA_FIFO_CAPABILITIES = 4,
923    SVGA_FIFO_FLAGS,
924    /* Valid with SVGA_FIFO_CAP_FENCE: */
925    SVGA_FIFO_FENCE,
926 
927    /*
928     * Block 3a (optional extended registers): Additional registers for the
929     * extended FIFO, whose presence isn't actually implied by
930     * SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to
931     * leave room for them.
932     *
933     * These in block 3a, the VMX currently considers mandatory for the
934     * extended FIFO.
935     */
936 
937    /* Valid if exists (i.e. if extended FIFO enabled): */
938    SVGA_FIFO_3D_HWVERSION,       /* See SVGA3dHardwareVersion in svga3d_reg.h */
939    /* Valid with SVGA_FIFO_CAP_PITCHLOCK: */
940    SVGA_FIFO_PITCHLOCK,
941 
942    /* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */
943    SVGA_FIFO_CURSOR_ON,          /* Cursor bypass 3 show/hide register */
944    SVGA_FIFO_CURSOR_X,           /* Cursor bypass 3 x register */
945    SVGA_FIFO_CURSOR_Y,           /* Cursor bypass 3 y register */
946    SVGA_FIFO_CURSOR_COUNT,       /* Incremented when any of the other 3 change */
947    SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */
948 
949    /* Valid with SVGA_FIFO_CAP_RESERVE: */
950    SVGA_FIFO_RESERVED,           /* Bytes past NEXT_CMD with real contents */
951 
952    /*
953     * Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2:
954     *
955     * By default this is SVGA_ID_INVALID, to indicate that the cursor
956     * coordinates are specified relative to the virtual root. If this
957     * is set to a specific screen ID, cursor position is reinterpreted
958     * as a signed offset relative to that screen's origin.
959     */
960    SVGA_FIFO_CURSOR_SCREEN_ID,
961 
962    /*
963     * Valid with SVGA_FIFO_CAP_DEAD
964     *
965     * An arbitrary value written by the host, drivers should not use it.
966     */
967    SVGA_FIFO_DEAD,
968 
969    /*
970     * Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED:
971     *
972     * Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h)
973     * on platforms that can enforce graphics resource limits.
974     */
975    SVGA_FIFO_3D_HWVERSION_REVISED,
976 
977    /*
978     * XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
979     * registers, but this must be done carefully and with judicious use of
980     * capability bits, since comparisons based on SVGA_FIFO_MIN aren't
981     * enough to tell you whether the register exists: we've shipped drivers
982     * and products that used SVGA_FIFO_3D_CAPS but didn't know about some of
983     * the earlier ones.  The actual order of introduction was:
984     * - PITCHLOCK
985     * - 3D_CAPS
986     * - CURSOR_* (cursor bypass 3)
987     * - RESERVED
988     * So, code that wants to know whether it can use any of the
989     * aforementioned registers, or anything else added after PITCHLOCK and
990     * before 3D_CAPS, needs to reason about something other than
991     * SVGA_FIFO_MIN.
992     */
993 
994    /*
995     * 3D caps block space; valid with 3D hardware version >=
996     * SVGA3D_HWVERSION_WS6_B1.
997     */
998    SVGA_FIFO_3D_CAPS      = 32,
999    SVGA_FIFO_3D_CAPS_LAST = 32 + 255,
1000 
1001    /*
1002     * End of VMX's current definition of "extended-FIFO registers".
1003     * Registers before here are always enabled/disabled as a block; either
1004     * the extended FIFO is enabled and includes all preceding registers, or
1005     * it's disabled entirely.
1006     *
1007     * Block 3b (truly optional extended registers): Additional registers for
1008     * the extended FIFO, which the VMX already knows how to enable and
1009     * disable with correct granularity.
1010     *
1011     * Registers after here exist if and only if the guest SVGA driver
1012     * sets SVGA_FIFO_MIN high enough to leave room for them.
1013     */
1014 
1015    /* Valid if register exists: */
1016    SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */
1017    SVGA_FIFO_FENCE_GOAL,         /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
1018    SVGA_FIFO_BUSY,               /* See "FIFO Synchronization Registers" */
1019 
1020    /*
1021     * Always keep this last.  This defines the maximum number of
1022     * registers we know about.  At power-on, this value is placed in
1023     * the SVGA_REG_MEM_REGS register, and we expect the guest driver
1024     * to allocate this much space in FIFO memory for registers.
1025     */
1026     SVGA_FIFO_NUM_REGS
1027 };
1028 
1029 
1030 /*
1031  * Definition of registers included in extended FIFO support.
1032  *
1033  * The guest SVGA driver gets to allocate the FIFO between registers
1034  * and data.  It must always allocate at least 4 registers, but old
1035  * drivers stopped there.
1036  *
1037  * The VMX will enable extended FIFO support if and only if the guest
1038  * left enough room for all registers defined as part of the mandatory
1039  * set for the extended FIFO.
1040  *
1041  * Note that the guest drivers typically allocate the FIFO only at
1042  * initialization time, not at mode switches, so it's likely that the
1043  * number of FIFO registers won't change without a reboot.
1044  *
1045  * All registers less than this value are guaranteed to be present if
1046  * svgaUser->fifo.extended is set. Any later registers must be tested
1047  * individually for compatibility at each use (in the VMX).
1048  *
1049  * This value is used only by the VMX, so it can change without
1050  * affecting driver compatibility; keep it that way?
1051  */
1052 #define SVGA_FIFO_EXTENDED_MANDATORY_REGS  (SVGA_FIFO_3D_CAPS_LAST + 1)
1053 
1054 
1055 /*
1056  * FIFO Synchronization Registers
1057  *
1058  *  This explains the relationship between the various FIFO
1059  *  sync-related registers in IOSpace and in FIFO space.
1060  *
1061  *  SVGA_REG_SYNC --
1062  *
1063  *       The SYNC register can be used in two different ways by the guest:
1064  *
1065  *         1. If the guest wishes to fully sync (drain) the FIFO,
1066  *            it will write once to SYNC then poll on the BUSY
1067  *            register. The FIFO is sync'ed once BUSY is zero.
1068  *
1069  *         2. If the guest wants to asynchronously wake up the host,
1070  *            it will write once to SYNC without polling on BUSY.
1071  *            Ideally it will do this after some new commands have
1072  *            been placed in the FIFO, and after reading a zero
1073  *            from SVGA_FIFO_BUSY.
1074  *
1075  *       (1) is the original behaviour that SYNC was designed to
1076  *       support.  Originally, a write to SYNC would implicitly
1077  *       trigger a read from BUSY. This causes us to synchronously
1078  *       process the FIFO.
1079  *
1080  *       This behaviour has since been changed so that writing SYNC
1081  *       will *not* implicitly cause a read from BUSY. Instead, it
1082  *       makes a channel call which asynchronously wakes up the MKS
1083  *       thread.
1084  *
1085  *       New guests can use this new behaviour to implement (2)
1086  *       efficiently. This lets guests get the host's attention
1087  *       without waiting for the MKS to poll, which gives us much
1088  *       better CPU utilization on SMP hosts and on UP hosts while
1089  *       we're blocked on the host GPU.
1090  *
1091  *       Old guests shouldn't notice the behaviour change. SYNC was
1092  *       never guaranteed to process the entire FIFO, since it was
1093  *       bounded to a particular number of CPU cycles. Old guests will
1094  *       still loop on the BUSY register until the FIFO is empty.
1095  *
1096  *       Writing to SYNC currently has the following side-effects:
1097  *
1098  *         - Sets SVGA_REG_BUSY to TRUE (in the monitor)
1099  *         - Asynchronously wakes up the MKS thread for FIFO processing
1100  *         - The value written to SYNC is recorded as a "reason", for
1101  *           stats purposes.
1102  *
1103  *       If SVGA_FIFO_BUSY is available, drivers are advised to only
1104  *       write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set
1105  *       SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will
1106  *       eventually set SVGA_FIFO_BUSY on its own, but this approach
1107  *       lets the driver avoid sending multiple asynchronous wakeup
1108  *       messages to the MKS thread.
1109  *
1110  *  SVGA_REG_BUSY --
1111  *
1112  *       This register is set to TRUE when SVGA_REG_SYNC is written,
1113  *       and it reads as FALSE when the FIFO has been completely
1114  *       drained.
1115  *
1116  *       Every read from this register causes us to synchronously
1117  *       process FIFO commands. There is no guarantee as to how many
1118  *       commands each read will process.
1119  *
1120  *       CPU time spent processing FIFO commands will be billed to
1121  *       the guest.
1122  *
1123  *       New drivers should avoid using this register unless they
1124  *       need to guarantee that the FIFO is completely drained. It
1125  *       is overkill for performing a sync-to-fence. Older drivers
1126  *       will use this register for any type of synchronization.
1127  *
1128  *  SVGA_FIFO_BUSY --
1129  *
1130  *       This register is a fast way for the guest driver to check
1131  *       whether the FIFO is already being processed. It reads and
1132  *       writes at normal RAM speeds, with no monitor intervention.
1133  *
1134  *       If this register reads as TRUE, the host is guaranteeing that
1135  *       any new commands written into the FIFO will be noticed before
1136  *       the MKS goes back to sleep.
1137  *
1138  *       If this register reads as FALSE, no such guarantee can be
1139  *       made.
1140  *
1141  *       The guest should use this register to quickly determine
1142  *       whether or not it needs to wake up the host. If the guest
1143  *       just wrote a command or group of commands that it would like
1144  *       the host to begin processing, it should:
1145  *
1146  *         1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further
1147  *            action is necessary.
1148  *
1149  *         2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest
1150  *            code that we've already sent a SYNC to the host and we
1151  *            don't need to send a duplicate.
1152  *
1153  *         3. Write a reason to SVGA_REG_SYNC. This will send an
1154  *            asynchronous wakeup to the MKS thread.
1155  */
1156 
1157 
1158 /*
1159  * FIFO Capabilities
1160  *
1161  *      Fence -- Fence register and command are supported
1162  *      Accel Front -- Front buffer only commands are supported
1163  *      Pitch Lock -- Pitch lock register is supported
1164  *      Video -- SVGA Video overlay units are supported
1165  *      Escape -- Escape command is supported
1166  *
1167  * XXX: Add longer descriptions for each capability, including a list
1168  *      of the new features that each capability provides.
1169  *
1170  * SVGA_FIFO_CAP_SCREEN_OBJECT --
1171  *
1172  *    Provides dynamic multi-screen rendering, for improved Unity and
1173  *    multi-monitor modes. With Screen Object, the guest can
1174  *    dynamically create and destroy 'screens', which can represent
1175  *    Unity windows or virtual monitors. Screen Object also provides
1176  *    strong guarantees that DMA operations happen only when
1177  *    guest-initiated. Screen Object deprecates the BAR1 guest
1178  *    framebuffer (GFB) and all commands that work only with the GFB.
1179  *
1180  *    New registers:
1181  *       FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID
1182  *
1183  *    New 2D commands:
1184  *       DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN,
1185  *       BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY
1186  *
1187  *    New 3D commands:
1188  *       BLIT_SURFACE_TO_SCREEN
1189  *
1190  *    New guarantees:
1191  *
1192  *       - The host will not read or write guest memory, including the GFB,
1193  *         except when explicitly initiated by a DMA command.
1194  *
1195  *       - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK,
1196  *         is guaranteed to complete before any subsequent FENCEs.
1197  *
1198  *       - All legacy commands which affect a Screen (UPDATE, PRESENT,
1199  *         PRESENT_READBACK) as well as new Screen blit commands will
1200  *         all behave consistently as blits, and memory will be read
1201  *         or written in FIFO order.
1202  *
1203  *         For example, if you PRESENT from one SVGA3D surface to multiple
1204  *         places on the screen, the data copied will always be from the
1205  *         SVGA3D surface at the time the PRESENT was issued in the FIFO.
1206  *         This was not necessarily true on devices without Screen Object.
1207  *
1208  *         This means that on devices that support Screen Object, the
1209  *         PRESENT_READBACK command should not be necessary unless you
1210  *         actually want to read back the results of 3D rendering into
1211  *         system memory. (And for that, the BLIT_SCREEN_TO_GMRFB
1212  *         command provides a strict superset of functionality.)
1213  *
1214  *       - When a screen is resized, either using Screen Object commands or
1215  *         legacy multimon registers, its contents are preserved.
1216  *
1217  * SVGA_FIFO_CAP_GMR2 --
1218  *
1219  *    Provides new commands to define and remap guest memory regions (GMR).
1220  *
1221  *    New 2D commands:
1222  *       DEFINE_GMR2, REMAP_GMR2.
1223  *
1224  * SVGA_FIFO_CAP_3D_HWVERSION_REVISED --
1225  *
1226  *    Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists.
1227  *    This register may replace SVGA_FIFO_3D_HWVERSION on platforms
1228  *    that enforce graphics resource limits.  This allows the platform
1229  *    to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest
1230  *    drivers that do not limit their resources.
1231  *
1232  *    Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators
1233  *    are codependent (and thus we use a single capability bit).
1234  *
1235  * SVGA_FIFO_CAP_SCREEN_OBJECT_2 --
1236  *
1237  *    Modifies the DEFINE_SCREEN command to include a guest provided
1238  *    backing store in GMR memory and the bytesPerLine for the backing
1239  *    store.  This capability requires the use of a backing store when
1240  *    creating screen objects.  However if SVGA_FIFO_CAP_SCREEN_OBJECT
1241  *    is present then backing stores are optional.
1242  *
1243  * SVGA_FIFO_CAP_DEAD --
1244  *
1245  *    Drivers should not use this cap bit.  This cap bit can not be
1246  *    reused since some hosts already expose it.
1247  */
1248 
1249 #define SVGA_FIFO_CAP_NONE                  0
1250 #define SVGA_FIFO_CAP_FENCE             (1<<0)
1251 #define SVGA_FIFO_CAP_ACCELFRONT        (1<<1)
1252 #define SVGA_FIFO_CAP_PITCHLOCK         (1<<2)
1253 #define SVGA_FIFO_CAP_VIDEO             (1<<3)
1254 #define SVGA_FIFO_CAP_CURSOR_BYPASS_3   (1<<4)
1255 #define SVGA_FIFO_CAP_ESCAPE            (1<<5)
1256 #define SVGA_FIFO_CAP_RESERVE           (1<<6)
1257 #define SVGA_FIFO_CAP_SCREEN_OBJECT     (1<<7)
1258 #define SVGA_FIFO_CAP_GMR2              (1<<8)
1259 #define SVGA_FIFO_CAP_3D_HWVERSION_REVISED  SVGA_FIFO_CAP_GMR2
1260 #define SVGA_FIFO_CAP_SCREEN_OBJECT_2   (1<<9)
1261 #define SVGA_FIFO_CAP_DEAD              (1<<10)
1262 
1263 
1264 /*
1265  * FIFO Flags
1266  *
1267  *      Accel Front -- Driver should use front buffer only commands
1268  */
1269 
1270 #define SVGA_FIFO_FLAG_NONE                 0
1271 #define SVGA_FIFO_FLAG_ACCELFRONT       (1<<0)
1272 #define SVGA_FIFO_FLAG_RESERVED        (1<<31) /* Internal use only */
1273 
1274 /*
1275  * FIFO reservation sentinel value
1276  */
1277 
1278 #define SVGA_FIFO_RESERVED_UNKNOWN      0xffffffff
1279 
1280 
1281 /*
1282  * Video overlay support
1283  */
1284 
1285 #define SVGA_NUM_OVERLAY_UNITS 32
1286 
1287 
1288 /*
1289  * Video capabilities that the guest is currently using
1290  */
1291 
1292 #define SVGA_VIDEO_FLAG_COLORKEY        0x0001
1293 
1294 
1295 /*
1296  * Offsets for the video overlay registers
1297  */
1298 
1299 enum {
1300    SVGA_VIDEO_ENABLED = 0,
1301    SVGA_VIDEO_FLAGS,
1302    SVGA_VIDEO_DATA_OFFSET,
1303    SVGA_VIDEO_FORMAT,
1304    SVGA_VIDEO_COLORKEY,
1305    SVGA_VIDEO_SIZE,          /* Deprecated */
1306    SVGA_VIDEO_WIDTH,
1307    SVGA_VIDEO_HEIGHT,
1308    SVGA_VIDEO_SRC_X,
1309    SVGA_VIDEO_SRC_Y,
1310    SVGA_VIDEO_SRC_WIDTH,
1311    SVGA_VIDEO_SRC_HEIGHT,
1312    SVGA_VIDEO_DST_X,         /* Signed int32 */
1313    SVGA_VIDEO_DST_Y,         /* Signed int32 */
1314    SVGA_VIDEO_DST_WIDTH,
1315    SVGA_VIDEO_DST_HEIGHT,
1316    SVGA_VIDEO_PITCH_1,
1317    SVGA_VIDEO_PITCH_2,
1318    SVGA_VIDEO_PITCH_3,
1319    SVGA_VIDEO_DATA_GMRID,    /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */
1320    SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords */
1321                              /* (SVGA_ID_INVALID) */
1322    SVGA_VIDEO_NUM_REGS
1323 };
1324 
1325 
1326 /*
1327  * SVGA Overlay Units
1328  *
1329  *      width and height relate to the entire source video frame.
1330  *      srcX, srcY, srcWidth and srcHeight represent subset of the source
1331  *      video frame to be displayed.
1332  */
1333 
1334 typedef
1335 #include "vmware_pack_begin.h"
1336 struct SVGAOverlayUnit {
1337    uint32 enabled;
1338    uint32 flags;
1339    uint32 dataOffset;
1340    uint32 format;
1341    uint32 colorKey;
1342    uint32 size;
1343    uint32 width;
1344    uint32 height;
1345    uint32 srcX;
1346    uint32 srcY;
1347    uint32 srcWidth;
1348    uint32 srcHeight;
1349    int32  dstX;
1350    int32  dstY;
1351    uint32 dstWidth;
1352    uint32 dstHeight;
1353    uint32 pitches[3];
1354    uint32 dataGMRId;
1355    uint32 dstScreenId;
1356 }
1357 #include "vmware_pack_end.h"
1358 SVGAOverlayUnit;
1359 
1360 
1361 /*
1362  * Guest display topology
1363  *
1364  * XXX: This structure is not part of the SVGA device's interface, and
1365  * doesn't really belong here.
1366  */
1367 #define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
1368 
1369 typedef struct SVGADisplayTopology {
1370    uint16 displayId;
1371    uint16 isPrimary;
1372    uint32 width;
1373    uint32 height;
1374    uint32 positionX;
1375    uint32 positionY;
1376 } SVGADisplayTopology;
1377 
1378 
1379 /*
1380  * SVGAScreenObject --
1381  *
1382  *    This is a new way to represent a guest's multi-monitor screen or
1383  *    Unity window. Screen objects are only supported if the
1384  *    SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set.
1385  *
1386  *    If Screen Objects are supported, they can be used to fully
1387  *    replace the functionality provided by the framebuffer registers
1388  *    (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY.
1389  *
1390  *    The screen object is a struct with guaranteed binary
1391  *    compatibility. New flags can be added, and the struct may grow,
1392  *    but existing fields must retain their meaning.
1393  *
1394  *    Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of
1395  *    a SVGAGuestPtr that is used to back the screen contents.  This
1396  *    memory must come from the GFB.  The guest is not allowed to
1397  *    access the memory and doing so will have undefined results.  The
1398  *    backing store is required to be page aligned and the size is
1399  *    padded to the next page boundry.  The number of pages is:
1400  *       (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE
1401  *
1402  *    The pitch in the backingStore is required to be at least large
1403  *    enough to hold a 32bbp scanline.  It is recommended that the
1404  *    driver pad bytesPerLine for a potential performance win.
1405  *
1406  *    The cloneCount field is treated as a hint from the guest that
1407  *    the user wants this display to be cloned, countCount times.  A
1408  *    value of zero means no cloning should happen.
1409  */
1410 
1411 #define SVGA_SCREEN_MUST_BE_SET     (1 << 0)
1412 #define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */
1413 #define SVGA_SCREEN_IS_PRIMARY      (1 << 1)
1414 #define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2)
1415 
1416 /*
1417  * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2.  When the screen is
1418  * deactivated the base layer is defined to lose all contents and
1419  * become black.  When a screen is deactivated the backing store is
1420  * optional.  When set backingPtr and bytesPerLine will be ignored.
1421  */
1422 #define SVGA_SCREEN_DEACTIVATE  (1 << 3)
1423 
1424 /*
1425  * Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2.  When this flag is set
1426  * the screen contents will be outputted as all black to the user
1427  * though the base layer contents is preserved.  The screen base layer
1428  * can still be read and written to like normal though the no visible
1429  * effect will be seen by the user.  When the flag is changed the
1430  * screen will be blanked or redrawn to the current contents as needed
1431  * without any extra commands from the driver.  This flag only has an
1432  * effect when the screen is not deactivated.
1433  */
1434 #define SVGA_SCREEN_BLANKING (1 << 4)
1435 
1436 typedef
1437 #include "vmware_pack_begin.h"
1438 struct {
1439    uint32 structSize;   /* sizeof(SVGAScreenObject) */
1440    uint32 id;
1441    uint32 flags;
1442    struct {
1443       uint32 width;
1444       uint32 height;
1445    } size;
1446    struct {
1447       int32 x;
1448       int32 y;
1449    } root;
1450 
1451    /*
1452     * Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional
1453     * with SVGA_FIFO_CAP_SCREEN_OBJECT.
1454     */
1455    SVGAGuestImage backingStore;
1456 
1457    /*
1458     * The cloneCount field is treated as a hint from the guest that
1459     * the user wants this display to be cloned, cloneCount times.
1460     *
1461     * A value of zero means no cloning should happen.
1462     */
1463    uint32 cloneCount;
1464 }
1465 #include "vmware_pack_end.h"
1466 SVGAScreenObject;
1467 
1468 
1469 /*
1470  *  Commands in the command FIFO:
1471  *
1472  *  Command IDs defined below are used for the traditional 2D FIFO
1473  *  communication (not all commands are available for all versions of the
1474  *  SVGA FIFO protocol).
1475  *
1476  *  Note the holes in the command ID numbers: These commands have been
1477  *  deprecated, and the old IDs must not be reused.
1478  *
1479  *  Command IDs from 1000 to 2999 are reserved for use by the SVGA3D
1480  *  protocol.
1481  *
1482  *  Each command's parameters are described by the comments and
1483  *  structs below.
1484  */
1485 
1486 typedef enum {
1487    SVGA_CMD_INVALID_CMD           = 0,
1488    SVGA_CMD_UPDATE                = 1,
1489    SVGA_CMD_RECT_COPY             = 3,
1490    SVGA_CMD_RECT_ROP_COPY         = 14,
1491    SVGA_CMD_DEFINE_CURSOR         = 19,
1492    SVGA_CMD_DEFINE_ALPHA_CURSOR   = 22,
1493    SVGA_CMD_UPDATE_VERBOSE        = 25,
1494    SVGA_CMD_FRONT_ROP_FILL        = 29,
1495    SVGA_CMD_FENCE                 = 30,
1496    SVGA_CMD_ESCAPE                = 33,
1497    SVGA_CMD_DEFINE_SCREEN         = 34,
1498    SVGA_CMD_DESTROY_SCREEN        = 35,
1499    SVGA_CMD_DEFINE_GMRFB          = 36,
1500    SVGA_CMD_BLIT_GMRFB_TO_SCREEN  = 37,
1501    SVGA_CMD_BLIT_SCREEN_TO_GMRFB  = 38,
1502    SVGA_CMD_ANNOTATION_FILL       = 39,
1503    SVGA_CMD_ANNOTATION_COPY       = 40,
1504    SVGA_CMD_DEFINE_GMR2           = 41,
1505    SVGA_CMD_REMAP_GMR2            = 42,
1506    SVGA_CMD_DEAD                  = 43,
1507    SVGA_CMD_DEAD_2                = 44,
1508    SVGA_CMD_NOP                   = 45,
1509    SVGA_CMD_NOP_ERROR             = 46,
1510    SVGA_CMD_MAX
1511 } SVGAFifoCmdId;
1512 
1513 #define SVGA_CMD_MAX_DATASIZE       (256 * 1024)
1514 #define SVGA_CMD_MAX_ARGS           64
1515 
1516 
1517 /*
1518  * SVGA_CMD_UPDATE --
1519  *
1520  *    This is a DMA transfer which copies from the Guest Framebuffer
1521  *    (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which
1522  *    intersect with the provided virtual rectangle.
1523  *
1524  *    This command does not support using arbitrary guest memory as a
1525  *    data source- it only works with the pre-defined GFB memory.
1526  *    This command also does not support signed virtual coordinates.
1527  *    If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with
1528  *    negative root x/y coordinates, the negative portion of those
1529  *    screens will not be reachable by this command.
1530  *
1531  *    This command is not necessary when using framebuffer
1532  *    traces. Traces are automatically enabled if the SVGA FIFO is
1533  *    disabled, and you may explicitly enable/disable traces using
1534  *    SVGA_REG_TRACES. With traces enabled, any write to the GFB will
1535  *    automatically act as if a subsequent SVGA_CMD_UPDATE was issued.
1536  *
1537  *    Traces and SVGA_CMD_UPDATE are the only supported ways to render
1538  *    pseudocolor screen updates. The newer Screen Object commands
1539  *    only support true color formats.
1540  *
1541  * Availability:
1542  *    Always available.
1543  */
1544 
1545 typedef
1546 #include "vmware_pack_begin.h"
1547 struct {
1548    uint32 x;
1549    uint32 y;
1550    uint32 width;
1551    uint32 height;
1552 }
1553 #include "vmware_pack_end.h"
1554 SVGAFifoCmdUpdate;
1555 
1556 
1557 /*
1558  * SVGA_CMD_RECT_COPY --
1559  *
1560  *    Perform a rectangular DMA transfer from one area of the GFB to
1561  *    another, and copy the result to any screens which intersect it.
1562  *
1563  * Availability:
1564  *    SVGA_CAP_RECT_COPY
1565  */
1566 
1567 typedef
1568 #include "vmware_pack_begin.h"
1569 struct {
1570    uint32 srcX;
1571    uint32 srcY;
1572    uint32 destX;
1573    uint32 destY;
1574    uint32 width;
1575    uint32 height;
1576 }
1577 #include "vmware_pack_end.h"
1578 SVGAFifoCmdRectCopy;
1579 
1580 
1581 /*
1582  * SVGA_CMD_RECT_ROP_COPY --
1583  *
1584  *    Perform a rectangular DMA transfer from one area of the GFB to
1585  *    another, and copy the result to any screens which intersect it.
1586  *    The value of ROP may only be SVGA_ROP_COPY, and this command is
1587  *    only supported for backwards compatibility reasons.
1588  *
1589  * Availability:
1590  *    SVGA_CAP_RECT_COPY
1591  */
1592 
1593 typedef
1594 #include "vmware_pack_begin.h"
1595 struct {
1596    uint32 srcX;
1597    uint32 srcY;
1598    uint32 destX;
1599    uint32 destY;
1600    uint32 width;
1601    uint32 height;
1602    uint32 rop;
1603 }
1604 #include "vmware_pack_end.h"
1605 SVGAFifoCmdRectRopCopy;
1606 
1607 
1608 /*
1609  * SVGA_CMD_DEFINE_CURSOR --
1610  *
1611  *    Provide a new cursor image, as an AND/XOR mask.
1612  *
1613  *    The recommended way to position the cursor overlay is by using
1614  *    the SVGA_FIFO_CURSOR_* registers, supported by the
1615  *    SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1616  *
1617  * Availability:
1618  *    SVGA_CAP_CURSOR
1619  */
1620 
1621 typedef
1622 #include "vmware_pack_begin.h"
1623 struct {
1624    uint32 id;             /* Reserved, must be zero. */
1625    uint32 hotspotX;
1626    uint32 hotspotY;
1627    uint32 width;
1628    uint32 height;
1629    uint32 andMaskDepth;   /* Value must be 1 or equal to BITS_PER_PIXEL */
1630    uint32 xorMaskDepth;   /* Value must be 1 or equal to BITS_PER_PIXEL */
1631    /*
1632     * Followed by scanline data for AND mask, then XOR mask.
1633     * Each scanline is padded to a 32-bit boundary.
1634    */
1635 }
1636 #include "vmware_pack_end.h"
1637 SVGAFifoCmdDefineCursor;
1638 
1639 
1640 /*
1641  * SVGA_CMD_DEFINE_ALPHA_CURSOR --
1642  *
1643  *    Provide a new cursor image, in 32-bit BGRA format.
1644  *
1645  *    The recommended way to position the cursor overlay is by using
1646  *    the SVGA_FIFO_CURSOR_* registers, supported by the
1647  *    SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1648  *
1649  * Availability:
1650  *    SVGA_CAP_ALPHA_CURSOR
1651  */
1652 
1653 typedef
1654 #include "vmware_pack_begin.h"
1655 struct {
1656    uint32 id;             /* Reserved, must be zero. */
1657    uint32 hotspotX;
1658    uint32 hotspotY;
1659    uint32 width;
1660    uint32 height;
1661    /* Followed by scanline data */
1662 }
1663 #include "vmware_pack_end.h"
1664 SVGAFifoCmdDefineAlphaCursor;
1665 
1666 
1667 /*
1668  * SVGA_CMD_UPDATE_VERBOSE --
1669  *
1670  *    Just like SVGA_CMD_UPDATE, but also provide a per-rectangle
1671  *    'reason' value, an opaque cookie which is used by internal
1672  *    debugging tools. Third party drivers should not use this
1673  *    command.
1674  *
1675  * Availability:
1676  *    SVGA_CAP_EXTENDED_FIFO
1677  */
1678 
1679 typedef
1680 #include "vmware_pack_begin.h"
1681 struct {
1682    uint32 x;
1683    uint32 y;
1684    uint32 width;
1685    uint32 height;
1686    uint32 reason;
1687 }
1688 #include "vmware_pack_end.h"
1689 SVGAFifoCmdUpdateVerbose;
1690 
1691 
1692 /*
1693  * SVGA_CMD_FRONT_ROP_FILL --
1694  *
1695  *    This is a hint which tells the SVGA device that the driver has
1696  *    just filled a rectangular region of the GFB with a solid
1697  *    color. Instead of reading these pixels from the GFB, the device
1698  *    can assume that they all equal 'color'. This is primarily used
1699  *    for remote desktop protocols.
1700  *
1701  * Availability:
1702  *    SVGA_FIFO_CAP_ACCELFRONT
1703  */
1704 
1705 #define  SVGA_ROP_COPY                    0x03
1706 
1707 typedef
1708 #include "vmware_pack_begin.h"
1709 struct {
1710    uint32 color;     /* In the same format as the GFB */
1711    uint32 x;
1712    uint32 y;
1713    uint32 width;
1714    uint32 height;
1715    uint32 rop;       /* Must be SVGA_ROP_COPY */
1716 }
1717 #include "vmware_pack_end.h"
1718 SVGAFifoCmdFrontRopFill;
1719 
1720 
1721 /*
1722  * SVGA_CMD_FENCE --
1723  *
1724  *    Insert a synchronization fence.  When the SVGA device reaches
1725  *    this command, it will copy the 'fence' value into the
1726  *    SVGA_FIFO_FENCE register. It will also compare the fence against
1727  *    SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the
1728  *    SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will
1729  *    raise this interrupt.
1730  *
1731  * Availability:
1732  *    SVGA_FIFO_FENCE for this command,
1733  *    SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL.
1734  */
1735 
1736 typedef
1737 #include "vmware_pack_begin.h"
1738 struct {
1739    uint32 fence;
1740 }
1741 #include "vmware_pack_end.h"
1742 SVGAFifoCmdFence;
1743 
1744 
1745 /*
1746  * SVGA_CMD_ESCAPE --
1747  *
1748  *    Send an extended or vendor-specific variable length command.
1749  *    This is used for video overlay, third party plugins, and
1750  *    internal debugging tools. See svga_escape.h
1751  *
1752  * Availability:
1753  *    SVGA_FIFO_CAP_ESCAPE
1754  */
1755 
1756 typedef
1757 #include "vmware_pack_begin.h"
1758 struct {
1759    uint32 nsid;
1760    uint32 size;
1761    /* followed by 'size' bytes of data */
1762 }
1763 #include "vmware_pack_end.h"
1764 SVGAFifoCmdEscape;
1765 
1766 
1767 /*
1768  * SVGA_CMD_DEFINE_SCREEN --
1769  *
1770  *    Define or redefine an SVGAScreenObject. See the description of
1771  *    SVGAScreenObject above.  The video driver is responsible for
1772  *    generating new screen IDs. They should be small positive
1773  *    integers. The virtual device will have an implementation
1774  *    specific upper limit on the number of screen IDs
1775  *    supported. Drivers are responsible for recycling IDs. The first
1776  *    valid ID is zero.
1777  *
1778  *    - Interaction with other registers:
1779  *
1780  *    For backwards compatibility, when the GFB mode registers (WIDTH,
1781  *    HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1782  *    deletes all screens other than screen #0, and redefines screen
1783  *    #0 according to the specified mode. Drivers that use
1784  *    SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0.
1785  *
1786  *    If you use screen objects, do not use the legacy multi-mon
1787  *    registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*).
1788  *
1789  * Availability:
1790  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1791  */
1792 
1793 typedef
1794 #include "vmware_pack_begin.h"
1795 struct {
1796    SVGAScreenObject screen;   /* Variable-length according to version */
1797 }
1798 #include "vmware_pack_end.h"
1799 SVGAFifoCmdDefineScreen;
1800 
1801 
1802 /*
1803  * SVGA_CMD_DESTROY_SCREEN --
1804  *
1805  *    Destroy an SVGAScreenObject. Its ID is immediately available for
1806  *    re-use.
1807  *
1808  * Availability:
1809  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1810  */
1811 
1812 typedef
1813 #include "vmware_pack_begin.h"
1814 struct {
1815    uint32 screenId;
1816 }
1817 #include "vmware_pack_end.h"
1818 SVGAFifoCmdDestroyScreen;
1819 
1820 
1821 /*
1822  * SVGA_CMD_DEFINE_GMRFB --
1823  *
1824  *    This command sets a piece of SVGA device state called the
1825  *    Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a
1826  *    piece of light-weight state which identifies the location and
1827  *    format of an image in guest memory or in BAR1. The GMRFB has
1828  *    an arbitrary size, and it doesn't need to match the geometry
1829  *    of the GFB or any screen object.
1830  *
1831  *    The GMRFB can be redefined as often as you like. You could
1832  *    always use the same GMRFB, you could redefine it before
1833  *    rendering from a different guest screen, or you could even
1834  *    redefine it before every blit.
1835  *
1836  *    There are multiple ways to use this command. The simplest way is
1837  *    to use it to move the framebuffer either to elsewhere in the GFB
1838  *    (BAR1) memory region, or to a user-defined GMR. This lets a
1839  *    driver use a framebuffer allocated entirely out of normal system
1840  *    memory, which we encourage.
1841  *
1842  *    Another way to use this command is to set up a ring buffer of
1843  *    updates in GFB memory. If a driver wants to ensure that no
1844  *    frames are skipped by the SVGA device, it is important that the
1845  *    driver not modify the source data for a blit until the device is
1846  *    done processing the command. One efficient way to accomplish
1847  *    this is to use a ring of small DMA buffers. Each buffer is used
1848  *    for one blit, then we move on to the next buffer in the
1849  *    ring. The FENCE mechanism is used to protect each buffer from
1850  *    re-use until the device is finished with that buffer's
1851  *    corresponding blit.
1852  *
1853  *    This command does not affect the meaning of SVGA_CMD_UPDATE.
1854  *    UPDATEs always occur from the legacy GFB memory area. This
1855  *    command has no support for pseudocolor GMRFBs. Currently only
1856  *    true-color 15, 16, and 24-bit depths are supported. Future
1857  *    devices may expose capabilities for additional framebuffer
1858  *    formats.
1859  *
1860  *    The default GMRFB value is undefined. Drivers must always send
1861  *    this command at least once before performing any blit from the
1862  *    GMRFB.
1863  *
1864  * Availability:
1865  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1866  */
1867 
1868 typedef
1869 #include "vmware_pack_begin.h"
1870 struct {
1871    SVGAGuestPtr        ptr;
1872    uint32              bytesPerLine;
1873    SVGAGMRImageFormat  format;
1874 }
1875 #include "vmware_pack_end.h"
1876 SVGAFifoCmdDefineGMRFB;
1877 
1878 
1879 /*
1880  * SVGA_CMD_BLIT_GMRFB_TO_SCREEN --
1881  *
1882  *    This is a guest-to-host blit. It performs a DMA operation to
1883  *    copy a rectangular region of pixels from the current GMRFB to
1884  *    a ScreenObject.
1885  *
1886  *    The destination coordinate may be specified relative to a
1887  *    screen's origin.  The provided screen ID must be valid.
1888  *
1889  *    The SVGA device is guaranteed to finish reading from the GMRFB
1890  *    by the time any subsequent FENCE commands are reached.
1891  *
1892  *    This command consumes an annotation. See the
1893  *    SVGA_CMD_ANNOTATION_* commands for details.
1894  *
1895  * Availability:
1896  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1897  */
1898 
1899 typedef
1900 #include "vmware_pack_begin.h"
1901 struct {
1902    SVGASignedPoint  srcOrigin;
1903    SVGASignedRect   destRect;
1904    uint32           destScreenId;
1905 }
1906 #include "vmware_pack_end.h"
1907 SVGAFifoCmdBlitGMRFBToScreen;
1908 
1909 
1910 /*
1911  * SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
1912  *
1913  *    This is a host-to-guest blit. It performs a DMA operation to
1914  *    copy a rectangular region of pixels from a single ScreenObject
1915  *    back to the current GMRFB.
1916  *
1917  *    The source coordinate is specified relative to a screen's
1918  *    origin.  The provided screen ID must be valid. If any parameters
1919  *    are invalid, the resulting pixel values are undefined.
1920  *
1921  *    The SVGA device is guaranteed to finish writing to the GMRFB by
1922  *    the time any subsequent FENCE commands are reached.
1923  *
1924  * Availability:
1925  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1926  */
1927 
1928 typedef
1929 #include "vmware_pack_begin.h"
1930 struct {
1931    SVGASignedPoint  destOrigin;
1932    SVGASignedRect   srcRect;
1933    uint32           srcScreenId;
1934 }
1935 #include "vmware_pack_end.h"
1936 SVGAFifoCmdBlitScreenToGMRFB;
1937 
1938 
1939 /*
1940  * SVGA_CMD_ANNOTATION_FILL --
1941  *
1942  *    The annotation commands have been deprecated, should not be used
1943  *    by new drivers.  They used to provide performance hints to the SVGA
1944  *    device about the content of screen updates, but newer SVGA devices
1945  *    ignore these.
1946  *
1947  * Availability:
1948  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1949  */
1950 
1951 typedef
1952 #include "vmware_pack_begin.h"
1953 struct {
1954    SVGAColorBGRX  color;
1955 }
1956 #include "vmware_pack_end.h"
1957 SVGAFifoCmdAnnotationFill;
1958 
1959 
1960 /*
1961  * SVGA_CMD_ANNOTATION_COPY --
1962  *
1963  *    The annotation commands have been deprecated, should not be used
1964  *    by new drivers.  They used to provide performance hints to the SVGA
1965  *    device about the content of screen updates, but newer SVGA devices
1966  *    ignore these.
1967  *
1968  * Availability:
1969  *    SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
1970  */
1971 
1972 typedef
1973 #include "vmware_pack_begin.h"
1974 struct {
1975    SVGASignedPoint  srcOrigin;
1976    uint32           srcScreenId;
1977 }
1978 #include "vmware_pack_end.h"
1979 SVGAFifoCmdAnnotationCopy;
1980 
1981 
1982 /*
1983  * SVGA_CMD_DEFINE_GMR2 --
1984  *
1985  *    Define guest memory region v2.  See the description of GMRs above.
1986  *
1987  * Availability:
1988  *    SVGA_CAP_GMR2
1989  */
1990 
1991 typedef
1992 #include "vmware_pack_begin.h"
1993 struct {
1994    uint32 gmrId;
1995    uint32 numPages;
1996 }
1997 #include "vmware_pack_end.h"
1998 SVGAFifoCmdDefineGMR2;
1999 
2000 
2001 /*
2002  * SVGA_CMD_REMAP_GMR2 --
2003  *
2004  *    Remap guest memory region v2.  See the description of GMRs above.
2005  *
2006  *    This command allows guest to modify a portion of an existing GMR by
2007  *    invalidating it or reassigning it to different guest physical pages.
2008  *    The pages are identified by physical page number (PPN).  The pages
2009  *    are assumed to be pinned and valid for DMA operations.
2010  *
2011  *    Description of command flags:
2012  *
2013  *    SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR.
2014  *       The PPN list must not overlap with the remap region (this can be
2015  *       handled trivially by referencing a separate GMR).  If flag is
2016  *       disabled, PPN list is appended to SVGARemapGMR command.
2017  *
2018  *    SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise
2019  *       it is in PPN32 format.
2020  *
2021  *    SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry.
2022  *       A single PPN can be used to invalidate a portion of a GMR or
2023  *       map it to to a single guest scratch page.
2024  *
2025  * Availability:
2026  *    SVGA_CAP_GMR2
2027  */
2028 
2029 typedef enum {
2030    SVGA_REMAP_GMR2_PPN32         = 0,
2031    SVGA_REMAP_GMR2_VIA_GMR       = (1 << 0),
2032    SVGA_REMAP_GMR2_PPN64         = (1 << 1),
2033    SVGA_REMAP_GMR2_SINGLE_PPN    = (1 << 2),
2034 } SVGARemapGMR2Flags;
2035 
2036 typedef
2037 #include "vmware_pack_begin.h"
2038 struct {
2039    uint32 gmrId;
2040    SVGARemapGMR2Flags flags;
2041    uint32 offsetPages; /* offset in pages to begin remap */
2042    uint32 numPages; /* number of pages to remap */
2043    /*
2044     * Followed by additional data depending on SVGARemapGMR2Flags.
2045     *
2046     * If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows.
2047     * Otherwise an array of page descriptors in PPN32 or PPN64 format
2048     * (according to flag SVGA_REMAP_GMR2_PPN64) follows.  If flag
2049     * SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.
2050     */
2051 }
2052 #include "vmware_pack_end.h"
2053 SVGAFifoCmdRemapGMR2;
2054 
2055 
2056 /*
2057  * Size of SVGA device memory such as frame buffer and FIFO.
2058  */
2059 #define SVGA_VRAM_MIN_SIZE             (4 * 640 * 480) /* bytes */
2060 #define SVGA_VRAM_MIN_SIZE_3D       (16 * 1024 * 1024)
2061 #define SVGA_VRAM_MAX_SIZE         (128 * 1024 * 1024)
2062 #define SVGA_MEMORY_SIZE_MAX      (1024 * 1024 * 1024)
2063 #define SVGA_FIFO_SIZE_MAX           (2 * 1024 * 1024)
2064 #define SVGA_GRAPHICS_MEMORY_KB_MIN       (32 * 1024)
2065 #define SVGA_GRAPHICS_MEMORY_KB_MAX       (2 * 1024 * 1024)
2066 #define SVGA_GRAPHICS_MEMORY_KB_DEFAULT   (256 * 1024)
2067 
2068 #define SVGA_VRAM_SIZE_W2K          (64 * 1024 * 1024) /* 64 MB */
2069 
2070 #if defined(VMX86_SERVER)
2071 #define SVGA_VRAM_SIZE               (4 * 1024 * 1024)
2072 #define SVGA_VRAM_SIZE_3D           (64 * 1024 * 1024)
2073 #define SVGA_FIFO_SIZE                    (256 * 1024)
2074 #define SVGA_FIFO_SIZE_3D                 (516 * 1024)
2075 #define SVGA_MEMORY_SIZE_DEFAULT   (160 * 1024 * 1024)
2076 #define SVGA_AUTODETECT_DEFAULT                  FALSE
2077 #else
2078 #define SVGA_VRAM_SIZE              (16 * 1024 * 1024)
2079 #define SVGA_VRAM_SIZE_3D           SVGA_VRAM_MAX_SIZE
2080 #define SVGA_FIFO_SIZE               (2 * 1024 * 1024)
2081 #define SVGA_FIFO_SIZE_3D               SVGA_FIFO_SIZE
2082 #define SVGA_MEMORY_SIZE_DEFAULT   (768 * 1024 * 1024)
2083 #define SVGA_AUTODETECT_DEFAULT                   TRUE
2084 #endif
2085 
2086 #define SVGA_FIFO_SIZE_GBOBJECTS          (256 * 1024)
2087 #define SVGA_VRAM_SIZE_GBOBJECTS     (4 * 1024 * 1024)
2088 
2089 #endif
2090