1 /* 2 * Copyright (C) 2015 Red Hat, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_fourcc.h> 28 #include <drm/drm_plane_helper.h> 29 30 #include "virtgpu_drv.h" 31 32 static const uint32_t virtio_gpu_formats[] = { 33 DRM_FORMAT_HOST_XRGB8888, 34 }; 35 36 static const uint32_t virtio_gpu_cursor_formats[] = { 37 DRM_FORMAT_HOST_ARGB8888, 38 }; 39 40 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc) 41 { 42 uint32_t format; 43 44 switch (drm_fourcc) { 45 case DRM_FORMAT_XRGB8888: 46 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM; 47 break; 48 case DRM_FORMAT_ARGB8888: 49 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM; 50 break; 51 case DRM_FORMAT_BGRX8888: 52 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM; 53 break; 54 case DRM_FORMAT_BGRA8888: 55 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM; 56 break; 57 default: 58 /* 59 * This should not happen, we handle everything listed 60 * in virtio_gpu_formats[]. 61 */ 62 format = 0; 63 break; 64 } 65 WARN_ON(format == 0); 66 return format; 67 } 68 69 static void virtio_gpu_plane_destroy(struct drm_plane *plane) 70 { 71 drm_plane_cleanup(plane); 72 kfree(plane); 73 } 74 75 static const struct drm_plane_funcs virtio_gpu_plane_funcs = { 76 .update_plane = drm_atomic_helper_update_plane, 77 .disable_plane = drm_atomic_helper_disable_plane, 78 .destroy = virtio_gpu_plane_destroy, 79 .reset = drm_atomic_helper_plane_reset, 80 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 81 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 82 }; 83 84 static int virtio_gpu_plane_atomic_check(struct drm_plane *plane, 85 struct drm_plane_state *state) 86 { 87 bool is_cursor = plane->type == DRM_PLANE_TYPE_CURSOR; 88 struct drm_crtc_state *crtc_state; 89 int ret; 90 91 if (!state->fb || !state->crtc) 92 return 0; 93 94 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 95 if (IS_ERR(crtc_state)) 96 return PTR_ERR(crtc_state); 97 98 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 99 DRM_PLANE_HELPER_NO_SCALING, 100 DRM_PLANE_HELPER_NO_SCALING, 101 is_cursor, true); 102 return ret; 103 } 104 105 static void virtio_gpu_primary_plane_update(struct drm_plane *plane, 106 struct drm_plane_state *old_state) 107 { 108 struct drm_device *dev = plane->dev; 109 struct virtio_gpu_device *vgdev = dev->dev_private; 110 struct virtio_gpu_output *output = NULL; 111 struct virtio_gpu_framebuffer *vgfb; 112 struct virtio_gpu_object *bo; 113 uint32_t handle; 114 115 if (plane->state->crtc) 116 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc); 117 if (old_state->crtc) 118 output = drm_crtc_to_virtio_gpu_output(old_state->crtc); 119 if (WARN_ON(!output)) 120 return; 121 122 if (plane->state->fb && output->enabled) { 123 vgfb = to_virtio_gpu_framebuffer(plane->state->fb); 124 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]); 125 handle = bo->hw_res_handle; 126 if (bo->dumb) { 127 struct virtio_gpu_object_array *objs; 128 129 objs = virtio_gpu_array_alloc(1); 130 if (!objs) 131 return; 132 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]); 133 virtio_gpu_cmd_transfer_to_host_2d 134 (vgdev, 0, 135 plane->state->src_w >> 16, 136 plane->state->src_h >> 16, 137 plane->state->src_x >> 16, 138 plane->state->src_y >> 16, 139 objs, NULL); 140 } 141 } else { 142 handle = 0; 143 } 144 145 DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n", handle, 146 plane->state->crtc_w, plane->state->crtc_h, 147 plane->state->crtc_x, plane->state->crtc_y, 148 plane->state->src_w >> 16, 149 plane->state->src_h >> 16, 150 plane->state->src_x >> 16, 151 plane->state->src_y >> 16); 152 virtio_gpu_cmd_set_scanout(vgdev, output->index, handle, 153 plane->state->src_w >> 16, 154 plane->state->src_h >> 16, 155 plane->state->src_x >> 16, 156 plane->state->src_y >> 16); 157 if (handle) 158 virtio_gpu_cmd_resource_flush(vgdev, handle, 159 plane->state->src_x >> 16, 160 plane->state->src_y >> 16, 161 plane->state->src_w >> 16, 162 plane->state->src_h >> 16); 163 } 164 165 static int virtio_gpu_cursor_prepare_fb(struct drm_plane *plane, 166 struct drm_plane_state *new_state) 167 { 168 struct drm_device *dev = plane->dev; 169 struct virtio_gpu_device *vgdev = dev->dev_private; 170 struct virtio_gpu_framebuffer *vgfb; 171 struct virtio_gpu_object *bo; 172 173 if (!new_state->fb) 174 return 0; 175 176 vgfb = to_virtio_gpu_framebuffer(new_state->fb); 177 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]); 178 if (bo && bo->dumb && (plane->state->fb != new_state->fb)) { 179 vgfb->fence = virtio_gpu_fence_alloc(vgdev); 180 if (!vgfb->fence) 181 return -ENOMEM; 182 } 183 184 return 0; 185 } 186 187 static void virtio_gpu_cursor_cleanup_fb(struct drm_plane *plane, 188 struct drm_plane_state *old_state) 189 { 190 struct virtio_gpu_framebuffer *vgfb; 191 192 if (!plane->state->fb) 193 return; 194 195 vgfb = to_virtio_gpu_framebuffer(plane->state->fb); 196 if (vgfb->fence) { 197 dma_fence_put(&vgfb->fence->f); 198 vgfb->fence = NULL; 199 } 200 } 201 202 static void virtio_gpu_cursor_plane_update(struct drm_plane *plane, 203 struct drm_plane_state *old_state) 204 { 205 struct drm_device *dev = plane->dev; 206 struct virtio_gpu_device *vgdev = dev->dev_private; 207 struct virtio_gpu_output *output = NULL; 208 struct virtio_gpu_framebuffer *vgfb; 209 struct virtio_gpu_object *bo = NULL; 210 uint32_t handle; 211 212 if (plane->state->crtc) 213 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc); 214 if (old_state->crtc) 215 output = drm_crtc_to_virtio_gpu_output(old_state->crtc); 216 if (WARN_ON(!output)) 217 return; 218 219 if (plane->state->fb) { 220 vgfb = to_virtio_gpu_framebuffer(plane->state->fb); 221 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]); 222 handle = bo->hw_res_handle; 223 } else { 224 handle = 0; 225 } 226 227 if (bo && bo->dumb && (plane->state->fb != old_state->fb)) { 228 /* new cursor -- update & wait */ 229 struct virtio_gpu_object_array *objs; 230 231 objs = virtio_gpu_array_alloc(1); 232 if (!objs) 233 return; 234 virtio_gpu_array_add_obj(objs, vgfb->base.obj[0]); 235 virtio_gpu_array_lock_resv(objs); 236 virtio_gpu_cmd_transfer_to_host_2d 237 (vgdev, 0, 238 plane->state->crtc_w, 239 plane->state->crtc_h, 240 0, 0, objs, vgfb->fence); 241 dma_fence_wait(&vgfb->fence->f, true); 242 dma_fence_put(&vgfb->fence->f); 243 vgfb->fence = NULL; 244 } 245 246 if (plane->state->fb != old_state->fb) { 247 DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle, 248 plane->state->crtc_x, 249 plane->state->crtc_y, 250 plane->state->fb ? plane->state->fb->hot_x : 0, 251 plane->state->fb ? plane->state->fb->hot_y : 0); 252 output->cursor.hdr.type = 253 cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR); 254 output->cursor.resource_id = cpu_to_le32(handle); 255 if (plane->state->fb) { 256 output->cursor.hot_x = 257 cpu_to_le32(plane->state->fb->hot_x); 258 output->cursor.hot_y = 259 cpu_to_le32(plane->state->fb->hot_y); 260 } else { 261 output->cursor.hot_x = cpu_to_le32(0); 262 output->cursor.hot_y = cpu_to_le32(0); 263 } 264 } else { 265 DRM_DEBUG("move +%d+%d\n", 266 plane->state->crtc_x, 267 plane->state->crtc_y); 268 output->cursor.hdr.type = 269 cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR); 270 } 271 output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x); 272 output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y); 273 virtio_gpu_cursor_ping(vgdev, output); 274 } 275 276 static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = { 277 .atomic_check = virtio_gpu_plane_atomic_check, 278 .atomic_update = virtio_gpu_primary_plane_update, 279 }; 280 281 static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = { 282 .prepare_fb = virtio_gpu_cursor_prepare_fb, 283 .cleanup_fb = virtio_gpu_cursor_cleanup_fb, 284 .atomic_check = virtio_gpu_plane_atomic_check, 285 .atomic_update = virtio_gpu_cursor_plane_update, 286 }; 287 288 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev, 289 enum drm_plane_type type, 290 int index) 291 { 292 struct drm_device *dev = vgdev->ddev; 293 const struct drm_plane_helper_funcs *funcs; 294 struct drm_plane *plane; 295 const uint32_t *formats; 296 int ret, nformats; 297 298 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 299 if (!plane) 300 return ERR_PTR(-ENOMEM); 301 302 if (type == DRM_PLANE_TYPE_CURSOR) { 303 formats = virtio_gpu_cursor_formats; 304 nformats = ARRAY_SIZE(virtio_gpu_cursor_formats); 305 funcs = &virtio_gpu_cursor_helper_funcs; 306 } else { 307 formats = virtio_gpu_formats; 308 nformats = ARRAY_SIZE(virtio_gpu_formats); 309 funcs = &virtio_gpu_primary_helper_funcs; 310 } 311 ret = drm_universal_plane_init(dev, plane, 1 << index, 312 &virtio_gpu_plane_funcs, 313 formats, nformats, 314 NULL, type, NULL); 315 if (ret) 316 goto err_plane_init; 317 318 drm_plane_helper_add(plane, funcs); 319 return plane; 320 321 err_plane_init: 322 kfree(plane); 323 return ERR_PTR(ret); 324 } 325