1 /* 2 * Copyright (C) 2015 Red Hat, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sublicense, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial 15 * portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #include "virtgpu_drv.h" 27 #include <drm/drm_plane_helper.h> 28 #include <drm/drm_atomic_helper.h> 29 30 static const uint32_t virtio_gpu_formats[] = { 31 DRM_FORMAT_HOST_XRGB8888, 32 }; 33 34 static const uint32_t virtio_gpu_cursor_formats[] = { 35 DRM_FORMAT_HOST_ARGB8888, 36 }; 37 38 uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc) 39 { 40 uint32_t format; 41 42 switch (drm_fourcc) { 43 case DRM_FORMAT_XRGB8888: 44 format = VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM; 45 break; 46 case DRM_FORMAT_ARGB8888: 47 format = VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM; 48 break; 49 case DRM_FORMAT_BGRX8888: 50 format = VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM; 51 break; 52 case DRM_FORMAT_BGRA8888: 53 format = VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM; 54 break; 55 default: 56 /* 57 * This should not happen, we handle everything listed 58 * in virtio_gpu_formats[]. 59 */ 60 format = 0; 61 break; 62 } 63 WARN_ON(format == 0); 64 return format; 65 } 66 67 static void virtio_gpu_plane_destroy(struct drm_plane *plane) 68 { 69 drm_plane_cleanup(plane); 70 kfree(plane); 71 } 72 73 static const struct drm_plane_funcs virtio_gpu_plane_funcs = { 74 .update_plane = drm_atomic_helper_update_plane, 75 .disable_plane = drm_atomic_helper_disable_plane, 76 .destroy = virtio_gpu_plane_destroy, 77 .reset = drm_atomic_helper_plane_reset, 78 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 79 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 80 }; 81 82 static int virtio_gpu_plane_atomic_check(struct drm_plane *plane, 83 struct drm_plane_state *state) 84 { 85 return 0; 86 } 87 88 static void virtio_gpu_primary_plane_update(struct drm_plane *plane, 89 struct drm_plane_state *old_state) 90 { 91 struct drm_device *dev = plane->dev; 92 struct virtio_gpu_device *vgdev = dev->dev_private; 93 struct virtio_gpu_output *output = NULL; 94 struct virtio_gpu_framebuffer *vgfb; 95 struct virtio_gpu_object *bo; 96 uint32_t handle; 97 98 if (plane->state->crtc) 99 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc); 100 if (old_state->crtc) 101 output = drm_crtc_to_virtio_gpu_output(old_state->crtc); 102 if (WARN_ON(!output)) 103 return; 104 105 if (plane->state->fb && output->enabled) { 106 vgfb = to_virtio_gpu_framebuffer(plane->state->fb); 107 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]); 108 handle = bo->hw_res_handle; 109 if (bo->dumb) { 110 virtio_gpu_cmd_transfer_to_host_2d 111 (vgdev, bo, 0, 112 cpu_to_le32(plane->state->src_w >> 16), 113 cpu_to_le32(plane->state->src_h >> 16), 114 cpu_to_le32(plane->state->src_x >> 16), 115 cpu_to_le32(plane->state->src_y >> 16), NULL); 116 } 117 } else { 118 handle = 0; 119 } 120 121 DRM_DEBUG("handle 0x%x, crtc %dx%d+%d+%d, src %dx%d+%d+%d\n", handle, 122 plane->state->crtc_w, plane->state->crtc_h, 123 plane->state->crtc_x, plane->state->crtc_y, 124 plane->state->src_w >> 16, 125 plane->state->src_h >> 16, 126 plane->state->src_x >> 16, 127 plane->state->src_y >> 16); 128 virtio_gpu_cmd_set_scanout(vgdev, output->index, handle, 129 plane->state->src_w >> 16, 130 plane->state->src_h >> 16, 131 plane->state->src_x >> 16, 132 plane->state->src_y >> 16); 133 virtio_gpu_cmd_resource_flush(vgdev, handle, 134 plane->state->src_x >> 16, 135 plane->state->src_y >> 16, 136 plane->state->src_w >> 16, 137 plane->state->src_h >> 16); 138 } 139 140 static int virtio_gpu_cursor_prepare_fb(struct drm_plane *plane, 141 struct drm_plane_state *new_state) 142 { 143 struct drm_device *dev = plane->dev; 144 struct virtio_gpu_device *vgdev = dev->dev_private; 145 struct virtio_gpu_framebuffer *vgfb; 146 struct virtio_gpu_object *bo; 147 148 if (!new_state->fb) 149 return 0; 150 151 vgfb = to_virtio_gpu_framebuffer(new_state->fb); 152 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]); 153 if (bo && bo->dumb && (plane->state->fb != new_state->fb)) { 154 vgfb->fence = virtio_gpu_fence_alloc(vgdev); 155 if (!vgfb->fence) 156 return -ENOMEM; 157 } 158 159 return 0; 160 } 161 162 static void virtio_gpu_cursor_cleanup_fb(struct drm_plane *plane, 163 struct drm_plane_state *old_state) 164 { 165 struct virtio_gpu_framebuffer *vgfb; 166 167 if (!plane->state->fb) 168 return; 169 170 vgfb = to_virtio_gpu_framebuffer(plane->state->fb); 171 if (vgfb->fence) 172 virtio_gpu_fence_cleanup(vgfb->fence); 173 } 174 175 static void virtio_gpu_cursor_plane_update(struct drm_plane *plane, 176 struct drm_plane_state *old_state) 177 { 178 struct drm_device *dev = plane->dev; 179 struct virtio_gpu_device *vgdev = dev->dev_private; 180 struct virtio_gpu_output *output = NULL; 181 struct virtio_gpu_framebuffer *vgfb; 182 struct virtio_gpu_object *bo = NULL; 183 uint32_t handle; 184 int ret = 0; 185 186 if (plane->state->crtc) 187 output = drm_crtc_to_virtio_gpu_output(plane->state->crtc); 188 if (old_state->crtc) 189 output = drm_crtc_to_virtio_gpu_output(old_state->crtc); 190 if (WARN_ON(!output)) 191 return; 192 193 if (plane->state->fb) { 194 vgfb = to_virtio_gpu_framebuffer(plane->state->fb); 195 bo = gem_to_virtio_gpu_obj(vgfb->base.obj[0]); 196 handle = bo->hw_res_handle; 197 } else { 198 handle = 0; 199 } 200 201 if (bo && bo->dumb && (plane->state->fb != old_state->fb)) { 202 /* new cursor -- update & wait */ 203 virtio_gpu_cmd_transfer_to_host_2d 204 (vgdev, bo, 0, 205 cpu_to_le32(plane->state->crtc_w), 206 cpu_to_le32(plane->state->crtc_h), 207 0, 0, vgfb->fence); 208 ret = virtio_gpu_object_reserve(bo, false); 209 if (!ret) { 210 reservation_object_add_excl_fence(bo->tbo.resv, 211 &vgfb->fence->f); 212 dma_fence_put(&vgfb->fence->f); 213 vgfb->fence = NULL; 214 virtio_gpu_object_unreserve(bo); 215 virtio_gpu_object_wait(bo, false); 216 } 217 } 218 219 if (plane->state->fb != old_state->fb) { 220 DRM_DEBUG("update, handle %d, pos +%d+%d, hot %d,%d\n", handle, 221 plane->state->crtc_x, 222 plane->state->crtc_y, 223 plane->state->fb ? plane->state->fb->hot_x : 0, 224 plane->state->fb ? plane->state->fb->hot_y : 0); 225 output->cursor.hdr.type = 226 cpu_to_le32(VIRTIO_GPU_CMD_UPDATE_CURSOR); 227 output->cursor.resource_id = cpu_to_le32(handle); 228 if (plane->state->fb) { 229 output->cursor.hot_x = 230 cpu_to_le32(plane->state->fb->hot_x); 231 output->cursor.hot_y = 232 cpu_to_le32(plane->state->fb->hot_y); 233 } else { 234 output->cursor.hot_x = cpu_to_le32(0); 235 output->cursor.hot_y = cpu_to_le32(0); 236 } 237 } else { 238 DRM_DEBUG("move +%d+%d\n", 239 plane->state->crtc_x, 240 plane->state->crtc_y); 241 output->cursor.hdr.type = 242 cpu_to_le32(VIRTIO_GPU_CMD_MOVE_CURSOR); 243 } 244 output->cursor.pos.x = cpu_to_le32(plane->state->crtc_x); 245 output->cursor.pos.y = cpu_to_le32(plane->state->crtc_y); 246 virtio_gpu_cursor_ping(vgdev, output); 247 } 248 249 static const struct drm_plane_helper_funcs virtio_gpu_primary_helper_funcs = { 250 .atomic_check = virtio_gpu_plane_atomic_check, 251 .atomic_update = virtio_gpu_primary_plane_update, 252 }; 253 254 static const struct drm_plane_helper_funcs virtio_gpu_cursor_helper_funcs = { 255 .prepare_fb = virtio_gpu_cursor_prepare_fb, 256 .cleanup_fb = virtio_gpu_cursor_cleanup_fb, 257 .atomic_check = virtio_gpu_plane_atomic_check, 258 .atomic_update = virtio_gpu_cursor_plane_update, 259 }; 260 261 struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev, 262 enum drm_plane_type type, 263 int index) 264 { 265 struct drm_device *dev = vgdev->ddev; 266 const struct drm_plane_helper_funcs *funcs; 267 struct drm_plane *plane; 268 const uint32_t *formats; 269 int ret, nformats; 270 271 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 272 if (!plane) 273 return ERR_PTR(-ENOMEM); 274 275 if (type == DRM_PLANE_TYPE_CURSOR) { 276 formats = virtio_gpu_cursor_formats; 277 nformats = ARRAY_SIZE(virtio_gpu_cursor_formats); 278 funcs = &virtio_gpu_cursor_helper_funcs; 279 } else { 280 formats = virtio_gpu_formats; 281 nformats = ARRAY_SIZE(virtio_gpu_formats); 282 funcs = &virtio_gpu_primary_helper_funcs; 283 } 284 ret = drm_universal_plane_init(dev, plane, 1 << index, 285 &virtio_gpu_plane_funcs, 286 formats, nformats, 287 NULL, type, NULL); 288 if (ret) 289 goto err_plane_init; 290 291 drm_plane_helper_add(plane, funcs); 292 return plane; 293 294 err_plane_init: 295 kfree(plane); 296 return ERR_PTR(ret); 297 } 298