1 /* 2 * Copyright (C) 2015 Red Hat, Inc. 3 * All Rights Reserved. 4 * 5 * Authors: 6 * Dave Airlie 7 * Alon Levy 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 */ 27 28 #include <drm/drmP.h> 29 #include <drm/virtgpu_drm.h> 30 #include <drm/ttm/ttm_execbuf_util.h> 31 #include <linux/sync_file.h> 32 33 #include "virtgpu_drv.h" 34 35 static void convert_to_hw_box(struct virtio_gpu_box *dst, 36 const struct drm_virtgpu_3d_box *src) 37 { 38 dst->x = cpu_to_le32(src->x); 39 dst->y = cpu_to_le32(src->y); 40 dst->z = cpu_to_le32(src->z); 41 dst->w = cpu_to_le32(src->w); 42 dst->h = cpu_to_le32(src->h); 43 dst->d = cpu_to_le32(src->d); 44 } 45 46 static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data, 47 struct drm_file *file_priv) 48 { 49 struct virtio_gpu_device *vgdev = dev->dev_private; 50 struct drm_virtgpu_map *virtio_gpu_map = data; 51 52 return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev, 53 virtio_gpu_map->handle, 54 &virtio_gpu_map->offset); 55 } 56 57 int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket, 58 struct list_head *head) 59 { 60 struct ttm_operation_ctx ctx = { false, false }; 61 struct ttm_validate_buffer *buf; 62 struct ttm_buffer_object *bo; 63 struct virtio_gpu_object *qobj; 64 int ret; 65 66 ret = ttm_eu_reserve_buffers(ticket, head, true, NULL); 67 if (ret != 0) 68 return ret; 69 70 list_for_each_entry(buf, head, head) { 71 bo = buf->bo; 72 qobj = container_of(bo, struct virtio_gpu_object, tbo); 73 ret = ttm_bo_validate(bo, &qobj->placement, &ctx); 74 if (ret) { 75 ttm_eu_backoff_reservation(ticket, head); 76 return ret; 77 } 78 } 79 return 0; 80 } 81 82 void virtio_gpu_unref_list(struct list_head *head) 83 { 84 struct ttm_validate_buffer *buf; 85 struct ttm_buffer_object *bo; 86 struct virtio_gpu_object *qobj; 87 88 list_for_each_entry(buf, head, head) { 89 bo = buf->bo; 90 qobj = container_of(bo, struct virtio_gpu_object, tbo); 91 92 drm_gem_object_put_unlocked(&qobj->gem_base); 93 } 94 } 95 96 /* 97 * Usage of execbuffer: 98 * Relocations need to take into account the full VIRTIO_GPUDrawable size. 99 * However, the command as passed from user space must *not* contain the initial 100 * VIRTIO_GPUReleaseInfo struct (first XXX bytes) 101 */ 102 static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data, 103 struct drm_file *drm_file) 104 { 105 struct drm_virtgpu_execbuffer *exbuf = data; 106 struct virtio_gpu_device *vgdev = dev->dev_private; 107 struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv; 108 struct drm_gem_object *gobj; 109 struct virtio_gpu_fence *out_fence; 110 struct virtio_gpu_object *qobj; 111 int ret; 112 uint32_t *bo_handles = NULL; 113 void __user *user_bo_handles = NULL; 114 struct list_head validate_list; 115 struct ttm_validate_buffer *buflist = NULL; 116 int i; 117 struct ww_acquire_ctx ticket; 118 struct sync_file *sync_file; 119 int in_fence_fd = exbuf->fence_fd; 120 int out_fence_fd = -1; 121 void *buf; 122 123 if (vgdev->has_virgl_3d == false) 124 return -ENOSYS; 125 126 if ((exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS)) 127 return -EINVAL; 128 129 exbuf->fence_fd = -1; 130 131 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) { 132 struct dma_fence *in_fence; 133 134 in_fence = sync_file_get_fence(in_fence_fd); 135 136 if (!in_fence) 137 return -EINVAL; 138 139 /* 140 * Wait if the fence is from a foreign context, or if the fence 141 * array contains any fence from a foreign context. 142 */ 143 ret = 0; 144 if (!dma_fence_match_context(in_fence, vgdev->fence_drv.context)) 145 ret = dma_fence_wait(in_fence, true); 146 147 dma_fence_put(in_fence); 148 if (ret) 149 return ret; 150 } 151 152 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) { 153 out_fence_fd = get_unused_fd_flags(O_CLOEXEC); 154 if (out_fence_fd < 0) 155 return out_fence_fd; 156 } 157 158 INIT_LIST_HEAD(&validate_list); 159 if (exbuf->num_bo_handles) { 160 161 bo_handles = kvmalloc_array(exbuf->num_bo_handles, 162 sizeof(uint32_t), GFP_KERNEL); 163 buflist = kvmalloc_array(exbuf->num_bo_handles, 164 sizeof(struct ttm_validate_buffer), 165 GFP_KERNEL | __GFP_ZERO); 166 if (!bo_handles || !buflist) { 167 ret = -ENOMEM; 168 goto out_unused_fd; 169 } 170 171 user_bo_handles = (void __user *)(uintptr_t)exbuf->bo_handles; 172 if (copy_from_user(bo_handles, user_bo_handles, 173 exbuf->num_bo_handles * sizeof(uint32_t))) { 174 ret = -EFAULT; 175 goto out_unused_fd; 176 } 177 178 for (i = 0; i < exbuf->num_bo_handles; i++) { 179 gobj = drm_gem_object_lookup(drm_file, bo_handles[i]); 180 if (!gobj) { 181 ret = -ENOENT; 182 goto out_unused_fd; 183 } 184 185 qobj = gem_to_virtio_gpu_obj(gobj); 186 buflist[i].bo = &qobj->tbo; 187 188 list_add(&buflist[i].head, &validate_list); 189 } 190 kvfree(bo_handles); 191 bo_handles = NULL; 192 } 193 194 ret = virtio_gpu_object_list_validate(&ticket, &validate_list); 195 if (ret) 196 goto out_free; 197 198 buf = memdup_user((void __user *)(uintptr_t)exbuf->command, 199 exbuf->size); 200 if (IS_ERR(buf)) { 201 ret = PTR_ERR(buf); 202 goto out_unresv; 203 } 204 205 out_fence = virtio_gpu_fence_alloc(vgdev); 206 if(!out_fence) { 207 ret = -ENOMEM; 208 goto out_memdup; 209 } 210 211 if (out_fence_fd >= 0) { 212 sync_file = sync_file_create(&out_fence->f); 213 if (!sync_file) { 214 dma_fence_put(&out_fence->f); 215 ret = -ENOMEM; 216 goto out_memdup; 217 } 218 219 exbuf->fence_fd = out_fence_fd; 220 fd_install(out_fence_fd, sync_file->file); 221 } 222 223 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size, 224 vfpriv->ctx_id, out_fence); 225 226 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &out_fence->f); 227 228 /* fence the command bo */ 229 virtio_gpu_unref_list(&validate_list); 230 kvfree(buflist); 231 return 0; 232 233 out_memdup: 234 kfree(buf); 235 out_unresv: 236 ttm_eu_backoff_reservation(&ticket, &validate_list); 237 out_free: 238 virtio_gpu_unref_list(&validate_list); 239 out_unused_fd: 240 kvfree(bo_handles); 241 kvfree(buflist); 242 243 if (out_fence_fd >= 0) 244 put_unused_fd(out_fence_fd); 245 246 return ret; 247 } 248 249 static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data, 250 struct drm_file *file_priv) 251 { 252 struct virtio_gpu_device *vgdev = dev->dev_private; 253 struct drm_virtgpu_getparam *param = data; 254 int value; 255 256 switch (param->param) { 257 case VIRTGPU_PARAM_3D_FEATURES: 258 value = vgdev->has_virgl_3d == true ? 1 : 0; 259 break; 260 case VIRTGPU_PARAM_CAPSET_QUERY_FIX: 261 value = 1; 262 break; 263 default: 264 return -EINVAL; 265 } 266 if (copy_to_user((void __user *)(unsigned long)param->value, 267 &value, sizeof(int))) { 268 return -EFAULT; 269 } 270 return 0; 271 } 272 273 static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data, 274 struct drm_file *file_priv) 275 { 276 struct virtio_gpu_device *vgdev = dev->dev_private; 277 struct drm_virtgpu_resource_create *rc = data; 278 struct virtio_gpu_fence *fence; 279 int ret; 280 struct virtio_gpu_object *qobj; 281 struct drm_gem_object *obj; 282 uint32_t handle = 0; 283 struct virtio_gpu_object_params params = { 0 }; 284 285 if (vgdev->has_virgl_3d == false) { 286 if (rc->depth > 1) 287 return -EINVAL; 288 if (rc->nr_samples > 1) 289 return -EINVAL; 290 if (rc->last_level > 1) 291 return -EINVAL; 292 if (rc->target != 2) 293 return -EINVAL; 294 if (rc->array_size > 1) 295 return -EINVAL; 296 } 297 298 params.format = rc->format; 299 params.width = rc->width; 300 params.height = rc->height; 301 params.size = rc->size; 302 if (vgdev->has_virgl_3d) { 303 params.virgl = true; 304 params.target = rc->target; 305 params.bind = rc->bind; 306 params.depth = rc->depth; 307 params.array_size = rc->array_size; 308 params.last_level = rc->last_level; 309 params.nr_samples = rc->nr_samples; 310 params.flags = rc->flags; 311 } 312 /* allocate a single page size object */ 313 if (params.size == 0) 314 params.size = PAGE_SIZE; 315 316 fence = virtio_gpu_fence_alloc(vgdev); 317 if (!fence) 318 return -ENOMEM; 319 qobj = virtio_gpu_alloc_object(dev, ¶ms, fence); 320 dma_fence_put(&fence->f); 321 if (IS_ERR(qobj)) 322 return PTR_ERR(qobj); 323 obj = &qobj->gem_base; 324 325 ret = drm_gem_handle_create(file_priv, obj, &handle); 326 if (ret) { 327 drm_gem_object_release(obj); 328 return ret; 329 } 330 drm_gem_object_put_unlocked(obj); 331 332 rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */ 333 rc->bo_handle = handle; 334 return 0; 335 } 336 337 static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data, 338 struct drm_file *file_priv) 339 { 340 struct drm_virtgpu_resource_info *ri = data; 341 struct drm_gem_object *gobj = NULL; 342 struct virtio_gpu_object *qobj = NULL; 343 344 gobj = drm_gem_object_lookup(file_priv, ri->bo_handle); 345 if (gobj == NULL) 346 return -ENOENT; 347 348 qobj = gem_to_virtio_gpu_obj(gobj); 349 350 ri->size = qobj->gem_base.size; 351 ri->res_handle = qobj->hw_res_handle; 352 drm_gem_object_put_unlocked(gobj); 353 return 0; 354 } 355 356 static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, 357 void *data, 358 struct drm_file *file) 359 { 360 struct virtio_gpu_device *vgdev = dev->dev_private; 361 struct virtio_gpu_fpriv *vfpriv = file->driver_priv; 362 struct drm_virtgpu_3d_transfer_from_host *args = data; 363 struct ttm_operation_ctx ctx = { true, false }; 364 struct drm_gem_object *gobj = NULL; 365 struct virtio_gpu_object *qobj = NULL; 366 struct virtio_gpu_fence *fence; 367 int ret; 368 u32 offset = args->offset; 369 struct virtio_gpu_box box; 370 371 if (vgdev->has_virgl_3d == false) 372 return -ENOSYS; 373 374 gobj = drm_gem_object_lookup(file, args->bo_handle); 375 if (gobj == NULL) 376 return -ENOENT; 377 378 qobj = gem_to_virtio_gpu_obj(gobj); 379 380 ret = virtio_gpu_object_reserve(qobj, false); 381 if (ret) 382 goto out; 383 384 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); 385 if (unlikely(ret)) 386 goto out_unres; 387 388 convert_to_hw_box(&box, &args->box); 389 390 fence = virtio_gpu_fence_alloc(vgdev); 391 if (!fence) { 392 ret = -ENOMEM; 393 goto out_unres; 394 } 395 virtio_gpu_cmd_transfer_from_host_3d 396 (vgdev, qobj->hw_res_handle, 397 vfpriv->ctx_id, offset, args->level, 398 &box, fence); 399 reservation_object_add_excl_fence(qobj->tbo.resv, 400 &fence->f); 401 402 dma_fence_put(&fence->f); 403 out_unres: 404 virtio_gpu_object_unreserve(qobj); 405 out: 406 drm_gem_object_put_unlocked(gobj); 407 return ret; 408 } 409 410 static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, 411 struct drm_file *file) 412 { 413 struct virtio_gpu_device *vgdev = dev->dev_private; 414 struct virtio_gpu_fpriv *vfpriv = file->driver_priv; 415 struct drm_virtgpu_3d_transfer_to_host *args = data; 416 struct ttm_operation_ctx ctx = { true, false }; 417 struct drm_gem_object *gobj = NULL; 418 struct virtio_gpu_object *qobj = NULL; 419 struct virtio_gpu_fence *fence; 420 struct virtio_gpu_box box; 421 int ret; 422 u32 offset = args->offset; 423 424 gobj = drm_gem_object_lookup(file, args->bo_handle); 425 if (gobj == NULL) 426 return -ENOENT; 427 428 qobj = gem_to_virtio_gpu_obj(gobj); 429 430 ret = virtio_gpu_object_reserve(qobj, false); 431 if (ret) 432 goto out; 433 434 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); 435 if (unlikely(ret)) 436 goto out_unres; 437 438 convert_to_hw_box(&box, &args->box); 439 if (!vgdev->has_virgl_3d) { 440 virtio_gpu_cmd_transfer_to_host_2d 441 (vgdev, qobj, offset, 442 box.w, box.h, box.x, box.y, NULL); 443 } else { 444 fence = virtio_gpu_fence_alloc(vgdev); 445 if (!fence) { 446 ret = -ENOMEM; 447 goto out_unres; 448 } 449 virtio_gpu_cmd_transfer_to_host_3d 450 (vgdev, qobj, 451 vfpriv ? vfpriv->ctx_id : 0, offset, 452 args->level, &box, fence); 453 reservation_object_add_excl_fence(qobj->tbo.resv, 454 &fence->f); 455 dma_fence_put(&fence->f); 456 } 457 458 out_unres: 459 virtio_gpu_object_unreserve(qobj); 460 out: 461 drm_gem_object_put_unlocked(gobj); 462 return ret; 463 } 464 465 static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data, 466 struct drm_file *file) 467 { 468 struct drm_virtgpu_3d_wait *args = data; 469 struct drm_gem_object *gobj = NULL; 470 struct virtio_gpu_object *qobj = NULL; 471 int ret; 472 bool nowait = false; 473 474 gobj = drm_gem_object_lookup(file, args->handle); 475 if (gobj == NULL) 476 return -ENOENT; 477 478 qobj = gem_to_virtio_gpu_obj(gobj); 479 480 if (args->flags & VIRTGPU_WAIT_NOWAIT) 481 nowait = true; 482 ret = virtio_gpu_object_wait(qobj, nowait); 483 484 drm_gem_object_put_unlocked(gobj); 485 return ret; 486 } 487 488 static int virtio_gpu_get_caps_ioctl(struct drm_device *dev, 489 void *data, struct drm_file *file) 490 { 491 struct virtio_gpu_device *vgdev = dev->dev_private; 492 struct drm_virtgpu_get_caps *args = data; 493 unsigned size, host_caps_size; 494 int i; 495 int found_valid = -1; 496 int ret; 497 struct virtio_gpu_drv_cap_cache *cache_ent; 498 void *ptr; 499 500 if (vgdev->num_capsets == 0) 501 return -ENOSYS; 502 503 /* don't allow userspace to pass 0 */ 504 if (args->size == 0) 505 return -EINVAL; 506 507 spin_lock(&vgdev->display_info_lock); 508 for (i = 0; i < vgdev->num_capsets; i++) { 509 if (vgdev->capsets[i].id == args->cap_set_id) { 510 if (vgdev->capsets[i].max_version >= args->cap_set_ver) { 511 found_valid = i; 512 break; 513 } 514 } 515 } 516 517 if (found_valid == -1) { 518 spin_unlock(&vgdev->display_info_lock); 519 return -EINVAL; 520 } 521 522 host_caps_size = vgdev->capsets[found_valid].max_size; 523 /* only copy to user the minimum of the host caps size or the guest caps size */ 524 size = min(args->size, host_caps_size); 525 526 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) { 527 if (cache_ent->id == args->cap_set_id && 528 cache_ent->version == args->cap_set_ver) { 529 ptr = cache_ent->caps_cache; 530 spin_unlock(&vgdev->display_info_lock); 531 goto copy_exit; 532 } 533 } 534 spin_unlock(&vgdev->display_info_lock); 535 536 /* not in cache - need to talk to hw */ 537 virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver, 538 &cache_ent); 539 540 ret = wait_event_timeout(vgdev->resp_wq, 541 atomic_read(&cache_ent->is_valid), 5 * HZ); 542 if (!ret) 543 return -EBUSY; 544 545 ptr = cache_ent->caps_cache; 546 547 copy_exit: 548 if (copy_to_user((void __user *)(unsigned long)args->addr, ptr, size)) 549 return -EFAULT; 550 551 return 0; 552 } 553 554 struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = { 555 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl, 556 DRM_AUTH | DRM_RENDER_ALLOW), 557 558 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl, 559 DRM_AUTH | DRM_RENDER_ALLOW), 560 561 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl, 562 DRM_AUTH | DRM_RENDER_ALLOW), 563 564 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE, 565 virtio_gpu_resource_create_ioctl, 566 DRM_AUTH | DRM_RENDER_ALLOW), 567 568 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl, 569 DRM_AUTH | DRM_RENDER_ALLOW), 570 571 /* make transfer async to the main ring? - no sure, can we 572 * thread these in the underlying GL 573 */ 574 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST, 575 virtio_gpu_transfer_from_host_ioctl, 576 DRM_AUTH | DRM_RENDER_ALLOW), 577 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST, 578 virtio_gpu_transfer_to_host_ioctl, 579 DRM_AUTH | DRM_RENDER_ALLOW), 580 581 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl, 582 DRM_AUTH | DRM_RENDER_ALLOW), 583 584 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl, 585 DRM_AUTH | DRM_RENDER_ALLOW), 586 }; 587