1 /* 2 * Copyright (C) 2015 Red Hat, Inc. 3 * All Rights Reserved. 4 * 5 * Authors: 6 * Dave Airlie 7 * Alon Levy 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 */ 27 28 #include <linux/file.h> 29 #include <linux/sync_file.h> 30 31 #include <drm/drm_file.h> 32 #include <drm/virtgpu_drm.h> 33 34 #include "virtgpu_drv.h" 35 36 static void virtio_gpu_create_context(struct drm_device *dev, 37 struct drm_file *file) 38 { 39 struct virtio_gpu_device *vgdev = dev->dev_private; 40 struct virtio_gpu_fpriv *vfpriv = file->driver_priv; 41 char dbgname[TASK_COMM_LEN]; 42 43 mutex_lock(&vfpriv->context_lock); 44 if (vfpriv->context_created) 45 goto out_unlock; 46 47 get_task_comm(dbgname, current); 48 virtio_gpu_cmd_context_create(vgdev, vfpriv->ctx_id, 49 strlen(dbgname), dbgname); 50 virtio_gpu_notify(vgdev); 51 vfpriv->context_created = true; 52 53 out_unlock: 54 mutex_unlock(&vfpriv->context_lock); 55 } 56 57 static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data, 58 struct drm_file *file) 59 { 60 struct virtio_gpu_device *vgdev = dev->dev_private; 61 struct drm_virtgpu_map *virtio_gpu_map = data; 62 63 return virtio_gpu_mode_dumb_mmap(file, vgdev->ddev, 64 virtio_gpu_map->handle, 65 &virtio_gpu_map->offset); 66 } 67 68 /* 69 * Usage of execbuffer: 70 * Relocations need to take into account the full VIRTIO_GPUDrawable size. 71 * However, the command as passed from user space must *not* contain the initial 72 * VIRTIO_GPUReleaseInfo struct (first XXX bytes) 73 */ 74 static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data, 75 struct drm_file *file) 76 { 77 struct drm_virtgpu_execbuffer *exbuf = data; 78 struct virtio_gpu_device *vgdev = dev->dev_private; 79 struct virtio_gpu_fpriv *vfpriv = file->driver_priv; 80 struct virtio_gpu_fence *out_fence; 81 int ret; 82 uint32_t *bo_handles = NULL; 83 void __user *user_bo_handles = NULL; 84 struct virtio_gpu_object_array *buflist = NULL; 85 struct sync_file *sync_file; 86 int in_fence_fd = exbuf->fence_fd; 87 int out_fence_fd = -1; 88 void *buf; 89 90 if (vgdev->has_virgl_3d == false) 91 return -ENOSYS; 92 93 if ((exbuf->flags & ~VIRTGPU_EXECBUF_FLAGS)) 94 return -EINVAL; 95 96 exbuf->fence_fd = -1; 97 98 virtio_gpu_create_context(dev, file); 99 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_IN) { 100 struct dma_fence *in_fence; 101 102 in_fence = sync_file_get_fence(in_fence_fd); 103 104 if (!in_fence) 105 return -EINVAL; 106 107 /* 108 * Wait if the fence is from a foreign context, or if the fence 109 * array contains any fence from a foreign context. 110 */ 111 ret = 0; 112 if (!dma_fence_match_context(in_fence, vgdev->fence_drv.context)) 113 ret = dma_fence_wait(in_fence, true); 114 115 dma_fence_put(in_fence); 116 if (ret) 117 return ret; 118 } 119 120 if (exbuf->flags & VIRTGPU_EXECBUF_FENCE_FD_OUT) { 121 out_fence_fd = get_unused_fd_flags(O_CLOEXEC); 122 if (out_fence_fd < 0) 123 return out_fence_fd; 124 } 125 126 if (exbuf->num_bo_handles) { 127 bo_handles = kvmalloc_array(exbuf->num_bo_handles, 128 sizeof(uint32_t), GFP_KERNEL); 129 if (!bo_handles) { 130 ret = -ENOMEM; 131 goto out_unused_fd; 132 } 133 134 user_bo_handles = u64_to_user_ptr(exbuf->bo_handles); 135 if (copy_from_user(bo_handles, user_bo_handles, 136 exbuf->num_bo_handles * sizeof(uint32_t))) { 137 ret = -EFAULT; 138 goto out_unused_fd; 139 } 140 141 buflist = virtio_gpu_array_from_handles(file, bo_handles, 142 exbuf->num_bo_handles); 143 if (!buflist) { 144 ret = -ENOENT; 145 goto out_unused_fd; 146 } 147 kvfree(bo_handles); 148 bo_handles = NULL; 149 } 150 151 buf = vmemdup_user(u64_to_user_ptr(exbuf->command), exbuf->size); 152 if (IS_ERR(buf)) { 153 ret = PTR_ERR(buf); 154 goto out_unused_fd; 155 } 156 157 if (buflist) { 158 ret = virtio_gpu_array_lock_resv(buflist); 159 if (ret) 160 goto out_memdup; 161 } 162 163 out_fence = virtio_gpu_fence_alloc(vgdev); 164 if(!out_fence) { 165 ret = -ENOMEM; 166 goto out_unresv; 167 } 168 169 if (out_fence_fd >= 0) { 170 sync_file = sync_file_create(&out_fence->f); 171 if (!sync_file) { 172 dma_fence_put(&out_fence->f); 173 ret = -ENOMEM; 174 goto out_memdup; 175 } 176 177 exbuf->fence_fd = out_fence_fd; 178 fd_install(out_fence_fd, sync_file->file); 179 } 180 181 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size, 182 vfpriv->ctx_id, buflist, out_fence); 183 virtio_gpu_notify(vgdev); 184 return 0; 185 186 out_unresv: 187 if (buflist) 188 virtio_gpu_array_unlock_resv(buflist); 189 out_memdup: 190 kvfree(buf); 191 out_unused_fd: 192 kvfree(bo_handles); 193 if (buflist) 194 virtio_gpu_array_put_free(buflist); 195 196 if (out_fence_fd >= 0) 197 put_unused_fd(out_fence_fd); 198 199 return ret; 200 } 201 202 static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data, 203 struct drm_file *file) 204 { 205 struct virtio_gpu_device *vgdev = dev->dev_private; 206 struct drm_virtgpu_getparam *param = data; 207 int value; 208 209 switch (param->param) { 210 case VIRTGPU_PARAM_3D_FEATURES: 211 value = vgdev->has_virgl_3d == true ? 1 : 0; 212 break; 213 case VIRTGPU_PARAM_CAPSET_QUERY_FIX: 214 value = 1; 215 break; 216 default: 217 return -EINVAL; 218 } 219 if (copy_to_user(u64_to_user_ptr(param->value), &value, sizeof(int))) 220 return -EFAULT; 221 222 return 0; 223 } 224 225 static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data, 226 struct drm_file *file) 227 { 228 struct virtio_gpu_device *vgdev = dev->dev_private; 229 struct drm_virtgpu_resource_create *rc = data; 230 struct virtio_gpu_fence *fence; 231 int ret; 232 struct virtio_gpu_object *qobj; 233 struct drm_gem_object *obj; 234 uint32_t handle = 0; 235 struct virtio_gpu_object_params params = { 0 }; 236 237 if (vgdev->has_virgl_3d) { 238 virtio_gpu_create_context(dev, file); 239 params.virgl = true; 240 params.target = rc->target; 241 params.bind = rc->bind; 242 params.depth = rc->depth; 243 params.array_size = rc->array_size; 244 params.last_level = rc->last_level; 245 params.nr_samples = rc->nr_samples; 246 params.flags = rc->flags; 247 } else { 248 if (rc->depth > 1) 249 return -EINVAL; 250 if (rc->nr_samples > 1) 251 return -EINVAL; 252 if (rc->last_level > 1) 253 return -EINVAL; 254 if (rc->target != 2) 255 return -EINVAL; 256 if (rc->array_size > 1) 257 return -EINVAL; 258 } 259 260 params.format = rc->format; 261 params.width = rc->width; 262 params.height = rc->height; 263 params.size = rc->size; 264 /* allocate a single page size object */ 265 if (params.size == 0) 266 params.size = PAGE_SIZE; 267 268 fence = virtio_gpu_fence_alloc(vgdev); 269 if (!fence) 270 return -ENOMEM; 271 ret = virtio_gpu_object_create(vgdev, ¶ms, &qobj, fence); 272 dma_fence_put(&fence->f); 273 if (ret < 0) 274 return ret; 275 obj = &qobj->base.base; 276 277 ret = drm_gem_handle_create(file, obj, &handle); 278 if (ret) { 279 drm_gem_object_release(obj); 280 return ret; 281 } 282 drm_gem_object_put_unlocked(obj); 283 284 rc->res_handle = qobj->hw_res_handle; /* similiar to a VM address */ 285 rc->bo_handle = handle; 286 return 0; 287 } 288 289 static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data, 290 struct drm_file *file) 291 { 292 struct drm_virtgpu_resource_info *ri = data; 293 struct drm_gem_object *gobj = NULL; 294 struct virtio_gpu_object *qobj = NULL; 295 296 gobj = drm_gem_object_lookup(file, ri->bo_handle); 297 if (gobj == NULL) 298 return -ENOENT; 299 300 qobj = gem_to_virtio_gpu_obj(gobj); 301 302 ri->size = qobj->base.base.size; 303 ri->res_handle = qobj->hw_res_handle; 304 drm_gem_object_put_unlocked(gobj); 305 return 0; 306 } 307 308 static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, 309 void *data, 310 struct drm_file *file) 311 { 312 struct virtio_gpu_device *vgdev = dev->dev_private; 313 struct virtio_gpu_fpriv *vfpriv = file->driver_priv; 314 struct drm_virtgpu_3d_transfer_from_host *args = data; 315 struct virtio_gpu_object_array *objs; 316 struct virtio_gpu_fence *fence; 317 int ret; 318 u32 offset = args->offset; 319 320 if (vgdev->has_virgl_3d == false) 321 return -ENOSYS; 322 323 virtio_gpu_create_context(dev, file); 324 objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1); 325 if (objs == NULL) 326 return -ENOENT; 327 328 ret = virtio_gpu_array_lock_resv(objs); 329 if (ret != 0) 330 goto err_put_free; 331 332 fence = virtio_gpu_fence_alloc(vgdev); 333 if (!fence) { 334 ret = -ENOMEM; 335 goto err_unlock; 336 } 337 virtio_gpu_cmd_transfer_from_host_3d 338 (vgdev, vfpriv->ctx_id, offset, args->level, 339 &args->box, objs, fence); 340 dma_fence_put(&fence->f); 341 virtio_gpu_notify(vgdev); 342 return 0; 343 344 err_unlock: 345 virtio_gpu_array_unlock_resv(objs); 346 err_put_free: 347 virtio_gpu_array_put_free(objs); 348 return ret; 349 } 350 351 static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, 352 struct drm_file *file) 353 { 354 struct virtio_gpu_device *vgdev = dev->dev_private; 355 struct virtio_gpu_fpriv *vfpriv = file->driver_priv; 356 struct drm_virtgpu_3d_transfer_to_host *args = data; 357 struct virtio_gpu_object_array *objs; 358 struct virtio_gpu_fence *fence; 359 int ret; 360 u32 offset = args->offset; 361 362 objs = virtio_gpu_array_from_handles(file, &args->bo_handle, 1); 363 if (objs == NULL) 364 return -ENOENT; 365 366 if (!vgdev->has_virgl_3d) { 367 virtio_gpu_cmd_transfer_to_host_2d 368 (vgdev, offset, 369 args->box.w, args->box.h, args->box.x, args->box.y, 370 objs, NULL); 371 } else { 372 virtio_gpu_create_context(dev, file); 373 ret = virtio_gpu_array_lock_resv(objs); 374 if (ret != 0) 375 goto err_put_free; 376 377 ret = -ENOMEM; 378 fence = virtio_gpu_fence_alloc(vgdev); 379 if (!fence) 380 goto err_unlock; 381 382 virtio_gpu_cmd_transfer_to_host_3d 383 (vgdev, 384 vfpriv ? vfpriv->ctx_id : 0, offset, 385 args->level, &args->box, objs, fence); 386 dma_fence_put(&fence->f); 387 } 388 virtio_gpu_notify(vgdev); 389 return 0; 390 391 err_unlock: 392 virtio_gpu_array_unlock_resv(objs); 393 err_put_free: 394 virtio_gpu_array_put_free(objs); 395 return ret; 396 } 397 398 static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data, 399 struct drm_file *file) 400 { 401 struct drm_virtgpu_3d_wait *args = data; 402 struct drm_gem_object *obj; 403 long timeout = 15 * HZ; 404 int ret; 405 406 obj = drm_gem_object_lookup(file, args->handle); 407 if (obj == NULL) 408 return -ENOENT; 409 410 if (args->flags & VIRTGPU_WAIT_NOWAIT) { 411 ret = dma_resv_test_signaled_rcu(obj->resv, true); 412 } else { 413 ret = dma_resv_wait_timeout_rcu(obj->resv, true, true, 414 timeout); 415 } 416 if (ret == 0) 417 ret = -EBUSY; 418 else if (ret > 0) 419 ret = 0; 420 421 drm_gem_object_put_unlocked(obj); 422 return ret; 423 } 424 425 static int virtio_gpu_get_caps_ioctl(struct drm_device *dev, 426 void *data, struct drm_file *file) 427 { 428 struct virtio_gpu_device *vgdev = dev->dev_private; 429 struct drm_virtgpu_get_caps *args = data; 430 unsigned size, host_caps_size; 431 int i; 432 int found_valid = -1; 433 int ret; 434 struct virtio_gpu_drv_cap_cache *cache_ent; 435 void *ptr; 436 437 if (vgdev->num_capsets == 0) 438 return -ENOSYS; 439 440 /* don't allow userspace to pass 0 */ 441 if (args->size == 0) 442 return -EINVAL; 443 444 spin_lock(&vgdev->display_info_lock); 445 for (i = 0; i < vgdev->num_capsets; i++) { 446 if (vgdev->capsets[i].id == args->cap_set_id) { 447 if (vgdev->capsets[i].max_version >= args->cap_set_ver) { 448 found_valid = i; 449 break; 450 } 451 } 452 } 453 454 if (found_valid == -1) { 455 spin_unlock(&vgdev->display_info_lock); 456 return -EINVAL; 457 } 458 459 host_caps_size = vgdev->capsets[found_valid].max_size; 460 /* only copy to user the minimum of the host caps size or the guest caps size */ 461 size = min(args->size, host_caps_size); 462 463 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) { 464 if (cache_ent->id == args->cap_set_id && 465 cache_ent->version == args->cap_set_ver) { 466 spin_unlock(&vgdev->display_info_lock); 467 goto copy_exit; 468 } 469 } 470 spin_unlock(&vgdev->display_info_lock); 471 472 /* not in cache - need to talk to hw */ 473 virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver, 474 &cache_ent); 475 virtio_gpu_notify(vgdev); 476 477 copy_exit: 478 ret = wait_event_timeout(vgdev->resp_wq, 479 atomic_read(&cache_ent->is_valid), 5 * HZ); 480 if (!ret) 481 return -EBUSY; 482 483 /* is_valid check must proceed before copy of the cache entry. */ 484 smp_rmb(); 485 486 ptr = cache_ent->caps_cache; 487 488 if (copy_to_user(u64_to_user_ptr(args->addr), ptr, size)) 489 return -EFAULT; 490 491 return 0; 492 } 493 494 struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = { 495 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl, 496 DRM_RENDER_ALLOW), 497 498 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl, 499 DRM_RENDER_ALLOW), 500 501 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl, 502 DRM_RENDER_ALLOW), 503 504 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE, 505 virtio_gpu_resource_create_ioctl, 506 DRM_RENDER_ALLOW), 507 508 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl, 509 DRM_RENDER_ALLOW), 510 511 /* make transfer async to the main ring? - no sure, can we 512 * thread these in the underlying GL 513 */ 514 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST, 515 virtio_gpu_transfer_from_host_ioctl, 516 DRM_RENDER_ALLOW), 517 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST, 518 virtio_gpu_transfer_to_host_ioctl, 519 DRM_RENDER_ALLOW), 520 521 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl, 522 DRM_RENDER_ALLOW), 523 524 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl, 525 DRM_RENDER_ALLOW), 526 }; 527