1 /* 2 * Copyright (C) 2015 Red Hat, Inc. 3 * All Rights Reserved. 4 * 5 * Authors: 6 * Dave Airlie 7 * Alon Levy 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 */ 27 28 #include <drm/drmP.h> 29 #include <drm/virtgpu_drm.h> 30 #include <drm/ttm/ttm_execbuf_util.h> 31 32 #include "virtgpu_drv.h" 33 34 static void convert_to_hw_box(struct virtio_gpu_box *dst, 35 const struct drm_virtgpu_3d_box *src) 36 { 37 dst->x = cpu_to_le32(src->x); 38 dst->y = cpu_to_le32(src->y); 39 dst->z = cpu_to_le32(src->z); 40 dst->w = cpu_to_le32(src->w); 41 dst->h = cpu_to_le32(src->h); 42 dst->d = cpu_to_le32(src->d); 43 } 44 45 static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data, 46 struct drm_file *file_priv) 47 { 48 struct virtio_gpu_device *vgdev = dev->dev_private; 49 struct drm_virtgpu_map *virtio_gpu_map = data; 50 51 return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev, 52 virtio_gpu_map->handle, 53 &virtio_gpu_map->offset); 54 } 55 56 static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket, 57 struct list_head *head) 58 { 59 struct ttm_operation_ctx ctx = { false, false }; 60 struct ttm_validate_buffer *buf; 61 struct ttm_buffer_object *bo; 62 struct virtio_gpu_object *qobj; 63 int ret; 64 65 ret = ttm_eu_reserve_buffers(ticket, head, true, NULL); 66 if (ret != 0) 67 return ret; 68 69 list_for_each_entry(buf, head, head) { 70 bo = buf->bo; 71 qobj = container_of(bo, struct virtio_gpu_object, tbo); 72 ret = ttm_bo_validate(bo, &qobj->placement, &ctx); 73 if (ret) { 74 ttm_eu_backoff_reservation(ticket, head); 75 return ret; 76 } 77 } 78 return 0; 79 } 80 81 static void virtio_gpu_unref_list(struct list_head *head) 82 { 83 struct ttm_validate_buffer *buf; 84 struct ttm_buffer_object *bo; 85 struct virtio_gpu_object *qobj; 86 list_for_each_entry(buf, head, head) { 87 bo = buf->bo; 88 qobj = container_of(bo, struct virtio_gpu_object, tbo); 89 90 drm_gem_object_put_unlocked(&qobj->gem_base); 91 } 92 } 93 94 /* 95 * Usage of execbuffer: 96 * Relocations need to take into account the full VIRTIO_GPUDrawable size. 97 * However, the command as passed from user space must *not* contain the initial 98 * VIRTIO_GPUReleaseInfo struct (first XXX bytes) 99 */ 100 static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data, 101 struct drm_file *drm_file) 102 { 103 struct drm_virtgpu_execbuffer *exbuf = data; 104 struct virtio_gpu_device *vgdev = dev->dev_private; 105 struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv; 106 struct drm_gem_object *gobj; 107 struct virtio_gpu_fence *fence; 108 struct virtio_gpu_object *qobj; 109 int ret; 110 uint32_t *bo_handles = NULL; 111 void __user *user_bo_handles = NULL; 112 struct list_head validate_list; 113 struct ttm_validate_buffer *buflist = NULL; 114 int i; 115 struct ww_acquire_ctx ticket; 116 void *buf; 117 118 if (vgdev->has_virgl_3d == false) 119 return -ENOSYS; 120 121 INIT_LIST_HEAD(&validate_list); 122 if (exbuf->num_bo_handles) { 123 124 bo_handles = kvmalloc_array(exbuf->num_bo_handles, 125 sizeof(uint32_t), GFP_KERNEL); 126 buflist = kvmalloc_array(exbuf->num_bo_handles, 127 sizeof(struct ttm_validate_buffer), 128 GFP_KERNEL | __GFP_ZERO); 129 if (!bo_handles || !buflist) { 130 kvfree(bo_handles); 131 kvfree(buflist); 132 return -ENOMEM; 133 } 134 135 user_bo_handles = (void __user *)(uintptr_t)exbuf->bo_handles; 136 if (copy_from_user(bo_handles, user_bo_handles, 137 exbuf->num_bo_handles * sizeof(uint32_t))) { 138 ret = -EFAULT; 139 kvfree(bo_handles); 140 kvfree(buflist); 141 return ret; 142 } 143 144 for (i = 0; i < exbuf->num_bo_handles; i++) { 145 gobj = drm_gem_object_lookup(drm_file, bo_handles[i]); 146 if (!gobj) { 147 kvfree(bo_handles); 148 kvfree(buflist); 149 return -ENOENT; 150 } 151 152 qobj = gem_to_virtio_gpu_obj(gobj); 153 buflist[i].bo = &qobj->tbo; 154 155 list_add(&buflist[i].head, &validate_list); 156 } 157 kvfree(bo_handles); 158 } 159 160 ret = virtio_gpu_object_list_validate(&ticket, &validate_list); 161 if (ret) 162 goto out_free; 163 164 buf = memdup_user((void __user *)(uintptr_t)exbuf->command, 165 exbuf->size); 166 if (IS_ERR(buf)) { 167 ret = PTR_ERR(buf); 168 goto out_unresv; 169 } 170 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size, 171 vfpriv->ctx_id, &fence); 172 173 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f); 174 175 /* fence the command bo */ 176 virtio_gpu_unref_list(&validate_list); 177 kvfree(buflist); 178 dma_fence_put(&fence->f); 179 return 0; 180 181 out_unresv: 182 ttm_eu_backoff_reservation(&ticket, &validate_list); 183 out_free: 184 virtio_gpu_unref_list(&validate_list); 185 kvfree(buflist); 186 return ret; 187 } 188 189 static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data, 190 struct drm_file *file_priv) 191 { 192 struct virtio_gpu_device *vgdev = dev->dev_private; 193 struct drm_virtgpu_getparam *param = data; 194 int value; 195 196 switch (param->param) { 197 case VIRTGPU_PARAM_3D_FEATURES: 198 value = vgdev->has_virgl_3d == true ? 1 : 0; 199 break; 200 default: 201 return -EINVAL; 202 } 203 if (copy_to_user((void __user *)(unsigned long)param->value, 204 &value, sizeof(int))) { 205 return -EFAULT; 206 } 207 return 0; 208 } 209 210 static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data, 211 struct drm_file *file_priv) 212 { 213 struct virtio_gpu_device *vgdev = dev->dev_private; 214 struct drm_virtgpu_resource_create *rc = data; 215 int ret; 216 uint32_t res_id; 217 struct virtio_gpu_object *qobj; 218 struct drm_gem_object *obj; 219 uint32_t handle = 0; 220 uint32_t size; 221 struct list_head validate_list; 222 struct ttm_validate_buffer mainbuf; 223 struct virtio_gpu_fence *fence = NULL; 224 struct ww_acquire_ctx ticket; 225 struct virtio_gpu_resource_create_3d rc_3d; 226 227 if (vgdev->has_virgl_3d == false) { 228 if (rc->depth > 1) 229 return -EINVAL; 230 if (rc->nr_samples > 1) 231 return -EINVAL; 232 if (rc->last_level > 1) 233 return -EINVAL; 234 if (rc->target != 2) 235 return -EINVAL; 236 if (rc->array_size > 1) 237 return -EINVAL; 238 } 239 240 INIT_LIST_HEAD(&validate_list); 241 memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer)); 242 243 virtio_gpu_resource_id_get(vgdev, &res_id); 244 245 size = rc->size; 246 247 /* allocate a single page size object */ 248 if (size == 0) 249 size = PAGE_SIZE; 250 251 qobj = virtio_gpu_alloc_object(dev, size, false, false); 252 if (IS_ERR(qobj)) { 253 ret = PTR_ERR(qobj); 254 goto fail_id; 255 } 256 obj = &qobj->gem_base; 257 258 if (!vgdev->has_virgl_3d) { 259 virtio_gpu_cmd_create_resource(vgdev, res_id, rc->format, 260 rc->width, rc->height); 261 262 ret = virtio_gpu_object_attach(vgdev, qobj, res_id, NULL); 263 } else { 264 /* use a gem reference since unref list undoes them */ 265 drm_gem_object_get(&qobj->gem_base); 266 mainbuf.bo = &qobj->tbo; 267 list_add(&mainbuf.head, &validate_list); 268 269 ret = virtio_gpu_object_list_validate(&ticket, &validate_list); 270 if (ret) { 271 DRM_DEBUG("failed to validate\n"); 272 goto fail_unref; 273 } 274 275 rc_3d.resource_id = cpu_to_le32(res_id); 276 rc_3d.target = cpu_to_le32(rc->target); 277 rc_3d.format = cpu_to_le32(rc->format); 278 rc_3d.bind = cpu_to_le32(rc->bind); 279 rc_3d.width = cpu_to_le32(rc->width); 280 rc_3d.height = cpu_to_le32(rc->height); 281 rc_3d.depth = cpu_to_le32(rc->depth); 282 rc_3d.array_size = cpu_to_le32(rc->array_size); 283 rc_3d.last_level = cpu_to_le32(rc->last_level); 284 rc_3d.nr_samples = cpu_to_le32(rc->nr_samples); 285 rc_3d.flags = cpu_to_le32(rc->flags); 286 287 virtio_gpu_cmd_resource_create_3d(vgdev, &rc_3d, NULL); 288 ret = virtio_gpu_object_attach(vgdev, qobj, res_id, &fence); 289 if (ret) { 290 ttm_eu_backoff_reservation(&ticket, &validate_list); 291 goto fail_unref; 292 } 293 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f); 294 } 295 296 qobj->hw_res_handle = res_id; 297 298 ret = drm_gem_handle_create(file_priv, obj, &handle); 299 if (ret) { 300 301 drm_gem_object_release(obj); 302 if (vgdev->has_virgl_3d) { 303 virtio_gpu_unref_list(&validate_list); 304 dma_fence_put(&fence->f); 305 } 306 return ret; 307 } 308 drm_gem_object_put_unlocked(obj); 309 310 rc->res_handle = res_id; /* similiar to a VM address */ 311 rc->bo_handle = handle; 312 313 if (vgdev->has_virgl_3d) { 314 virtio_gpu_unref_list(&validate_list); 315 dma_fence_put(&fence->f); 316 } 317 return 0; 318 fail_unref: 319 if (vgdev->has_virgl_3d) { 320 virtio_gpu_unref_list(&validate_list); 321 dma_fence_put(&fence->f); 322 } 323 //fail_obj: 324 // drm_gem_object_handle_unreference_unlocked(obj); 325 fail_id: 326 virtio_gpu_resource_id_put(vgdev, res_id); 327 return ret; 328 } 329 330 static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data, 331 struct drm_file *file_priv) 332 { 333 struct drm_virtgpu_resource_info *ri = data; 334 struct drm_gem_object *gobj = NULL; 335 struct virtio_gpu_object *qobj = NULL; 336 337 gobj = drm_gem_object_lookup(file_priv, ri->bo_handle); 338 if (gobj == NULL) 339 return -ENOENT; 340 341 qobj = gem_to_virtio_gpu_obj(gobj); 342 343 ri->size = qobj->gem_base.size; 344 ri->res_handle = qobj->hw_res_handle; 345 drm_gem_object_put_unlocked(gobj); 346 return 0; 347 } 348 349 static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, 350 void *data, 351 struct drm_file *file) 352 { 353 struct virtio_gpu_device *vgdev = dev->dev_private; 354 struct virtio_gpu_fpriv *vfpriv = file->driver_priv; 355 struct drm_virtgpu_3d_transfer_from_host *args = data; 356 struct ttm_operation_ctx ctx = { true, false }; 357 struct drm_gem_object *gobj = NULL; 358 struct virtio_gpu_object *qobj = NULL; 359 struct virtio_gpu_fence *fence; 360 int ret; 361 u32 offset = args->offset; 362 struct virtio_gpu_box box; 363 364 if (vgdev->has_virgl_3d == false) 365 return -ENOSYS; 366 367 gobj = drm_gem_object_lookup(file, args->bo_handle); 368 if (gobj == NULL) 369 return -ENOENT; 370 371 qobj = gem_to_virtio_gpu_obj(gobj); 372 373 ret = virtio_gpu_object_reserve(qobj, false); 374 if (ret) 375 goto out; 376 377 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); 378 if (unlikely(ret)) 379 goto out_unres; 380 381 convert_to_hw_box(&box, &args->box); 382 virtio_gpu_cmd_transfer_from_host_3d 383 (vgdev, qobj->hw_res_handle, 384 vfpriv->ctx_id, offset, args->level, 385 &box, &fence); 386 reservation_object_add_excl_fence(qobj->tbo.resv, 387 &fence->f); 388 389 dma_fence_put(&fence->f); 390 out_unres: 391 virtio_gpu_object_unreserve(qobj); 392 out: 393 drm_gem_object_put_unlocked(gobj); 394 return ret; 395 } 396 397 static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, 398 struct drm_file *file) 399 { 400 struct virtio_gpu_device *vgdev = dev->dev_private; 401 struct virtio_gpu_fpriv *vfpriv = file->driver_priv; 402 struct drm_virtgpu_3d_transfer_to_host *args = data; 403 struct ttm_operation_ctx ctx = { true, false }; 404 struct drm_gem_object *gobj = NULL; 405 struct virtio_gpu_object *qobj = NULL; 406 struct virtio_gpu_fence *fence; 407 struct virtio_gpu_box box; 408 int ret; 409 u32 offset = args->offset; 410 411 gobj = drm_gem_object_lookup(file, args->bo_handle); 412 if (gobj == NULL) 413 return -ENOENT; 414 415 qobj = gem_to_virtio_gpu_obj(gobj); 416 417 ret = virtio_gpu_object_reserve(qobj, false); 418 if (ret) 419 goto out; 420 421 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); 422 if (unlikely(ret)) 423 goto out_unres; 424 425 convert_to_hw_box(&box, &args->box); 426 if (!vgdev->has_virgl_3d) { 427 virtio_gpu_cmd_transfer_to_host_2d 428 (vgdev, qobj->hw_res_handle, offset, 429 box.w, box.h, box.x, box.y, NULL); 430 } else { 431 virtio_gpu_cmd_transfer_to_host_3d 432 (vgdev, qobj->hw_res_handle, 433 vfpriv ? vfpriv->ctx_id : 0, offset, 434 args->level, &box, &fence); 435 reservation_object_add_excl_fence(qobj->tbo.resv, 436 &fence->f); 437 dma_fence_put(&fence->f); 438 } 439 440 out_unres: 441 virtio_gpu_object_unreserve(qobj); 442 out: 443 drm_gem_object_put_unlocked(gobj); 444 return ret; 445 } 446 447 static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data, 448 struct drm_file *file) 449 { 450 struct drm_virtgpu_3d_wait *args = data; 451 struct drm_gem_object *gobj = NULL; 452 struct virtio_gpu_object *qobj = NULL; 453 int ret; 454 bool nowait = false; 455 456 gobj = drm_gem_object_lookup(file, args->handle); 457 if (gobj == NULL) 458 return -ENOENT; 459 460 qobj = gem_to_virtio_gpu_obj(gobj); 461 462 if (args->flags & VIRTGPU_WAIT_NOWAIT) 463 nowait = true; 464 ret = virtio_gpu_object_wait(qobj, nowait); 465 466 drm_gem_object_put_unlocked(gobj); 467 return ret; 468 } 469 470 static int virtio_gpu_get_caps_ioctl(struct drm_device *dev, 471 void *data, struct drm_file *file) 472 { 473 struct virtio_gpu_device *vgdev = dev->dev_private; 474 struct drm_virtgpu_get_caps *args = data; 475 int size; 476 int i; 477 int found_valid = -1; 478 int ret; 479 struct virtio_gpu_drv_cap_cache *cache_ent; 480 void *ptr; 481 if (vgdev->num_capsets == 0) 482 return -ENOSYS; 483 484 spin_lock(&vgdev->display_info_lock); 485 for (i = 0; i < vgdev->num_capsets; i++) { 486 if (vgdev->capsets[i].id == args->cap_set_id) { 487 if (vgdev->capsets[i].max_version >= args->cap_set_ver) { 488 found_valid = i; 489 break; 490 } 491 } 492 } 493 494 if (found_valid == -1) { 495 spin_unlock(&vgdev->display_info_lock); 496 return -EINVAL; 497 } 498 499 size = vgdev->capsets[found_valid].max_size; 500 if (args->size > size) { 501 spin_unlock(&vgdev->display_info_lock); 502 return -EINVAL; 503 } 504 505 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) { 506 if (cache_ent->id == args->cap_set_id && 507 cache_ent->version == args->cap_set_ver) { 508 ptr = cache_ent->caps_cache; 509 spin_unlock(&vgdev->display_info_lock); 510 goto copy_exit; 511 } 512 } 513 spin_unlock(&vgdev->display_info_lock); 514 515 /* not in cache - need to talk to hw */ 516 virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver, 517 &cache_ent); 518 519 ret = wait_event_timeout(vgdev->resp_wq, 520 atomic_read(&cache_ent->is_valid), 5 * HZ); 521 522 ptr = cache_ent->caps_cache; 523 524 copy_exit: 525 if (copy_to_user((void __user *)(unsigned long)args->addr, ptr, size)) 526 return -EFAULT; 527 528 return 0; 529 } 530 531 struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = { 532 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl, 533 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 534 535 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl, 536 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 537 538 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl, 539 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 540 541 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE, 542 virtio_gpu_resource_create_ioctl, 543 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 544 545 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl, 546 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 547 548 /* make transfer async to the main ring? - no sure, can we 549 thread these in the underlying GL */ 550 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST, 551 virtio_gpu_transfer_from_host_ioctl, 552 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 553 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST, 554 virtio_gpu_transfer_to_host_ioctl, 555 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 556 557 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl, 558 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 559 560 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl, 561 DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW), 562 }; 563