1 /* 2 * Copyright (C) 2015 Red Hat, Inc. 3 * All Rights Reserved. 4 * 5 * Authors: 6 * Dave Airlie 7 * Alon Levy 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a 10 * copy of this software and associated documentation files (the "Software"), 11 * to deal in the Software without restriction, including without limitation 12 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the 14 * Software is furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 */ 27 28 #include <drm/drmP.h> 29 #include <drm/virtgpu_drm.h> 30 #include <drm/ttm/ttm_execbuf_util.h> 31 32 #include "virtgpu_drv.h" 33 34 static void convert_to_hw_box(struct virtio_gpu_box *dst, 35 const struct drm_virtgpu_3d_box *src) 36 { 37 dst->x = cpu_to_le32(src->x); 38 dst->y = cpu_to_le32(src->y); 39 dst->z = cpu_to_le32(src->z); 40 dst->w = cpu_to_le32(src->w); 41 dst->h = cpu_to_le32(src->h); 42 dst->d = cpu_to_le32(src->d); 43 } 44 45 static int virtio_gpu_map_ioctl(struct drm_device *dev, void *data, 46 struct drm_file *file_priv) 47 { 48 struct virtio_gpu_device *vgdev = dev->dev_private; 49 struct drm_virtgpu_map *virtio_gpu_map = data; 50 51 return virtio_gpu_mode_dumb_mmap(file_priv, vgdev->ddev, 52 virtio_gpu_map->handle, 53 &virtio_gpu_map->offset); 54 } 55 56 static int virtio_gpu_object_list_validate(struct ww_acquire_ctx *ticket, 57 struct list_head *head) 58 { 59 struct ttm_operation_ctx ctx = { false, false }; 60 struct ttm_validate_buffer *buf; 61 struct ttm_buffer_object *bo; 62 struct virtio_gpu_object *qobj; 63 int ret; 64 65 ret = ttm_eu_reserve_buffers(ticket, head, true, NULL); 66 if (ret != 0) 67 return ret; 68 69 list_for_each_entry(buf, head, head) { 70 bo = buf->bo; 71 qobj = container_of(bo, struct virtio_gpu_object, tbo); 72 ret = ttm_bo_validate(bo, &qobj->placement, &ctx); 73 if (ret) { 74 ttm_eu_backoff_reservation(ticket, head); 75 return ret; 76 } 77 } 78 return 0; 79 } 80 81 static void virtio_gpu_unref_list(struct list_head *head) 82 { 83 struct ttm_validate_buffer *buf; 84 struct ttm_buffer_object *bo; 85 struct virtio_gpu_object *qobj; 86 87 list_for_each_entry(buf, head, head) { 88 bo = buf->bo; 89 qobj = container_of(bo, struct virtio_gpu_object, tbo); 90 91 drm_gem_object_put_unlocked(&qobj->gem_base); 92 } 93 } 94 95 /* 96 * Usage of execbuffer: 97 * Relocations need to take into account the full VIRTIO_GPUDrawable size. 98 * However, the command as passed from user space must *not* contain the initial 99 * VIRTIO_GPUReleaseInfo struct (first XXX bytes) 100 */ 101 static int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data, 102 struct drm_file *drm_file) 103 { 104 struct drm_virtgpu_execbuffer *exbuf = data; 105 struct virtio_gpu_device *vgdev = dev->dev_private; 106 struct virtio_gpu_fpriv *vfpriv = drm_file->driver_priv; 107 struct drm_gem_object *gobj; 108 struct virtio_gpu_fence *fence; 109 struct virtio_gpu_object *qobj; 110 int ret; 111 uint32_t *bo_handles = NULL; 112 void __user *user_bo_handles = NULL; 113 struct list_head validate_list; 114 struct ttm_validate_buffer *buflist = NULL; 115 int i; 116 struct ww_acquire_ctx ticket; 117 void *buf; 118 119 if (vgdev->has_virgl_3d == false) 120 return -ENOSYS; 121 122 INIT_LIST_HEAD(&validate_list); 123 if (exbuf->num_bo_handles) { 124 125 bo_handles = kvmalloc_array(exbuf->num_bo_handles, 126 sizeof(uint32_t), GFP_KERNEL); 127 buflist = kvmalloc_array(exbuf->num_bo_handles, 128 sizeof(struct ttm_validate_buffer), 129 GFP_KERNEL | __GFP_ZERO); 130 if (!bo_handles || !buflist) { 131 kvfree(bo_handles); 132 kvfree(buflist); 133 return -ENOMEM; 134 } 135 136 user_bo_handles = (void __user *)(uintptr_t)exbuf->bo_handles; 137 if (copy_from_user(bo_handles, user_bo_handles, 138 exbuf->num_bo_handles * sizeof(uint32_t))) { 139 ret = -EFAULT; 140 kvfree(bo_handles); 141 kvfree(buflist); 142 return ret; 143 } 144 145 for (i = 0; i < exbuf->num_bo_handles; i++) { 146 gobj = drm_gem_object_lookup(drm_file, bo_handles[i]); 147 if (!gobj) { 148 kvfree(bo_handles); 149 kvfree(buflist); 150 return -ENOENT; 151 } 152 153 qobj = gem_to_virtio_gpu_obj(gobj); 154 buflist[i].bo = &qobj->tbo; 155 156 list_add(&buflist[i].head, &validate_list); 157 } 158 kvfree(bo_handles); 159 } 160 161 ret = virtio_gpu_object_list_validate(&ticket, &validate_list); 162 if (ret) 163 goto out_free; 164 165 buf = memdup_user((void __user *)(uintptr_t)exbuf->command, 166 exbuf->size); 167 if (IS_ERR(buf)) { 168 ret = PTR_ERR(buf); 169 goto out_unresv; 170 } 171 virtio_gpu_cmd_submit(vgdev, buf, exbuf->size, 172 vfpriv->ctx_id, &fence); 173 174 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f); 175 176 /* fence the command bo */ 177 virtio_gpu_unref_list(&validate_list); 178 kvfree(buflist); 179 dma_fence_put(&fence->f); 180 return 0; 181 182 out_unresv: 183 ttm_eu_backoff_reservation(&ticket, &validate_list); 184 out_free: 185 virtio_gpu_unref_list(&validate_list); 186 kvfree(buflist); 187 return ret; 188 } 189 190 static int virtio_gpu_getparam_ioctl(struct drm_device *dev, void *data, 191 struct drm_file *file_priv) 192 { 193 struct virtio_gpu_device *vgdev = dev->dev_private; 194 struct drm_virtgpu_getparam *param = data; 195 int value; 196 197 switch (param->param) { 198 case VIRTGPU_PARAM_3D_FEATURES: 199 value = vgdev->has_virgl_3d == true ? 1 : 0; 200 break; 201 default: 202 return -EINVAL; 203 } 204 if (copy_to_user((void __user *)(unsigned long)param->value, 205 &value, sizeof(int))) { 206 return -EFAULT; 207 } 208 return 0; 209 } 210 211 static int virtio_gpu_resource_create_ioctl(struct drm_device *dev, void *data, 212 struct drm_file *file_priv) 213 { 214 struct virtio_gpu_device *vgdev = dev->dev_private; 215 struct drm_virtgpu_resource_create *rc = data; 216 int ret; 217 uint32_t res_id; 218 struct virtio_gpu_object *qobj; 219 struct drm_gem_object *obj; 220 uint32_t handle = 0; 221 uint32_t size; 222 struct list_head validate_list; 223 struct ttm_validate_buffer mainbuf; 224 struct virtio_gpu_fence *fence = NULL; 225 struct ww_acquire_ctx ticket; 226 struct virtio_gpu_resource_create_3d rc_3d; 227 228 if (vgdev->has_virgl_3d == false) { 229 if (rc->depth > 1) 230 return -EINVAL; 231 if (rc->nr_samples > 1) 232 return -EINVAL; 233 if (rc->last_level > 1) 234 return -EINVAL; 235 if (rc->target != 2) 236 return -EINVAL; 237 if (rc->array_size > 1) 238 return -EINVAL; 239 } 240 241 INIT_LIST_HEAD(&validate_list); 242 memset(&mainbuf, 0, sizeof(struct ttm_validate_buffer)); 243 244 virtio_gpu_resource_id_get(vgdev, &res_id); 245 246 size = rc->size; 247 248 /* allocate a single page size object */ 249 if (size == 0) 250 size = PAGE_SIZE; 251 252 qobj = virtio_gpu_alloc_object(dev, size, false, false); 253 if (IS_ERR(qobj)) { 254 ret = PTR_ERR(qobj); 255 goto fail_id; 256 } 257 obj = &qobj->gem_base; 258 259 if (!vgdev->has_virgl_3d) { 260 virtio_gpu_cmd_create_resource(vgdev, res_id, rc->format, 261 rc->width, rc->height); 262 263 ret = virtio_gpu_object_attach(vgdev, qobj, res_id, NULL); 264 } else { 265 /* use a gem reference since unref list undoes them */ 266 drm_gem_object_get(&qobj->gem_base); 267 mainbuf.bo = &qobj->tbo; 268 list_add(&mainbuf.head, &validate_list); 269 270 ret = virtio_gpu_object_list_validate(&ticket, &validate_list); 271 if (ret) { 272 DRM_DEBUG("failed to validate\n"); 273 goto fail_unref; 274 } 275 276 rc_3d.resource_id = cpu_to_le32(res_id); 277 rc_3d.target = cpu_to_le32(rc->target); 278 rc_3d.format = cpu_to_le32(rc->format); 279 rc_3d.bind = cpu_to_le32(rc->bind); 280 rc_3d.width = cpu_to_le32(rc->width); 281 rc_3d.height = cpu_to_le32(rc->height); 282 rc_3d.depth = cpu_to_le32(rc->depth); 283 rc_3d.array_size = cpu_to_le32(rc->array_size); 284 rc_3d.last_level = cpu_to_le32(rc->last_level); 285 rc_3d.nr_samples = cpu_to_le32(rc->nr_samples); 286 rc_3d.flags = cpu_to_le32(rc->flags); 287 288 virtio_gpu_cmd_resource_create_3d(vgdev, &rc_3d, NULL); 289 ret = virtio_gpu_object_attach(vgdev, qobj, res_id, &fence); 290 if (ret) { 291 ttm_eu_backoff_reservation(&ticket, &validate_list); 292 goto fail_unref; 293 } 294 ttm_eu_fence_buffer_objects(&ticket, &validate_list, &fence->f); 295 } 296 297 qobj->hw_res_handle = res_id; 298 299 ret = drm_gem_handle_create(file_priv, obj, &handle); 300 if (ret) { 301 302 drm_gem_object_release(obj); 303 if (vgdev->has_virgl_3d) { 304 virtio_gpu_unref_list(&validate_list); 305 dma_fence_put(&fence->f); 306 } 307 return ret; 308 } 309 drm_gem_object_put_unlocked(obj); 310 311 rc->res_handle = res_id; /* similiar to a VM address */ 312 rc->bo_handle = handle; 313 314 if (vgdev->has_virgl_3d) { 315 virtio_gpu_unref_list(&validate_list); 316 dma_fence_put(&fence->f); 317 } 318 return 0; 319 fail_unref: 320 if (vgdev->has_virgl_3d) { 321 virtio_gpu_unref_list(&validate_list); 322 dma_fence_put(&fence->f); 323 } 324 //fail_obj: 325 // drm_gem_object_handle_unreference_unlocked(obj); 326 fail_id: 327 virtio_gpu_resource_id_put(vgdev, res_id); 328 return ret; 329 } 330 331 static int virtio_gpu_resource_info_ioctl(struct drm_device *dev, void *data, 332 struct drm_file *file_priv) 333 { 334 struct drm_virtgpu_resource_info *ri = data; 335 struct drm_gem_object *gobj = NULL; 336 struct virtio_gpu_object *qobj = NULL; 337 338 gobj = drm_gem_object_lookup(file_priv, ri->bo_handle); 339 if (gobj == NULL) 340 return -ENOENT; 341 342 qobj = gem_to_virtio_gpu_obj(gobj); 343 344 ri->size = qobj->gem_base.size; 345 ri->res_handle = qobj->hw_res_handle; 346 drm_gem_object_put_unlocked(gobj); 347 return 0; 348 } 349 350 static int virtio_gpu_transfer_from_host_ioctl(struct drm_device *dev, 351 void *data, 352 struct drm_file *file) 353 { 354 struct virtio_gpu_device *vgdev = dev->dev_private; 355 struct virtio_gpu_fpriv *vfpriv = file->driver_priv; 356 struct drm_virtgpu_3d_transfer_from_host *args = data; 357 struct ttm_operation_ctx ctx = { true, false }; 358 struct drm_gem_object *gobj = NULL; 359 struct virtio_gpu_object *qobj = NULL; 360 struct virtio_gpu_fence *fence; 361 int ret; 362 u32 offset = args->offset; 363 struct virtio_gpu_box box; 364 365 if (vgdev->has_virgl_3d == false) 366 return -ENOSYS; 367 368 gobj = drm_gem_object_lookup(file, args->bo_handle); 369 if (gobj == NULL) 370 return -ENOENT; 371 372 qobj = gem_to_virtio_gpu_obj(gobj); 373 374 ret = virtio_gpu_object_reserve(qobj, false); 375 if (ret) 376 goto out; 377 378 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); 379 if (unlikely(ret)) 380 goto out_unres; 381 382 convert_to_hw_box(&box, &args->box); 383 virtio_gpu_cmd_transfer_from_host_3d 384 (vgdev, qobj->hw_res_handle, 385 vfpriv->ctx_id, offset, args->level, 386 &box, &fence); 387 reservation_object_add_excl_fence(qobj->tbo.resv, 388 &fence->f); 389 390 dma_fence_put(&fence->f); 391 out_unres: 392 virtio_gpu_object_unreserve(qobj); 393 out: 394 drm_gem_object_put_unlocked(gobj); 395 return ret; 396 } 397 398 static int virtio_gpu_transfer_to_host_ioctl(struct drm_device *dev, void *data, 399 struct drm_file *file) 400 { 401 struct virtio_gpu_device *vgdev = dev->dev_private; 402 struct virtio_gpu_fpriv *vfpriv = file->driver_priv; 403 struct drm_virtgpu_3d_transfer_to_host *args = data; 404 struct ttm_operation_ctx ctx = { true, false }; 405 struct drm_gem_object *gobj = NULL; 406 struct virtio_gpu_object *qobj = NULL; 407 struct virtio_gpu_fence *fence; 408 struct virtio_gpu_box box; 409 int ret; 410 u32 offset = args->offset; 411 412 gobj = drm_gem_object_lookup(file, args->bo_handle); 413 if (gobj == NULL) 414 return -ENOENT; 415 416 qobj = gem_to_virtio_gpu_obj(gobj); 417 418 ret = virtio_gpu_object_reserve(qobj, false); 419 if (ret) 420 goto out; 421 422 ret = ttm_bo_validate(&qobj->tbo, &qobj->placement, &ctx); 423 if (unlikely(ret)) 424 goto out_unres; 425 426 convert_to_hw_box(&box, &args->box); 427 if (!vgdev->has_virgl_3d) { 428 virtio_gpu_cmd_transfer_to_host_2d 429 (vgdev, qobj->hw_res_handle, offset, 430 box.w, box.h, box.x, box.y, NULL); 431 } else { 432 virtio_gpu_cmd_transfer_to_host_3d 433 (vgdev, qobj->hw_res_handle, 434 vfpriv ? vfpriv->ctx_id : 0, offset, 435 args->level, &box, &fence); 436 reservation_object_add_excl_fence(qobj->tbo.resv, 437 &fence->f); 438 dma_fence_put(&fence->f); 439 } 440 441 out_unres: 442 virtio_gpu_object_unreserve(qobj); 443 out: 444 drm_gem_object_put_unlocked(gobj); 445 return ret; 446 } 447 448 static int virtio_gpu_wait_ioctl(struct drm_device *dev, void *data, 449 struct drm_file *file) 450 { 451 struct drm_virtgpu_3d_wait *args = data; 452 struct drm_gem_object *gobj = NULL; 453 struct virtio_gpu_object *qobj = NULL; 454 int ret; 455 bool nowait = false; 456 457 gobj = drm_gem_object_lookup(file, args->handle); 458 if (gobj == NULL) 459 return -ENOENT; 460 461 qobj = gem_to_virtio_gpu_obj(gobj); 462 463 if (args->flags & VIRTGPU_WAIT_NOWAIT) 464 nowait = true; 465 ret = virtio_gpu_object_wait(qobj, nowait); 466 467 drm_gem_object_put_unlocked(gobj); 468 return ret; 469 } 470 471 static int virtio_gpu_get_caps_ioctl(struct drm_device *dev, 472 void *data, struct drm_file *file) 473 { 474 struct virtio_gpu_device *vgdev = dev->dev_private; 475 struct drm_virtgpu_get_caps *args = data; 476 int size; 477 int i; 478 int found_valid = -1; 479 int ret; 480 struct virtio_gpu_drv_cap_cache *cache_ent; 481 void *ptr; 482 483 if (vgdev->num_capsets == 0) 484 return -ENOSYS; 485 486 spin_lock(&vgdev->display_info_lock); 487 for (i = 0; i < vgdev->num_capsets; i++) { 488 if (vgdev->capsets[i].id == args->cap_set_id) { 489 if (vgdev->capsets[i].max_version >= args->cap_set_ver) { 490 found_valid = i; 491 break; 492 } 493 } 494 } 495 496 if (found_valid == -1) { 497 spin_unlock(&vgdev->display_info_lock); 498 return -EINVAL; 499 } 500 501 size = vgdev->capsets[found_valid].max_size; 502 if (args->size > size) { 503 spin_unlock(&vgdev->display_info_lock); 504 return -EINVAL; 505 } 506 507 list_for_each_entry(cache_ent, &vgdev->cap_cache, head) { 508 if (cache_ent->id == args->cap_set_id && 509 cache_ent->version == args->cap_set_ver) { 510 ptr = cache_ent->caps_cache; 511 spin_unlock(&vgdev->display_info_lock); 512 goto copy_exit; 513 } 514 } 515 spin_unlock(&vgdev->display_info_lock); 516 517 /* not in cache - need to talk to hw */ 518 virtio_gpu_cmd_get_capset(vgdev, found_valid, args->cap_set_ver, 519 &cache_ent); 520 521 ret = wait_event_timeout(vgdev->resp_wq, 522 atomic_read(&cache_ent->is_valid), 5 * HZ); 523 if (!ret) 524 return -EBUSY; 525 526 ptr = cache_ent->caps_cache; 527 528 copy_exit: 529 if (copy_to_user((void __user *)(unsigned long)args->addr, ptr, size)) 530 return -EFAULT; 531 532 return 0; 533 } 534 535 struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS] = { 536 DRM_IOCTL_DEF_DRV(VIRTGPU_MAP, virtio_gpu_map_ioctl, 537 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 538 539 DRM_IOCTL_DEF_DRV(VIRTGPU_EXECBUFFER, virtio_gpu_execbuffer_ioctl, 540 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 541 542 DRM_IOCTL_DEF_DRV(VIRTGPU_GETPARAM, virtio_gpu_getparam_ioctl, 543 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 544 545 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_CREATE, 546 virtio_gpu_resource_create_ioctl, 547 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 548 549 DRM_IOCTL_DEF_DRV(VIRTGPU_RESOURCE_INFO, virtio_gpu_resource_info_ioctl, 550 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 551 552 /* make transfer async to the main ring? - no sure, can we 553 * thread these in the underlying GL 554 */ 555 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_FROM_HOST, 556 virtio_gpu_transfer_from_host_ioctl, 557 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 558 DRM_IOCTL_DEF_DRV(VIRTGPU_TRANSFER_TO_HOST, 559 virtio_gpu_transfer_to_host_ioctl, 560 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 561 562 DRM_IOCTL_DEF_DRV(VIRTGPU_WAIT, virtio_gpu_wait_ioctl, 563 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 564 565 DRM_IOCTL_DEF_DRV(VIRTGPU_GET_CAPS, virtio_gpu_get_caps_ioctl, 566 DRM_AUTH | DRM_UNLOCKED | DRM_RENDER_ALLOW), 567 }; 568