1 /* 2 * Copyright (C) 2016 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License version 2 as published by 6 * the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 /** 18 * DOC: VC4 SDTV module 19 * 20 * The VEC encoder generates PAL or NTSC composite video output. 21 * 22 * TV mode selection is done by an atomic property on the encoder, 23 * because a drm_mode_modeinfo is insufficient to distinguish between 24 * PAL and PAL-M or NTSC and NTSC-J. 25 */ 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_panel.h> 30 #include <drm/drm_probe_helper.h> 31 #include <linux/clk.h> 32 #include <linux/component.h> 33 #include <linux/of_graph.h> 34 #include <linux/of_platform.h> 35 #include <linux/pm_runtime.h> 36 37 #include "vc4_drv.h" 38 #include "vc4_regs.h" 39 40 /* WSE Registers */ 41 #define VEC_WSE_RESET 0xc0 42 43 #define VEC_WSE_CONTROL 0xc4 44 #define VEC_WSE_WSS_ENABLE BIT(7) 45 46 #define VEC_WSE_WSS_DATA 0xc8 47 #define VEC_WSE_VPS_DATA1 0xcc 48 #define VEC_WSE_VPS_CONTROL 0xd0 49 50 /* VEC Registers */ 51 #define VEC_REVID 0x100 52 53 #define VEC_CONFIG0 0x104 54 #define VEC_CONFIG0_YDEL_MASK GENMASK(28, 26) 55 #define VEC_CONFIG0_YDEL(x) ((x) << 26) 56 #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) 57 #define VEC_CONFIG0_CDEL(x) ((x) << 24) 58 #define VEC_CONFIG0_PBPR_FIL BIT(18) 59 #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) 60 #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) 61 #define VEC_CONFIG0_CHROMA_GAIN_1_32 (1 << 16) 62 #define VEC_CONFIG0_CHROMA_GAIN_1_16 (2 << 16) 63 #define VEC_CONFIG0_CHROMA_GAIN_1_8 (3 << 16) 64 #define VEC_CONFIG0_CBURST_GAIN_MASK GENMASK(14, 13) 65 #define VEC_CONFIG0_CBURST_GAIN_UNITY (0 << 13) 66 #define VEC_CONFIG0_CBURST_GAIN_1_128 (1 << 13) 67 #define VEC_CONFIG0_CBURST_GAIN_1_64 (2 << 13) 68 #define VEC_CONFIG0_CBURST_GAIN_1_32 (3 << 13) 69 #define VEC_CONFIG0_CHRBW1 BIT(11) 70 #define VEC_CONFIG0_CHRBW0 BIT(10) 71 #define VEC_CONFIG0_SYNCDIS BIT(9) 72 #define VEC_CONFIG0_BURDIS BIT(8) 73 #define VEC_CONFIG0_CHRDIS BIT(7) 74 #define VEC_CONFIG0_PDEN BIT(6) 75 #define VEC_CONFIG0_YCDELAY BIT(4) 76 #define VEC_CONFIG0_RAMPEN BIT(2) 77 #define VEC_CONFIG0_YCDIS BIT(2) 78 #define VEC_CONFIG0_STD_MASK GENMASK(1, 0) 79 #define VEC_CONFIG0_NTSC_STD 0 80 #define VEC_CONFIG0_PAL_BDGHI_STD 1 81 #define VEC_CONFIG0_PAL_N_STD 3 82 83 #define VEC_SCHPH 0x108 84 #define VEC_SOFT_RESET 0x10c 85 #define VEC_CLMP0_START 0x144 86 #define VEC_CLMP0_END 0x148 87 #define VEC_FREQ3_2 0x180 88 #define VEC_FREQ1_0 0x184 89 90 #define VEC_CONFIG1 0x188 91 #define VEC_CONFIG_VEC_RESYNC_OFF BIT(18) 92 #define VEC_CONFIG_RGB219 BIT(17) 93 #define VEC_CONFIG_CBAR_EN BIT(16) 94 #define VEC_CONFIG_TC_OBB BIT(15) 95 #define VEC_CONFIG1_OUTPUT_MODE_MASK GENMASK(12, 10) 96 #define VEC_CONFIG1_C_Y_CVBS (0 << 10) 97 #define VEC_CONFIG1_CVBS_Y_C (1 << 10) 98 #define VEC_CONFIG1_PR_Y_PB (2 << 10) 99 #define VEC_CONFIG1_RGB (4 << 10) 100 #define VEC_CONFIG1_Y_C_CVBS (5 << 10) 101 #define VEC_CONFIG1_C_CVBS_Y (6 << 10) 102 #define VEC_CONFIG1_C_CVBS_CVBS (7 << 10) 103 #define VEC_CONFIG1_DIS_CHR BIT(9) 104 #define VEC_CONFIG1_DIS_LUMA BIT(8) 105 #define VEC_CONFIG1_YCBCR_IN BIT(6) 106 #define VEC_CONFIG1_DITHER_TYPE_LFSR 0 107 #define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5) 108 #define VEC_CONFIG1_DITHER_EN BIT(4) 109 #define VEC_CONFIG1_CYDELAY BIT(3) 110 #define VEC_CONFIG1_LUMADIS BIT(2) 111 #define VEC_CONFIG1_COMPDIS BIT(1) 112 #define VEC_CONFIG1_CUSTOM_FREQ BIT(0) 113 114 #define VEC_CONFIG2 0x18c 115 #define VEC_CONFIG2_PROG_SCAN BIT(15) 116 #define VEC_CONFIG2_SYNC_ADJ_MASK GENMASK(14, 12) 117 #define VEC_CONFIG2_SYNC_ADJ(x) (((x) / 2) << 12) 118 #define VEC_CONFIG2_PBPR_EN BIT(10) 119 #define VEC_CONFIG2_UV_DIG_DIS BIT(6) 120 #define VEC_CONFIG2_RGB_DIG_DIS BIT(5) 121 #define VEC_CONFIG2_TMUX_MASK GENMASK(3, 2) 122 #define VEC_CONFIG2_TMUX_DRIVE0 (0 << 2) 123 #define VEC_CONFIG2_TMUX_RG_COMP (1 << 2) 124 #define VEC_CONFIG2_TMUX_UV_YC (2 << 2) 125 #define VEC_CONFIG2_TMUX_SYNC_YC (3 << 2) 126 127 #define VEC_INTERRUPT_CONTROL 0x190 128 #define VEC_INTERRUPT_STATUS 0x194 129 #define VEC_FCW_SECAM_B 0x198 130 #define VEC_SECAM_GAIN_VAL 0x19c 131 132 #define VEC_CONFIG3 0x1a0 133 #define VEC_CONFIG3_HORIZ_LEN_STD (0 << 0) 134 #define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0) 135 #define VEC_CONFIG3_SHAPE_NON_LINEAR BIT(1) 136 137 #define VEC_STATUS0 0x200 138 #define VEC_MASK0 0x204 139 140 #define VEC_CFG 0x208 141 #define VEC_CFG_SG_MODE_MASK GENMASK(6, 5) 142 #define VEC_CFG_SG_MODE(x) ((x) << 5) 143 #define VEC_CFG_SG_EN BIT(4) 144 #define VEC_CFG_VEC_EN BIT(3) 145 #define VEC_CFG_MB_EN BIT(2) 146 #define VEC_CFG_ENABLE BIT(1) 147 #define VEC_CFG_TB_EN BIT(0) 148 149 #define VEC_DAC_TEST 0x20c 150 151 #define VEC_DAC_CONFIG 0x210 152 #define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24) 153 #define VEC_DAC_CONFIG_DRIVER_CTRL(x) ((x) << 16) 154 #define VEC_DAC_CONFIG_DAC_CTRL(x) (x) 155 156 #define VEC_DAC_MISC 0x214 157 #define VEC_DAC_MISC_VCD_CTRL_MASK GENMASK(31, 16) 158 #define VEC_DAC_MISC_VCD_CTRL(x) ((x) << 16) 159 #define VEC_DAC_MISC_VID_ACT BIT(8) 160 #define VEC_DAC_MISC_VCD_PWRDN BIT(6) 161 #define VEC_DAC_MISC_BIAS_PWRDN BIT(5) 162 #define VEC_DAC_MISC_DAC_PWRDN BIT(2) 163 #define VEC_DAC_MISC_LDO_PWRDN BIT(1) 164 #define VEC_DAC_MISC_DAC_RST_N BIT(0) 165 166 167 /* General VEC hardware state. */ 168 struct vc4_vec { 169 struct platform_device *pdev; 170 171 struct drm_encoder *encoder; 172 struct drm_connector *connector; 173 174 void __iomem *regs; 175 176 struct clk *clock; 177 178 const struct vc4_vec_tv_mode *tv_mode; 179 180 struct debugfs_regset32 regset; 181 }; 182 183 #define VEC_READ(offset) readl(vec->regs + (offset)) 184 #define VEC_WRITE(offset, val) writel(val, vec->regs + (offset)) 185 186 /* VC4 VEC encoder KMS struct */ 187 struct vc4_vec_encoder { 188 struct vc4_encoder base; 189 struct vc4_vec *vec; 190 }; 191 192 static inline struct vc4_vec_encoder * 193 to_vc4_vec_encoder(struct drm_encoder *encoder) 194 { 195 return container_of(encoder, struct vc4_vec_encoder, base.base); 196 } 197 198 /* VC4 VEC connector KMS struct */ 199 struct vc4_vec_connector { 200 struct drm_connector base; 201 struct vc4_vec *vec; 202 203 /* Since the connector is attached to just the one encoder, 204 * this is the reference to it so we can do the best_encoder() 205 * hook. 206 */ 207 struct drm_encoder *encoder; 208 }; 209 210 static inline struct vc4_vec_connector * 211 to_vc4_vec_connector(struct drm_connector *connector) 212 { 213 return container_of(connector, struct vc4_vec_connector, base); 214 } 215 216 enum vc4_vec_tv_mode_id { 217 VC4_VEC_TV_MODE_NTSC, 218 VC4_VEC_TV_MODE_NTSC_J, 219 VC4_VEC_TV_MODE_PAL, 220 VC4_VEC_TV_MODE_PAL_M, 221 }; 222 223 struct vc4_vec_tv_mode { 224 const struct drm_display_mode *mode; 225 void (*mode_set)(struct vc4_vec *vec); 226 }; 227 228 static const struct debugfs_reg32 vec_regs[] = { 229 VC4_REG32(VEC_WSE_CONTROL), 230 VC4_REG32(VEC_WSE_WSS_DATA), 231 VC4_REG32(VEC_WSE_VPS_DATA1), 232 VC4_REG32(VEC_WSE_VPS_CONTROL), 233 VC4_REG32(VEC_REVID), 234 VC4_REG32(VEC_CONFIG0), 235 VC4_REG32(VEC_SCHPH), 236 VC4_REG32(VEC_CLMP0_START), 237 VC4_REG32(VEC_CLMP0_END), 238 VC4_REG32(VEC_FREQ3_2), 239 VC4_REG32(VEC_FREQ1_0), 240 VC4_REG32(VEC_CONFIG1), 241 VC4_REG32(VEC_CONFIG2), 242 VC4_REG32(VEC_INTERRUPT_CONTROL), 243 VC4_REG32(VEC_INTERRUPT_STATUS), 244 VC4_REG32(VEC_FCW_SECAM_B), 245 VC4_REG32(VEC_SECAM_GAIN_VAL), 246 VC4_REG32(VEC_CONFIG3), 247 VC4_REG32(VEC_STATUS0), 248 VC4_REG32(VEC_MASK0), 249 VC4_REG32(VEC_CFG), 250 VC4_REG32(VEC_DAC_TEST), 251 VC4_REG32(VEC_DAC_CONFIG), 252 VC4_REG32(VEC_DAC_MISC), 253 }; 254 255 static void vc4_vec_ntsc_mode_set(struct vc4_vec *vec) 256 { 257 VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN); 258 VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS); 259 } 260 261 static void vc4_vec_ntsc_j_mode_set(struct vc4_vec *vec) 262 { 263 VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_NTSC_STD); 264 VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS); 265 } 266 267 static const struct drm_display_mode ntsc_mode = { 268 DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500, 269 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0, 270 480, 480 + 3, 480 + 3 + 3, 480 + 3 + 3 + 16, 0, 271 DRM_MODE_FLAG_INTERLACE) 272 }; 273 274 static void vc4_vec_pal_mode_set(struct vc4_vec *vec) 275 { 276 VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD); 277 VEC_WRITE(VEC_CONFIG1, VEC_CONFIG1_C_CVBS_CVBS); 278 } 279 280 static void vc4_vec_pal_m_mode_set(struct vc4_vec *vec) 281 { 282 VEC_WRITE(VEC_CONFIG0, VEC_CONFIG0_PAL_BDGHI_STD); 283 VEC_WRITE(VEC_CONFIG1, 284 VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ); 285 VEC_WRITE(VEC_FREQ3_2, 0x223b); 286 VEC_WRITE(VEC_FREQ1_0, 0x61d1); 287 } 288 289 static const struct drm_display_mode pal_mode = { 290 DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500, 291 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0, 292 576, 576 + 2, 576 + 2 + 3, 576 + 2 + 3 + 20, 0, 293 DRM_MODE_FLAG_INTERLACE) 294 }; 295 296 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { 297 [VC4_VEC_TV_MODE_NTSC] = { 298 .mode = &ntsc_mode, 299 .mode_set = vc4_vec_ntsc_mode_set, 300 }, 301 [VC4_VEC_TV_MODE_NTSC_J] = { 302 .mode = &ntsc_mode, 303 .mode_set = vc4_vec_ntsc_j_mode_set, 304 }, 305 [VC4_VEC_TV_MODE_PAL] = { 306 .mode = &pal_mode, 307 .mode_set = vc4_vec_pal_mode_set, 308 }, 309 [VC4_VEC_TV_MODE_PAL_M] = { 310 .mode = &pal_mode, 311 .mode_set = vc4_vec_pal_m_mode_set, 312 }, 313 }; 314 315 static enum drm_connector_status 316 vc4_vec_connector_detect(struct drm_connector *connector, bool force) 317 { 318 return connector_status_unknown; 319 } 320 321 static void vc4_vec_connector_destroy(struct drm_connector *connector) 322 { 323 drm_connector_unregister(connector); 324 drm_connector_cleanup(connector); 325 } 326 327 static int vc4_vec_connector_get_modes(struct drm_connector *connector) 328 { 329 struct drm_connector_state *state = connector->state; 330 struct drm_display_mode *mode; 331 332 mode = drm_mode_duplicate(connector->dev, 333 vc4_vec_tv_modes[state->tv.mode].mode); 334 if (!mode) { 335 DRM_ERROR("Failed to create a new display mode\n"); 336 return -ENOMEM; 337 } 338 339 drm_mode_probed_add(connector, mode); 340 341 return 1; 342 } 343 344 static const struct drm_connector_funcs vc4_vec_connector_funcs = { 345 .detect = vc4_vec_connector_detect, 346 .fill_modes = drm_helper_probe_single_connector_modes, 347 .destroy = vc4_vec_connector_destroy, 348 .reset = drm_atomic_helper_connector_reset, 349 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 350 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 351 }; 352 353 static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = { 354 .get_modes = vc4_vec_connector_get_modes, 355 }; 356 357 static struct drm_connector *vc4_vec_connector_init(struct drm_device *dev, 358 struct vc4_vec *vec) 359 { 360 struct drm_connector *connector = NULL; 361 struct vc4_vec_connector *vec_connector; 362 363 vec_connector = devm_kzalloc(dev->dev, sizeof(*vec_connector), 364 GFP_KERNEL); 365 if (!vec_connector) 366 return ERR_PTR(-ENOMEM); 367 368 connector = &vec_connector->base; 369 connector->interlace_allowed = true; 370 371 vec_connector->encoder = vec->encoder; 372 vec_connector->vec = vec; 373 374 drm_connector_init(dev, connector, &vc4_vec_connector_funcs, 375 DRM_MODE_CONNECTOR_Composite); 376 drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs); 377 378 drm_object_attach_property(&connector->base, 379 dev->mode_config.tv_mode_property, 380 VC4_VEC_TV_MODE_NTSC); 381 vec->tv_mode = &vc4_vec_tv_modes[VC4_VEC_TV_MODE_NTSC]; 382 383 drm_connector_attach_encoder(connector, vec->encoder); 384 385 return connector; 386 } 387 388 static const struct drm_encoder_funcs vc4_vec_encoder_funcs = { 389 .destroy = drm_encoder_cleanup, 390 }; 391 392 static void vc4_vec_encoder_disable(struct drm_encoder *encoder) 393 { 394 struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder); 395 struct vc4_vec *vec = vc4_vec_encoder->vec; 396 int ret; 397 398 VEC_WRITE(VEC_CFG, 0); 399 VEC_WRITE(VEC_DAC_MISC, 400 VEC_DAC_MISC_VCD_PWRDN | 401 VEC_DAC_MISC_BIAS_PWRDN | 402 VEC_DAC_MISC_DAC_PWRDN | 403 VEC_DAC_MISC_LDO_PWRDN); 404 405 clk_disable_unprepare(vec->clock); 406 407 ret = pm_runtime_put(&vec->pdev->dev); 408 if (ret < 0) { 409 DRM_ERROR("Failed to release power domain: %d\n", ret); 410 return; 411 } 412 } 413 414 static void vc4_vec_encoder_enable(struct drm_encoder *encoder) 415 { 416 struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder); 417 struct vc4_vec *vec = vc4_vec_encoder->vec; 418 int ret; 419 420 ret = pm_runtime_get_sync(&vec->pdev->dev); 421 if (ret < 0) { 422 DRM_ERROR("Failed to retain power domain: %d\n", ret); 423 return; 424 } 425 426 /* 427 * We need to set the clock rate each time we enable the encoder 428 * because there's a chance we share the same parent with the HDMI 429 * clock, and both drivers are requesting different rates. 430 * The good news is, these 2 encoders cannot be enabled at the same 431 * time, thus preventing incompatible rate requests. 432 */ 433 ret = clk_set_rate(vec->clock, 108000000); 434 if (ret) { 435 DRM_ERROR("Failed to set clock rate: %d\n", ret); 436 return; 437 } 438 439 ret = clk_prepare_enable(vec->clock); 440 if (ret) { 441 DRM_ERROR("Failed to turn on core clock: %d\n", ret); 442 return; 443 } 444 445 /* Reset the different blocks */ 446 VEC_WRITE(VEC_WSE_RESET, 1); 447 VEC_WRITE(VEC_SOFT_RESET, 1); 448 449 /* Disable the CGSM-A and WSE blocks */ 450 VEC_WRITE(VEC_WSE_CONTROL, 0); 451 452 /* Write config common to all modes. */ 453 454 /* 455 * Color subcarrier phase: phase = 360 * SCHPH / 256. 456 * 0x28 <=> 39.375 deg. 457 */ 458 VEC_WRITE(VEC_SCHPH, 0x28); 459 460 /* 461 * Reset to default values. 462 */ 463 VEC_WRITE(VEC_CLMP0_START, 0xac); 464 VEC_WRITE(VEC_CLMP0_END, 0xec); 465 VEC_WRITE(VEC_CONFIG2, 466 VEC_CONFIG2_UV_DIG_DIS | VEC_CONFIG2_RGB_DIG_DIS); 467 VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD); 468 VEC_WRITE(VEC_DAC_CONFIG, 469 VEC_DAC_CONFIG_DAC_CTRL(0xc) | 470 VEC_DAC_CONFIG_DRIVER_CTRL(0xc) | 471 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46)); 472 473 /* Mask all interrupts. */ 474 VEC_WRITE(VEC_MASK0, 0); 475 476 vec->tv_mode->mode_set(vec); 477 478 VEC_WRITE(VEC_DAC_MISC, 479 VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N); 480 VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN); 481 } 482 483 484 static bool vc4_vec_encoder_mode_fixup(struct drm_encoder *encoder, 485 const struct drm_display_mode *mode, 486 struct drm_display_mode *adjusted_mode) 487 { 488 return true; 489 } 490 491 static void vc4_vec_encoder_atomic_mode_set(struct drm_encoder *encoder, 492 struct drm_crtc_state *crtc_state, 493 struct drm_connector_state *conn_state) 494 { 495 struct vc4_vec_encoder *vc4_vec_encoder = to_vc4_vec_encoder(encoder); 496 struct vc4_vec *vec = vc4_vec_encoder->vec; 497 498 vec->tv_mode = &vc4_vec_tv_modes[conn_state->tv.mode]; 499 } 500 501 static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder, 502 struct drm_crtc_state *crtc_state, 503 struct drm_connector_state *conn_state) 504 { 505 const struct vc4_vec_tv_mode *vec_mode; 506 507 vec_mode = &vc4_vec_tv_modes[conn_state->tv.mode]; 508 509 if (conn_state->crtc && 510 !drm_mode_equal(vec_mode->mode, &crtc_state->adjusted_mode)) 511 return -EINVAL; 512 513 return 0; 514 } 515 516 static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = { 517 .disable = vc4_vec_encoder_disable, 518 .enable = vc4_vec_encoder_enable, 519 .mode_fixup = vc4_vec_encoder_mode_fixup, 520 .atomic_check = vc4_vec_encoder_atomic_check, 521 .atomic_mode_set = vc4_vec_encoder_atomic_mode_set, 522 }; 523 524 static const struct of_device_id vc4_vec_dt_match[] = { 525 { .compatible = "brcm,bcm2835-vec", .data = NULL }, 526 { /* sentinel */ }, 527 }; 528 529 static const char * const tv_mode_names[] = { 530 [VC4_VEC_TV_MODE_NTSC] = "NTSC", 531 [VC4_VEC_TV_MODE_NTSC_J] = "NTSC-J", 532 [VC4_VEC_TV_MODE_PAL] = "PAL", 533 [VC4_VEC_TV_MODE_PAL_M] = "PAL-M", 534 }; 535 536 static int vc4_vec_bind(struct device *dev, struct device *master, void *data) 537 { 538 struct platform_device *pdev = to_platform_device(dev); 539 struct drm_device *drm = dev_get_drvdata(master); 540 struct vc4_dev *vc4 = to_vc4_dev(drm); 541 struct vc4_vec *vec; 542 struct vc4_vec_encoder *vc4_vec_encoder; 543 int ret; 544 545 ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(tv_mode_names), 546 tv_mode_names); 547 if (ret) 548 return ret; 549 550 vec = devm_kzalloc(dev, sizeof(*vec), GFP_KERNEL); 551 if (!vec) 552 return -ENOMEM; 553 554 vc4_vec_encoder = devm_kzalloc(dev, sizeof(*vc4_vec_encoder), 555 GFP_KERNEL); 556 if (!vc4_vec_encoder) 557 return -ENOMEM; 558 vc4_vec_encoder->base.type = VC4_ENCODER_TYPE_VEC; 559 vc4_vec_encoder->vec = vec; 560 vec->encoder = &vc4_vec_encoder->base.base; 561 562 vec->pdev = pdev; 563 vec->regs = vc4_ioremap_regs(pdev, 0); 564 if (IS_ERR(vec->regs)) 565 return PTR_ERR(vec->regs); 566 vec->regset.base = vec->regs; 567 vec->regset.regs = vec_regs; 568 vec->regset.nregs = ARRAY_SIZE(vec_regs); 569 570 vec->clock = devm_clk_get(dev, NULL); 571 if (IS_ERR(vec->clock)) { 572 ret = PTR_ERR(vec->clock); 573 if (ret != -EPROBE_DEFER) 574 DRM_ERROR("Failed to get clock: %d\n", ret); 575 return ret; 576 } 577 578 pm_runtime_enable(dev); 579 580 drm_encoder_init(drm, vec->encoder, &vc4_vec_encoder_funcs, 581 DRM_MODE_ENCODER_TVDAC, NULL); 582 drm_encoder_helper_add(vec->encoder, &vc4_vec_encoder_helper_funcs); 583 584 vec->connector = vc4_vec_connector_init(drm, vec); 585 if (IS_ERR(vec->connector)) { 586 ret = PTR_ERR(vec->connector); 587 goto err_destroy_encoder; 588 } 589 590 dev_set_drvdata(dev, vec); 591 592 vc4->vec = vec; 593 594 vc4_debugfs_add_regset32(drm, "vec_regs", &vec->regset); 595 596 return 0; 597 598 err_destroy_encoder: 599 drm_encoder_cleanup(vec->encoder); 600 pm_runtime_disable(dev); 601 602 return ret; 603 } 604 605 static void vc4_vec_unbind(struct device *dev, struct device *master, 606 void *data) 607 { 608 struct drm_device *drm = dev_get_drvdata(master); 609 struct vc4_dev *vc4 = to_vc4_dev(drm); 610 struct vc4_vec *vec = dev_get_drvdata(dev); 611 612 vc4_vec_connector_destroy(vec->connector); 613 drm_encoder_cleanup(vec->encoder); 614 pm_runtime_disable(dev); 615 616 vc4->vec = NULL; 617 } 618 619 static const struct component_ops vc4_vec_ops = { 620 .bind = vc4_vec_bind, 621 .unbind = vc4_vec_unbind, 622 }; 623 624 static int vc4_vec_dev_probe(struct platform_device *pdev) 625 { 626 return component_add(&pdev->dev, &vc4_vec_ops); 627 } 628 629 static int vc4_vec_dev_remove(struct platform_device *pdev) 630 { 631 component_del(&pdev->dev, &vc4_vec_ops); 632 return 0; 633 } 634 635 struct platform_driver vc4_vec_driver = { 636 .probe = vc4_vec_dev_probe, 637 .remove = vc4_vec_dev_remove, 638 .driver = { 639 .name = "vc4_vec", 640 .of_match_table = vc4_vec_dt_match, 641 }, 642 }; 643