1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2016 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 SDTV module 8 * 9 * The VEC encoder generates PAL or NTSC composite video output. 10 * 11 * TV mode selection is done by an atomic property on the encoder, 12 * because a drm_mode_modeinfo is insufficient to distinguish between 13 * PAL and PAL-M or NTSC and NTSC-J. 14 */ 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_panel.h> 20 #include <drm/drm_probe_helper.h> 21 #include <drm/drm_simple_kms_helper.h> 22 #include <linux/clk.h> 23 #include <linux/component.h> 24 #include <linux/of_graph.h> 25 #include <linux/of_platform.h> 26 #include <linux/pm_runtime.h> 27 28 #include "vc4_drv.h" 29 #include "vc4_regs.h" 30 31 /* WSE Registers */ 32 #define VEC_WSE_RESET 0xc0 33 34 #define VEC_WSE_CONTROL 0xc4 35 #define VEC_WSE_WSS_ENABLE BIT(7) 36 37 #define VEC_WSE_WSS_DATA 0xc8 38 #define VEC_WSE_VPS_DATA1 0xcc 39 #define VEC_WSE_VPS_CONTROL 0xd0 40 41 /* VEC Registers */ 42 #define VEC_REVID 0x100 43 44 #define VEC_CONFIG0 0x104 45 #define VEC_CONFIG0_YDEL_MASK GENMASK(28, 26) 46 #define VEC_CONFIG0_YDEL(x) ((x) << 26) 47 #define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24) 48 #define VEC_CONFIG0_CDEL(x) ((x) << 24) 49 #define VEC_CONFIG0_PBPR_FIL BIT(18) 50 #define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16) 51 #define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16) 52 #define VEC_CONFIG0_CHROMA_GAIN_1_32 (1 << 16) 53 #define VEC_CONFIG0_CHROMA_GAIN_1_16 (2 << 16) 54 #define VEC_CONFIG0_CHROMA_GAIN_1_8 (3 << 16) 55 #define VEC_CONFIG0_CBURST_GAIN_MASK GENMASK(14, 13) 56 #define VEC_CONFIG0_CBURST_GAIN_UNITY (0 << 13) 57 #define VEC_CONFIG0_CBURST_GAIN_1_128 (1 << 13) 58 #define VEC_CONFIG0_CBURST_GAIN_1_64 (2 << 13) 59 #define VEC_CONFIG0_CBURST_GAIN_1_32 (3 << 13) 60 #define VEC_CONFIG0_CHRBW1 BIT(11) 61 #define VEC_CONFIG0_CHRBW0 BIT(10) 62 #define VEC_CONFIG0_SYNCDIS BIT(9) 63 #define VEC_CONFIG0_BURDIS BIT(8) 64 #define VEC_CONFIG0_CHRDIS BIT(7) 65 #define VEC_CONFIG0_PDEN BIT(6) 66 #define VEC_CONFIG0_YCDELAY BIT(4) 67 #define VEC_CONFIG0_RAMPEN BIT(2) 68 #define VEC_CONFIG0_YCDIS BIT(2) 69 #define VEC_CONFIG0_STD_MASK GENMASK(1, 0) 70 #define VEC_CONFIG0_NTSC_STD 0 71 #define VEC_CONFIG0_PAL_BDGHI_STD 1 72 #define VEC_CONFIG0_PAL_N_STD 3 73 74 #define VEC_SCHPH 0x108 75 #define VEC_SOFT_RESET 0x10c 76 #define VEC_CLMP0_START 0x144 77 #define VEC_CLMP0_END 0x148 78 #define VEC_FREQ3_2 0x180 79 #define VEC_FREQ1_0 0x184 80 81 #define VEC_CONFIG1 0x188 82 #define VEC_CONFIG_VEC_RESYNC_OFF BIT(18) 83 #define VEC_CONFIG_RGB219 BIT(17) 84 #define VEC_CONFIG_CBAR_EN BIT(16) 85 #define VEC_CONFIG_TC_OBB BIT(15) 86 #define VEC_CONFIG1_OUTPUT_MODE_MASK GENMASK(12, 10) 87 #define VEC_CONFIG1_C_Y_CVBS (0 << 10) 88 #define VEC_CONFIG1_CVBS_Y_C (1 << 10) 89 #define VEC_CONFIG1_PR_Y_PB (2 << 10) 90 #define VEC_CONFIG1_RGB (4 << 10) 91 #define VEC_CONFIG1_Y_C_CVBS (5 << 10) 92 #define VEC_CONFIG1_C_CVBS_Y (6 << 10) 93 #define VEC_CONFIG1_C_CVBS_CVBS (7 << 10) 94 #define VEC_CONFIG1_DIS_CHR BIT(9) 95 #define VEC_CONFIG1_DIS_LUMA BIT(8) 96 #define VEC_CONFIG1_YCBCR_IN BIT(6) 97 #define VEC_CONFIG1_DITHER_TYPE_LFSR 0 98 #define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5) 99 #define VEC_CONFIG1_DITHER_EN BIT(4) 100 #define VEC_CONFIG1_CYDELAY BIT(3) 101 #define VEC_CONFIG1_LUMADIS BIT(2) 102 #define VEC_CONFIG1_COMPDIS BIT(1) 103 #define VEC_CONFIG1_CUSTOM_FREQ BIT(0) 104 105 #define VEC_CONFIG2 0x18c 106 #define VEC_CONFIG2_PROG_SCAN BIT(15) 107 #define VEC_CONFIG2_SYNC_ADJ_MASK GENMASK(14, 12) 108 #define VEC_CONFIG2_SYNC_ADJ(x) (((x) / 2) << 12) 109 #define VEC_CONFIG2_PBPR_EN BIT(10) 110 #define VEC_CONFIG2_UV_DIG_DIS BIT(6) 111 #define VEC_CONFIG2_RGB_DIG_DIS BIT(5) 112 #define VEC_CONFIG2_TMUX_MASK GENMASK(3, 2) 113 #define VEC_CONFIG2_TMUX_DRIVE0 (0 << 2) 114 #define VEC_CONFIG2_TMUX_RG_COMP (1 << 2) 115 #define VEC_CONFIG2_TMUX_UV_YC (2 << 2) 116 #define VEC_CONFIG2_TMUX_SYNC_YC (3 << 2) 117 118 #define VEC_INTERRUPT_CONTROL 0x190 119 #define VEC_INTERRUPT_STATUS 0x194 120 #define VEC_FCW_SECAM_B 0x198 121 #define VEC_SECAM_GAIN_VAL 0x19c 122 123 #define VEC_CONFIG3 0x1a0 124 #define VEC_CONFIG3_HORIZ_LEN_STD (0 << 0) 125 #define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0) 126 #define VEC_CONFIG3_SHAPE_NON_LINEAR BIT(1) 127 128 #define VEC_STATUS0 0x200 129 #define VEC_MASK0 0x204 130 131 #define VEC_CFG 0x208 132 #define VEC_CFG_SG_MODE_MASK GENMASK(6, 5) 133 #define VEC_CFG_SG_MODE(x) ((x) << 5) 134 #define VEC_CFG_SG_EN BIT(4) 135 #define VEC_CFG_VEC_EN BIT(3) 136 #define VEC_CFG_MB_EN BIT(2) 137 #define VEC_CFG_ENABLE BIT(1) 138 #define VEC_CFG_TB_EN BIT(0) 139 140 #define VEC_DAC_TEST 0x20c 141 142 #define VEC_DAC_CONFIG 0x210 143 #define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24) 144 #define VEC_DAC_CONFIG_DRIVER_CTRL(x) ((x) << 16) 145 #define VEC_DAC_CONFIG_DAC_CTRL(x) (x) 146 147 #define VEC_DAC_MISC 0x214 148 #define VEC_DAC_MISC_VCD_CTRL_MASK GENMASK(31, 16) 149 #define VEC_DAC_MISC_VCD_CTRL(x) ((x) << 16) 150 #define VEC_DAC_MISC_VID_ACT BIT(8) 151 #define VEC_DAC_MISC_VCD_PWRDN BIT(6) 152 #define VEC_DAC_MISC_BIAS_PWRDN BIT(5) 153 #define VEC_DAC_MISC_DAC_PWRDN BIT(2) 154 #define VEC_DAC_MISC_LDO_PWRDN BIT(1) 155 #define VEC_DAC_MISC_DAC_RST_N BIT(0) 156 157 158 struct vc4_vec_variant { 159 u32 dac_config; 160 }; 161 162 /* General VEC hardware state. */ 163 struct vc4_vec { 164 struct vc4_encoder encoder; 165 struct drm_connector connector; 166 167 struct platform_device *pdev; 168 const struct vc4_vec_variant *variant; 169 170 void __iomem *regs; 171 172 struct clk *clock; 173 174 struct debugfs_regset32 regset; 175 }; 176 177 #define VEC_READ(offset) readl(vec->regs + (offset)) 178 #define VEC_WRITE(offset, val) writel(val, vec->regs + (offset)) 179 180 static inline struct vc4_vec * 181 encoder_to_vc4_vec(struct drm_encoder *encoder) 182 { 183 return container_of(encoder, struct vc4_vec, encoder.base); 184 } 185 186 enum vc4_vec_tv_mode_id { 187 VC4_VEC_TV_MODE_NTSC, 188 VC4_VEC_TV_MODE_NTSC_J, 189 VC4_VEC_TV_MODE_PAL, 190 VC4_VEC_TV_MODE_PAL_M, 191 }; 192 193 struct vc4_vec_tv_mode { 194 const struct drm_display_mode *mode; 195 u32 config0; 196 u32 config1; 197 u32 custom_freq; 198 }; 199 200 static const struct debugfs_reg32 vec_regs[] = { 201 VC4_REG32(VEC_WSE_CONTROL), 202 VC4_REG32(VEC_WSE_WSS_DATA), 203 VC4_REG32(VEC_WSE_VPS_DATA1), 204 VC4_REG32(VEC_WSE_VPS_CONTROL), 205 VC4_REG32(VEC_REVID), 206 VC4_REG32(VEC_CONFIG0), 207 VC4_REG32(VEC_SCHPH), 208 VC4_REG32(VEC_CLMP0_START), 209 VC4_REG32(VEC_CLMP0_END), 210 VC4_REG32(VEC_FREQ3_2), 211 VC4_REG32(VEC_FREQ1_0), 212 VC4_REG32(VEC_CONFIG1), 213 VC4_REG32(VEC_CONFIG2), 214 VC4_REG32(VEC_INTERRUPT_CONTROL), 215 VC4_REG32(VEC_INTERRUPT_STATUS), 216 VC4_REG32(VEC_FCW_SECAM_B), 217 VC4_REG32(VEC_SECAM_GAIN_VAL), 218 VC4_REG32(VEC_CONFIG3), 219 VC4_REG32(VEC_STATUS0), 220 VC4_REG32(VEC_MASK0), 221 VC4_REG32(VEC_CFG), 222 VC4_REG32(VEC_DAC_TEST), 223 VC4_REG32(VEC_DAC_CONFIG), 224 VC4_REG32(VEC_DAC_MISC), 225 }; 226 227 static const struct drm_display_mode ntsc_mode = { 228 DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 13500, 229 720, 720 + 14, 720 + 14 + 64, 720 + 14 + 64 + 60, 0, 230 480, 480 + 7, 480 + 7 + 6, 525, 0, 231 DRM_MODE_FLAG_INTERLACE) 232 }; 233 234 static const struct drm_display_mode pal_mode = { 235 DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 13500, 236 720, 720 + 20, 720 + 20 + 64, 720 + 20 + 64 + 60, 0, 237 576, 576 + 4, 576 + 4 + 6, 625, 0, 238 DRM_MODE_FLAG_INTERLACE) 239 }; 240 241 static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = { 242 [VC4_VEC_TV_MODE_NTSC] = { 243 .mode = &ntsc_mode, 244 .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN, 245 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 246 }, 247 [VC4_VEC_TV_MODE_NTSC_J] = { 248 .mode = &ntsc_mode, 249 .config0 = VEC_CONFIG0_NTSC_STD, 250 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 251 }, 252 [VC4_VEC_TV_MODE_PAL] = { 253 .mode = &pal_mode, 254 .config0 = VEC_CONFIG0_PAL_BDGHI_STD, 255 .config1 = VEC_CONFIG1_C_CVBS_CVBS, 256 }, 257 [VC4_VEC_TV_MODE_PAL_M] = { 258 .mode = &pal_mode, 259 .config0 = VEC_CONFIG0_PAL_BDGHI_STD, 260 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ, 261 .custom_freq = 0x223b61d1, 262 }, 263 }; 264 265 static enum drm_connector_status 266 vc4_vec_connector_detect(struct drm_connector *connector, bool force) 267 { 268 return connector_status_unknown; 269 } 270 271 static int vc4_vec_connector_get_modes(struct drm_connector *connector) 272 { 273 struct drm_connector_state *state = connector->state; 274 struct drm_display_mode *mode; 275 276 mode = drm_mode_duplicate(connector->dev, 277 vc4_vec_tv_modes[state->tv.mode].mode); 278 if (!mode) { 279 DRM_ERROR("Failed to create a new display mode\n"); 280 return -ENOMEM; 281 } 282 283 drm_mode_probed_add(connector, mode); 284 285 return 1; 286 } 287 288 static const struct drm_connector_funcs vc4_vec_connector_funcs = { 289 .detect = vc4_vec_connector_detect, 290 .fill_modes = drm_helper_probe_single_connector_modes, 291 .reset = drm_atomic_helper_connector_reset, 292 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 293 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 294 }; 295 296 static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = { 297 .get_modes = vc4_vec_connector_get_modes, 298 }; 299 300 static int vc4_vec_connector_init(struct drm_device *dev, struct vc4_vec *vec) 301 { 302 struct drm_connector *connector = &vec->connector; 303 int ret; 304 305 connector->interlace_allowed = true; 306 307 ret = drmm_connector_init(dev, connector, &vc4_vec_connector_funcs, 308 DRM_MODE_CONNECTOR_Composite, NULL); 309 if (ret) 310 return ret; 311 312 drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs); 313 314 drm_object_attach_property(&connector->base, 315 dev->mode_config.tv_mode_property, 316 VC4_VEC_TV_MODE_NTSC); 317 318 drm_connector_attach_encoder(connector, &vec->encoder.base); 319 320 return 0; 321 } 322 323 static void vc4_vec_encoder_disable(struct drm_encoder *encoder, 324 struct drm_atomic_state *state) 325 { 326 struct drm_device *drm = encoder->dev; 327 struct vc4_vec *vec = encoder_to_vc4_vec(encoder); 328 int idx, ret; 329 330 if (!drm_dev_enter(drm, &idx)) 331 return; 332 333 VEC_WRITE(VEC_CFG, 0); 334 VEC_WRITE(VEC_DAC_MISC, 335 VEC_DAC_MISC_VCD_PWRDN | 336 VEC_DAC_MISC_BIAS_PWRDN | 337 VEC_DAC_MISC_DAC_PWRDN | 338 VEC_DAC_MISC_LDO_PWRDN); 339 340 clk_disable_unprepare(vec->clock); 341 342 ret = pm_runtime_put(&vec->pdev->dev); 343 if (ret < 0) { 344 DRM_ERROR("Failed to release power domain: %d\n", ret); 345 goto err_dev_exit; 346 } 347 348 drm_dev_exit(idx); 349 return; 350 351 err_dev_exit: 352 drm_dev_exit(idx); 353 } 354 355 static void vc4_vec_encoder_enable(struct drm_encoder *encoder, 356 struct drm_atomic_state *state) 357 { 358 struct drm_device *drm = encoder->dev; 359 struct vc4_vec *vec = encoder_to_vc4_vec(encoder); 360 struct drm_connector *connector = &vec->connector; 361 struct drm_connector_state *conn_state = 362 drm_atomic_get_new_connector_state(state, connector); 363 const struct vc4_vec_tv_mode *tv_mode = 364 &vc4_vec_tv_modes[conn_state->tv.mode]; 365 int idx, ret; 366 367 if (!drm_dev_enter(drm, &idx)) 368 return; 369 370 ret = pm_runtime_get_sync(&vec->pdev->dev); 371 if (ret < 0) { 372 DRM_ERROR("Failed to retain power domain: %d\n", ret); 373 goto err_dev_exit; 374 } 375 376 /* 377 * We need to set the clock rate each time we enable the encoder 378 * because there's a chance we share the same parent with the HDMI 379 * clock, and both drivers are requesting different rates. 380 * The good news is, these 2 encoders cannot be enabled at the same 381 * time, thus preventing incompatible rate requests. 382 */ 383 ret = clk_set_rate(vec->clock, 108000000); 384 if (ret) { 385 DRM_ERROR("Failed to set clock rate: %d\n", ret); 386 goto err_put_runtime_pm; 387 } 388 389 ret = clk_prepare_enable(vec->clock); 390 if (ret) { 391 DRM_ERROR("Failed to turn on core clock: %d\n", ret); 392 goto err_put_runtime_pm; 393 } 394 395 /* Reset the different blocks */ 396 VEC_WRITE(VEC_WSE_RESET, 1); 397 VEC_WRITE(VEC_SOFT_RESET, 1); 398 399 /* Disable the CGSM-A and WSE blocks */ 400 VEC_WRITE(VEC_WSE_CONTROL, 0); 401 402 /* Write config common to all modes. */ 403 404 /* 405 * Color subcarrier phase: phase = 360 * SCHPH / 256. 406 * 0x28 <=> 39.375 deg. 407 */ 408 VEC_WRITE(VEC_SCHPH, 0x28); 409 410 /* 411 * Reset to default values. 412 */ 413 VEC_WRITE(VEC_CLMP0_START, 0xac); 414 VEC_WRITE(VEC_CLMP0_END, 0xec); 415 VEC_WRITE(VEC_CONFIG2, 416 VEC_CONFIG2_UV_DIG_DIS | VEC_CONFIG2_RGB_DIG_DIS); 417 VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD); 418 VEC_WRITE(VEC_DAC_CONFIG, vec->variant->dac_config); 419 420 /* Mask all interrupts. */ 421 VEC_WRITE(VEC_MASK0, 0); 422 423 VEC_WRITE(VEC_CONFIG0, tv_mode->config0); 424 VEC_WRITE(VEC_CONFIG1, tv_mode->config1); 425 426 if (tv_mode->custom_freq) { 427 VEC_WRITE(VEC_FREQ3_2, 428 (tv_mode->custom_freq >> 16) & 0xffff); 429 VEC_WRITE(VEC_FREQ1_0, 430 tv_mode->custom_freq & 0xffff); 431 } 432 433 VEC_WRITE(VEC_DAC_MISC, 434 VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N); 435 VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN); 436 437 drm_dev_exit(idx); 438 return; 439 440 err_put_runtime_pm: 441 pm_runtime_put(&vec->pdev->dev); 442 err_dev_exit: 443 drm_dev_exit(idx); 444 } 445 446 static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder, 447 struct drm_crtc_state *crtc_state, 448 struct drm_connector_state *conn_state) 449 { 450 const struct vc4_vec_tv_mode *vec_mode; 451 452 vec_mode = &vc4_vec_tv_modes[conn_state->tv.mode]; 453 454 if (conn_state->crtc && 455 !drm_mode_equal(vec_mode->mode, &crtc_state->adjusted_mode)) 456 return -EINVAL; 457 458 return 0; 459 } 460 461 static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = { 462 .atomic_check = vc4_vec_encoder_atomic_check, 463 .atomic_disable = vc4_vec_encoder_disable, 464 .atomic_enable = vc4_vec_encoder_enable, 465 }; 466 467 static int vc4_vec_late_register(struct drm_encoder *encoder) 468 { 469 struct drm_device *drm = encoder->dev; 470 struct vc4_vec *vec = encoder_to_vc4_vec(encoder); 471 int ret; 472 473 ret = vc4_debugfs_add_regset32(drm->primary, "vec_regs", 474 &vec->regset); 475 if (ret) 476 return ret; 477 478 return 0; 479 } 480 481 static const struct drm_encoder_funcs vc4_vec_encoder_funcs = { 482 .late_register = vc4_vec_late_register, 483 }; 484 485 static const struct vc4_vec_variant bcm2835_vec_variant = { 486 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0xc) | 487 VEC_DAC_CONFIG_DRIVER_CTRL(0xc) | 488 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46) 489 }; 490 491 static const struct vc4_vec_variant bcm2711_vec_variant = { 492 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0x0) | 493 VEC_DAC_CONFIG_DRIVER_CTRL(0x80) | 494 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x61) 495 }; 496 497 static const struct of_device_id vc4_vec_dt_match[] = { 498 { .compatible = "brcm,bcm2835-vec", .data = &bcm2835_vec_variant }, 499 { .compatible = "brcm,bcm2711-vec", .data = &bcm2711_vec_variant }, 500 { /* sentinel */ }, 501 }; 502 503 static const char * const tv_mode_names[] = { 504 [VC4_VEC_TV_MODE_NTSC] = "NTSC", 505 [VC4_VEC_TV_MODE_NTSC_J] = "NTSC-J", 506 [VC4_VEC_TV_MODE_PAL] = "PAL", 507 [VC4_VEC_TV_MODE_PAL_M] = "PAL-M", 508 }; 509 510 static int vc4_vec_bind(struct device *dev, struct device *master, void *data) 511 { 512 struct platform_device *pdev = to_platform_device(dev); 513 struct drm_device *drm = dev_get_drvdata(master); 514 struct vc4_vec *vec; 515 int ret; 516 517 ret = drm_mode_create_tv_properties(drm, ARRAY_SIZE(tv_mode_names), 518 tv_mode_names); 519 if (ret) 520 return ret; 521 522 vec = drmm_kzalloc(drm, sizeof(*vec), GFP_KERNEL); 523 if (!vec) 524 return -ENOMEM; 525 526 vec->encoder.type = VC4_ENCODER_TYPE_VEC; 527 vec->pdev = pdev; 528 vec->variant = (const struct vc4_vec_variant *) 529 of_device_get_match_data(dev); 530 vec->regs = vc4_ioremap_regs(pdev, 0); 531 if (IS_ERR(vec->regs)) 532 return PTR_ERR(vec->regs); 533 vec->regset.base = vec->regs; 534 vec->regset.regs = vec_regs; 535 vec->regset.nregs = ARRAY_SIZE(vec_regs); 536 537 vec->clock = devm_clk_get(dev, NULL); 538 if (IS_ERR(vec->clock)) { 539 ret = PTR_ERR(vec->clock); 540 if (ret != -EPROBE_DEFER) 541 DRM_ERROR("Failed to get clock: %d\n", ret); 542 return ret; 543 } 544 545 ret = devm_pm_runtime_enable(dev); 546 if (ret) 547 return ret; 548 549 ret = drmm_encoder_init(drm, &vec->encoder.base, 550 &vc4_vec_encoder_funcs, 551 DRM_MODE_ENCODER_TVDAC, 552 NULL); 553 if (ret) 554 return ret; 555 556 drm_encoder_helper_add(&vec->encoder.base, &vc4_vec_encoder_helper_funcs); 557 558 ret = vc4_vec_connector_init(drm, vec); 559 if (ret) 560 return ret; 561 562 dev_set_drvdata(dev, vec); 563 564 return 0; 565 } 566 567 static const struct component_ops vc4_vec_ops = { 568 .bind = vc4_vec_bind, 569 }; 570 571 static int vc4_vec_dev_probe(struct platform_device *pdev) 572 { 573 return component_add(&pdev->dev, &vc4_vec_ops); 574 } 575 576 static int vc4_vec_dev_remove(struct platform_device *pdev) 577 { 578 component_del(&pdev->dev, &vc4_vec_ops); 579 return 0; 580 } 581 582 struct platform_driver vc4_vec_driver = { 583 .probe = vc4_vec_dev_probe, 584 .remove = vc4_vec_dev_remove, 585 .driver = { 586 .name = "vc4_vec", 587 .of_match_table = vc4_vec_dt_match, 588 }, 589 }; 590