1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/platform_device.h> 11 #include <linux/pm_runtime.h> 12 13 #include <drm/drm_irq.h> 14 15 #include "vc4_drv.h" 16 #include "vc4_regs.h" 17 18 static const struct debugfs_reg32 v3d_regs[] = { 19 VC4_REG32(V3D_IDENT0), 20 VC4_REG32(V3D_IDENT1), 21 VC4_REG32(V3D_IDENT2), 22 VC4_REG32(V3D_SCRATCH), 23 VC4_REG32(V3D_L2CACTL), 24 VC4_REG32(V3D_SLCACTL), 25 VC4_REG32(V3D_INTCTL), 26 VC4_REG32(V3D_INTENA), 27 VC4_REG32(V3D_INTDIS), 28 VC4_REG32(V3D_CT0CS), 29 VC4_REG32(V3D_CT1CS), 30 VC4_REG32(V3D_CT0EA), 31 VC4_REG32(V3D_CT1EA), 32 VC4_REG32(V3D_CT0CA), 33 VC4_REG32(V3D_CT1CA), 34 VC4_REG32(V3D_CT00RA0), 35 VC4_REG32(V3D_CT01RA0), 36 VC4_REG32(V3D_CT0LC), 37 VC4_REG32(V3D_CT1LC), 38 VC4_REG32(V3D_CT0PC), 39 VC4_REG32(V3D_CT1PC), 40 VC4_REG32(V3D_PCS), 41 VC4_REG32(V3D_BFC), 42 VC4_REG32(V3D_RFC), 43 VC4_REG32(V3D_BPCA), 44 VC4_REG32(V3D_BPCS), 45 VC4_REG32(V3D_BPOA), 46 VC4_REG32(V3D_BPOS), 47 VC4_REG32(V3D_BXCF), 48 VC4_REG32(V3D_SQRSV0), 49 VC4_REG32(V3D_SQRSV1), 50 VC4_REG32(V3D_SQCNTL), 51 VC4_REG32(V3D_SRQPC), 52 VC4_REG32(V3D_SRQUA), 53 VC4_REG32(V3D_SRQUL), 54 VC4_REG32(V3D_SRQCS), 55 VC4_REG32(V3D_VPACNTL), 56 VC4_REG32(V3D_VPMBASE), 57 VC4_REG32(V3D_PCTRC), 58 VC4_REG32(V3D_PCTRE), 59 VC4_REG32(V3D_PCTR(0)), 60 VC4_REG32(V3D_PCTRS(0)), 61 VC4_REG32(V3D_PCTR(1)), 62 VC4_REG32(V3D_PCTRS(1)), 63 VC4_REG32(V3D_PCTR(2)), 64 VC4_REG32(V3D_PCTRS(2)), 65 VC4_REG32(V3D_PCTR(3)), 66 VC4_REG32(V3D_PCTRS(3)), 67 VC4_REG32(V3D_PCTR(4)), 68 VC4_REG32(V3D_PCTRS(4)), 69 VC4_REG32(V3D_PCTR(5)), 70 VC4_REG32(V3D_PCTRS(5)), 71 VC4_REG32(V3D_PCTR(6)), 72 VC4_REG32(V3D_PCTRS(6)), 73 VC4_REG32(V3D_PCTR(7)), 74 VC4_REG32(V3D_PCTRS(7)), 75 VC4_REG32(V3D_PCTR(8)), 76 VC4_REG32(V3D_PCTRS(8)), 77 VC4_REG32(V3D_PCTR(9)), 78 VC4_REG32(V3D_PCTRS(9)), 79 VC4_REG32(V3D_PCTR(10)), 80 VC4_REG32(V3D_PCTRS(10)), 81 VC4_REG32(V3D_PCTR(11)), 82 VC4_REG32(V3D_PCTRS(11)), 83 VC4_REG32(V3D_PCTR(12)), 84 VC4_REG32(V3D_PCTRS(12)), 85 VC4_REG32(V3D_PCTR(13)), 86 VC4_REG32(V3D_PCTRS(13)), 87 VC4_REG32(V3D_PCTR(14)), 88 VC4_REG32(V3D_PCTRS(14)), 89 VC4_REG32(V3D_PCTR(15)), 90 VC4_REG32(V3D_PCTRS(15)), 91 VC4_REG32(V3D_DBGE), 92 VC4_REG32(V3D_FDBGO), 93 VC4_REG32(V3D_FDBGB), 94 VC4_REG32(V3D_FDBGR), 95 VC4_REG32(V3D_FDBGS), 96 VC4_REG32(V3D_ERRSTAT), 97 }; 98 99 static int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused) 100 { 101 struct drm_info_node *node = (struct drm_info_node *)m->private; 102 struct drm_device *dev = node->minor->dev; 103 struct vc4_dev *vc4 = to_vc4_dev(dev); 104 int ret = vc4_v3d_pm_get(vc4); 105 106 if (ret == 0) { 107 uint32_t ident1 = V3D_READ(V3D_IDENT1); 108 uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC); 109 uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS); 110 uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS); 111 112 seq_printf(m, "Revision: %d\n", 113 VC4_GET_FIELD(ident1, V3D_IDENT1_REV)); 114 seq_printf(m, "Slices: %d\n", nslc); 115 seq_printf(m, "TMUs: %d\n", nslc * tups); 116 seq_printf(m, "QPUs: %d\n", nslc * qups); 117 seq_printf(m, "Semaphores: %d\n", 118 VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM)); 119 vc4_v3d_pm_put(vc4); 120 } 121 122 return 0; 123 } 124 125 /* 126 * Wraps pm_runtime_get_sync() in a refcount, so that we can reliably 127 * get the pm_runtime refcount to 0 in vc4_reset(). 128 */ 129 int 130 vc4_v3d_pm_get(struct vc4_dev *vc4) 131 { 132 mutex_lock(&vc4->power_lock); 133 if (vc4->power_refcount++ == 0) { 134 int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev); 135 136 if (ret < 0) { 137 vc4->power_refcount--; 138 mutex_unlock(&vc4->power_lock); 139 return ret; 140 } 141 } 142 mutex_unlock(&vc4->power_lock); 143 144 return 0; 145 } 146 147 void 148 vc4_v3d_pm_put(struct vc4_dev *vc4) 149 { 150 mutex_lock(&vc4->power_lock); 151 if (--vc4->power_refcount == 0) { 152 pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev); 153 pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev); 154 } 155 mutex_unlock(&vc4->power_lock); 156 } 157 158 static void vc4_v3d_init_hw(struct drm_device *dev) 159 { 160 struct vc4_dev *vc4 = to_vc4_dev(dev); 161 162 /* Take all the memory that would have been reserved for user 163 * QPU programs, since we don't have an interface for running 164 * them, anyway. 165 */ 166 V3D_WRITE(V3D_VPMBASE, 0); 167 } 168 169 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4) 170 { 171 struct drm_device *dev = &vc4->base; 172 unsigned long irqflags; 173 int slot; 174 uint64_t seqno = 0; 175 struct vc4_exec_info *exec; 176 177 try_again: 178 spin_lock_irqsave(&vc4->job_lock, irqflags); 179 slot = ffs(~vc4->bin_alloc_used); 180 if (slot != 0) { 181 /* Switch from ffs() bit index to a 0-based index. */ 182 slot--; 183 vc4->bin_alloc_used |= BIT(slot); 184 spin_unlock_irqrestore(&vc4->job_lock, irqflags); 185 return slot; 186 } 187 188 /* Couldn't find an open slot. Wait for render to complete 189 * and try again. 190 */ 191 exec = vc4_last_render_job(vc4); 192 if (exec) 193 seqno = exec->seqno; 194 spin_unlock_irqrestore(&vc4->job_lock, irqflags); 195 196 if (seqno) { 197 int ret = vc4_wait_for_seqno(dev, seqno, ~0ull, true); 198 199 if (ret == 0) 200 goto try_again; 201 202 return ret; 203 } 204 205 return -ENOMEM; 206 } 207 208 /* 209 * bin_bo_alloc() - allocates the memory that will be used for 210 * tile binning. 211 * 212 * The binner has a limitation that the addresses in the tile state 213 * buffer that point into the tile alloc buffer or binner overflow 214 * memory only have 28 bits (256MB), and the top 4 on the bus for 215 * tile alloc references end up coming from the tile state buffer's 216 * address. 217 * 218 * To work around this, we allocate a single large buffer while V3D is 219 * in use, make sure that it has the top 4 bits constant across its 220 * entire extent, and then put the tile state, tile alloc, and binner 221 * overflow memory inside that buffer. 222 * 223 * This creates a limitation where we may not be able to execute a job 224 * if it doesn't fit within the buffer that we allocated up front. 225 * However, it turns out that 16MB is "enough for anybody", and 226 * real-world applications run into allocation failures from the 227 * overall CMA pool before they make scenes complicated enough to run 228 * out of bin space. 229 */ 230 static int bin_bo_alloc(struct vc4_dev *vc4) 231 { 232 struct vc4_v3d *v3d = vc4->v3d; 233 uint32_t size = 16 * 1024 * 1024; 234 int ret = 0; 235 struct list_head list; 236 237 if (!v3d) 238 return -ENODEV; 239 240 /* We may need to try allocating more than once to get a BO 241 * that doesn't cross 256MB. Track the ones we've allocated 242 * that failed so far, so that we can free them when we've got 243 * one that succeeded (if we freed them right away, our next 244 * allocation would probably be the same chunk of memory). 245 */ 246 INIT_LIST_HEAD(&list); 247 248 while (true) { 249 struct vc4_bo *bo = vc4_bo_create(&vc4->base, size, true, 250 VC4_BO_TYPE_BIN); 251 252 if (IS_ERR(bo)) { 253 ret = PTR_ERR(bo); 254 255 dev_err(&v3d->pdev->dev, 256 "Failed to allocate memory for tile binning: " 257 "%d. You may need to enable CMA or give it " 258 "more memory.", 259 ret); 260 break; 261 } 262 263 /* Check if this BO won't trigger the addressing bug. */ 264 if ((bo->base.paddr & 0xf0000000) == 265 ((bo->base.paddr + bo->base.base.size - 1) & 0xf0000000)) { 266 vc4->bin_bo = bo; 267 268 /* Set up for allocating 512KB chunks of 269 * binner memory. The biggest allocation we 270 * need to do is for the initial tile alloc + 271 * tile state buffer. We can render to a 272 * maximum of ((2048*2048) / (32*32) = 4096 273 * tiles in a frame (until we do floating 274 * point rendering, at which point it would be 275 * 8192). Tile state is 48b/tile (rounded to 276 * a page), and tile alloc is 32b/tile 277 * (rounded to a page), plus a page of extra, 278 * for a total of 320kb for our worst-case. 279 * We choose 512kb so that it divides evenly 280 * into our 16MB, and the rest of the 512kb 281 * will be used as storage for the overflow 282 * from the initial 32b CL per bin. 283 */ 284 vc4->bin_alloc_size = 512 * 1024; 285 vc4->bin_alloc_used = 0; 286 vc4->bin_alloc_overflow = 0; 287 WARN_ON_ONCE(sizeof(vc4->bin_alloc_used) * 8 != 288 bo->base.base.size / vc4->bin_alloc_size); 289 290 kref_init(&vc4->bin_bo_kref); 291 292 /* Enable the out-of-memory interrupt to set our 293 * newly-allocated binner BO, potentially from an 294 * already-pending-but-masked interrupt. 295 */ 296 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM); 297 298 break; 299 } 300 301 /* Put it on the list to free later, and try again. */ 302 list_add(&bo->unref_head, &list); 303 } 304 305 /* Free all the BOs we allocated but didn't choose. */ 306 while (!list_empty(&list)) { 307 struct vc4_bo *bo = list_last_entry(&list, 308 struct vc4_bo, unref_head); 309 310 list_del(&bo->unref_head); 311 drm_gem_object_put(&bo->base.base); 312 } 313 314 return ret; 315 } 316 317 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used) 318 { 319 int ret = 0; 320 321 mutex_lock(&vc4->bin_bo_lock); 322 323 if (used && *used) 324 goto complete; 325 326 if (vc4->bin_bo) 327 kref_get(&vc4->bin_bo_kref); 328 else 329 ret = bin_bo_alloc(vc4); 330 331 if (ret == 0 && used) 332 *used = true; 333 334 complete: 335 mutex_unlock(&vc4->bin_bo_lock); 336 337 return ret; 338 } 339 340 static void bin_bo_release(struct kref *ref) 341 { 342 struct vc4_dev *vc4 = container_of(ref, struct vc4_dev, bin_bo_kref); 343 344 if (WARN_ON_ONCE(!vc4->bin_bo)) 345 return; 346 347 drm_gem_object_put(&vc4->bin_bo->base.base); 348 vc4->bin_bo = NULL; 349 } 350 351 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4) 352 { 353 mutex_lock(&vc4->bin_bo_lock); 354 kref_put(&vc4->bin_bo_kref, bin_bo_release); 355 mutex_unlock(&vc4->bin_bo_lock); 356 } 357 358 #ifdef CONFIG_PM 359 static int vc4_v3d_runtime_suspend(struct device *dev) 360 { 361 struct vc4_v3d *v3d = dev_get_drvdata(dev); 362 struct vc4_dev *vc4 = v3d->vc4; 363 364 vc4_irq_uninstall(&vc4->base); 365 366 clk_disable_unprepare(v3d->clk); 367 368 return 0; 369 } 370 371 static int vc4_v3d_runtime_resume(struct device *dev) 372 { 373 struct vc4_v3d *v3d = dev_get_drvdata(dev); 374 struct vc4_dev *vc4 = v3d->vc4; 375 int ret; 376 377 ret = clk_prepare_enable(v3d->clk); 378 if (ret != 0) 379 return ret; 380 381 vc4_v3d_init_hw(&vc4->base); 382 383 /* We disabled the IRQ as part of vc4_irq_uninstall in suspend. */ 384 enable_irq(vc4->base.irq); 385 vc4_irq_postinstall(&vc4->base); 386 387 return 0; 388 } 389 #endif 390 391 static int vc4_v3d_bind(struct device *dev, struct device *master, void *data) 392 { 393 struct platform_device *pdev = to_platform_device(dev); 394 struct drm_device *drm = dev_get_drvdata(master); 395 struct vc4_dev *vc4 = to_vc4_dev(drm); 396 struct vc4_v3d *v3d = NULL; 397 int ret; 398 399 v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL); 400 if (!v3d) 401 return -ENOMEM; 402 403 dev_set_drvdata(dev, v3d); 404 405 v3d->pdev = pdev; 406 407 v3d->regs = vc4_ioremap_regs(pdev, 0); 408 if (IS_ERR(v3d->regs)) 409 return PTR_ERR(v3d->regs); 410 v3d->regset.base = v3d->regs; 411 v3d->regset.regs = v3d_regs; 412 v3d->regset.nregs = ARRAY_SIZE(v3d_regs); 413 414 vc4->v3d = v3d; 415 v3d->vc4 = vc4; 416 417 v3d->clk = devm_clk_get(dev, NULL); 418 if (IS_ERR(v3d->clk)) { 419 int ret = PTR_ERR(v3d->clk); 420 421 if (ret == -ENOENT) { 422 /* bcm2835 didn't have a clock reference in the DT. */ 423 ret = 0; 424 v3d->clk = NULL; 425 } else { 426 if (ret != -EPROBE_DEFER) 427 dev_err(dev, "Failed to get V3D clock: %d\n", 428 ret); 429 return ret; 430 } 431 } 432 433 if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) { 434 DRM_ERROR("V3D_IDENT0 read 0x%08x instead of 0x%08x\n", 435 V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0); 436 return -EINVAL; 437 } 438 439 ret = clk_prepare_enable(v3d->clk); 440 if (ret != 0) 441 return ret; 442 443 /* Reset the binner overflow address/size at setup, to be sure 444 * we don't reuse an old one. 445 */ 446 V3D_WRITE(V3D_BPOA, 0); 447 V3D_WRITE(V3D_BPOS, 0); 448 449 vc4_v3d_init_hw(drm); 450 451 ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); 452 if (ret) { 453 DRM_ERROR("Failed to install IRQ handler\n"); 454 return ret; 455 } 456 457 pm_runtime_set_active(dev); 458 pm_runtime_use_autosuspend(dev); 459 pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */ 460 pm_runtime_enable(dev); 461 462 vc4_debugfs_add_file(drm, "v3d_ident", vc4_v3d_debugfs_ident, NULL); 463 vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset); 464 465 return 0; 466 } 467 468 static void vc4_v3d_unbind(struct device *dev, struct device *master, 469 void *data) 470 { 471 struct drm_device *drm = dev_get_drvdata(master); 472 struct vc4_dev *vc4 = to_vc4_dev(drm); 473 474 pm_runtime_disable(dev); 475 476 drm_irq_uninstall(drm); 477 478 /* Disable the binner's overflow memory address, so the next 479 * driver probe (if any) doesn't try to reuse our old 480 * allocation. 481 */ 482 V3D_WRITE(V3D_BPOA, 0); 483 V3D_WRITE(V3D_BPOS, 0); 484 485 vc4->v3d = NULL; 486 } 487 488 static const struct dev_pm_ops vc4_v3d_pm_ops = { 489 SET_RUNTIME_PM_OPS(vc4_v3d_runtime_suspend, vc4_v3d_runtime_resume, NULL) 490 }; 491 492 static const struct component_ops vc4_v3d_ops = { 493 .bind = vc4_v3d_bind, 494 .unbind = vc4_v3d_unbind, 495 }; 496 497 static int vc4_v3d_dev_probe(struct platform_device *pdev) 498 { 499 return component_add(&pdev->dev, &vc4_v3d_ops); 500 } 501 502 static int vc4_v3d_dev_remove(struct platform_device *pdev) 503 { 504 component_del(&pdev->dev, &vc4_v3d_ops); 505 return 0; 506 } 507 508 const struct of_device_id vc4_v3d_dt_match[] = { 509 { .compatible = "brcm,bcm2835-v3d" }, 510 { .compatible = "brcm,cygnus-v3d" }, 511 { .compatible = "brcm,vc4-v3d" }, 512 {} 513 }; 514 515 struct platform_driver vc4_v3d_driver = { 516 .probe = vc4_v3d_dev_probe, 517 .remove = vc4_v3d_dev_remove, 518 .driver = { 519 .name = "vc4_v3d", 520 .of_match_table = vc4_v3d_dt_match, 521 .pm = &vc4_v3d_pm_ops, 522 }, 523 }; 524