1 /* 2 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include <linux/clk.h> 20 #include <linux/component.h> 21 #include <linux/pm_runtime.h> 22 #include "vc4_drv.h" 23 #include "vc4_regs.h" 24 25 static const struct debugfs_reg32 v3d_regs[] = { 26 VC4_REG32(V3D_IDENT0), 27 VC4_REG32(V3D_IDENT1), 28 VC4_REG32(V3D_IDENT2), 29 VC4_REG32(V3D_SCRATCH), 30 VC4_REG32(V3D_L2CACTL), 31 VC4_REG32(V3D_SLCACTL), 32 VC4_REG32(V3D_INTCTL), 33 VC4_REG32(V3D_INTENA), 34 VC4_REG32(V3D_INTDIS), 35 VC4_REG32(V3D_CT0CS), 36 VC4_REG32(V3D_CT1CS), 37 VC4_REG32(V3D_CT0EA), 38 VC4_REG32(V3D_CT1EA), 39 VC4_REG32(V3D_CT0CA), 40 VC4_REG32(V3D_CT1CA), 41 VC4_REG32(V3D_CT00RA0), 42 VC4_REG32(V3D_CT01RA0), 43 VC4_REG32(V3D_CT0LC), 44 VC4_REG32(V3D_CT1LC), 45 VC4_REG32(V3D_CT0PC), 46 VC4_REG32(V3D_CT1PC), 47 VC4_REG32(V3D_PCS), 48 VC4_REG32(V3D_BFC), 49 VC4_REG32(V3D_RFC), 50 VC4_REG32(V3D_BPCA), 51 VC4_REG32(V3D_BPCS), 52 VC4_REG32(V3D_BPOA), 53 VC4_REG32(V3D_BPOS), 54 VC4_REG32(V3D_BXCF), 55 VC4_REG32(V3D_SQRSV0), 56 VC4_REG32(V3D_SQRSV1), 57 VC4_REG32(V3D_SQCNTL), 58 VC4_REG32(V3D_SRQPC), 59 VC4_REG32(V3D_SRQUA), 60 VC4_REG32(V3D_SRQUL), 61 VC4_REG32(V3D_SRQCS), 62 VC4_REG32(V3D_VPACNTL), 63 VC4_REG32(V3D_VPMBASE), 64 VC4_REG32(V3D_PCTRC), 65 VC4_REG32(V3D_PCTRE), 66 VC4_REG32(V3D_PCTR(0)), 67 VC4_REG32(V3D_PCTRS(0)), 68 VC4_REG32(V3D_PCTR(1)), 69 VC4_REG32(V3D_PCTRS(1)), 70 VC4_REG32(V3D_PCTR(2)), 71 VC4_REG32(V3D_PCTRS(2)), 72 VC4_REG32(V3D_PCTR(3)), 73 VC4_REG32(V3D_PCTRS(3)), 74 VC4_REG32(V3D_PCTR(4)), 75 VC4_REG32(V3D_PCTRS(4)), 76 VC4_REG32(V3D_PCTR(5)), 77 VC4_REG32(V3D_PCTRS(5)), 78 VC4_REG32(V3D_PCTR(6)), 79 VC4_REG32(V3D_PCTRS(6)), 80 VC4_REG32(V3D_PCTR(7)), 81 VC4_REG32(V3D_PCTRS(7)), 82 VC4_REG32(V3D_PCTR(8)), 83 VC4_REG32(V3D_PCTRS(8)), 84 VC4_REG32(V3D_PCTR(9)), 85 VC4_REG32(V3D_PCTRS(9)), 86 VC4_REG32(V3D_PCTR(10)), 87 VC4_REG32(V3D_PCTRS(10)), 88 VC4_REG32(V3D_PCTR(11)), 89 VC4_REG32(V3D_PCTRS(11)), 90 VC4_REG32(V3D_PCTR(12)), 91 VC4_REG32(V3D_PCTRS(12)), 92 VC4_REG32(V3D_PCTR(13)), 93 VC4_REG32(V3D_PCTRS(13)), 94 VC4_REG32(V3D_PCTR(14)), 95 VC4_REG32(V3D_PCTRS(14)), 96 VC4_REG32(V3D_PCTR(15)), 97 VC4_REG32(V3D_PCTRS(15)), 98 VC4_REG32(V3D_DBGE), 99 VC4_REG32(V3D_FDBGO), 100 VC4_REG32(V3D_FDBGB), 101 VC4_REG32(V3D_FDBGR), 102 VC4_REG32(V3D_FDBGS), 103 VC4_REG32(V3D_ERRSTAT), 104 }; 105 106 static int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused) 107 { 108 struct drm_info_node *node = (struct drm_info_node *)m->private; 109 struct drm_device *dev = node->minor->dev; 110 struct vc4_dev *vc4 = to_vc4_dev(dev); 111 int ret = vc4_v3d_pm_get(vc4); 112 113 if (ret == 0) { 114 uint32_t ident1 = V3D_READ(V3D_IDENT1); 115 uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC); 116 uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS); 117 uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS); 118 119 seq_printf(m, "Revision: %d\n", 120 VC4_GET_FIELD(ident1, V3D_IDENT1_REV)); 121 seq_printf(m, "Slices: %d\n", nslc); 122 seq_printf(m, "TMUs: %d\n", nslc * tups); 123 seq_printf(m, "QPUs: %d\n", nslc * qups); 124 seq_printf(m, "Semaphores: %d\n", 125 VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM)); 126 vc4_v3d_pm_put(vc4); 127 } 128 129 return 0; 130 } 131 132 /** 133 * Wraps pm_runtime_get_sync() in a refcount, so that we can reliably 134 * get the pm_runtime refcount to 0 in vc4_reset(). 135 */ 136 int 137 vc4_v3d_pm_get(struct vc4_dev *vc4) 138 { 139 mutex_lock(&vc4->power_lock); 140 if (vc4->power_refcount++ == 0) { 141 int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev); 142 143 if (ret < 0) { 144 vc4->power_refcount--; 145 mutex_unlock(&vc4->power_lock); 146 return ret; 147 } 148 } 149 mutex_unlock(&vc4->power_lock); 150 151 return 0; 152 } 153 154 void 155 vc4_v3d_pm_put(struct vc4_dev *vc4) 156 { 157 mutex_lock(&vc4->power_lock); 158 if (--vc4->power_refcount == 0) { 159 pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev); 160 pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev); 161 } 162 mutex_unlock(&vc4->power_lock); 163 } 164 165 static void vc4_v3d_init_hw(struct drm_device *dev) 166 { 167 struct vc4_dev *vc4 = to_vc4_dev(dev); 168 169 /* Take all the memory that would have been reserved for user 170 * QPU programs, since we don't have an interface for running 171 * them, anyway. 172 */ 173 V3D_WRITE(V3D_VPMBASE, 0); 174 } 175 176 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4) 177 { 178 struct drm_device *dev = vc4->dev; 179 unsigned long irqflags; 180 int slot; 181 uint64_t seqno = 0; 182 struct vc4_exec_info *exec; 183 184 try_again: 185 spin_lock_irqsave(&vc4->job_lock, irqflags); 186 slot = ffs(~vc4->bin_alloc_used); 187 if (slot != 0) { 188 /* Switch from ffs() bit index to a 0-based index. */ 189 slot--; 190 vc4->bin_alloc_used |= BIT(slot); 191 spin_unlock_irqrestore(&vc4->job_lock, irqflags); 192 return slot; 193 } 194 195 /* Couldn't find an open slot. Wait for render to complete 196 * and try again. 197 */ 198 exec = vc4_last_render_job(vc4); 199 if (exec) 200 seqno = exec->seqno; 201 spin_unlock_irqrestore(&vc4->job_lock, irqflags); 202 203 if (seqno) { 204 int ret = vc4_wait_for_seqno(dev, seqno, ~0ull, true); 205 206 if (ret == 0) 207 goto try_again; 208 209 return ret; 210 } 211 212 return -ENOMEM; 213 } 214 215 /** 216 * bin_bo_alloc() - allocates the memory that will be used for 217 * tile binning. 218 * 219 * The binner has a limitation that the addresses in the tile state 220 * buffer that point into the tile alloc buffer or binner overflow 221 * memory only have 28 bits (256MB), and the top 4 on the bus for 222 * tile alloc references end up coming from the tile state buffer's 223 * address. 224 * 225 * To work around this, we allocate a single large buffer while V3D is 226 * in use, make sure that it has the top 4 bits constant across its 227 * entire extent, and then put the tile state, tile alloc, and binner 228 * overflow memory inside that buffer. 229 * 230 * This creates a limitation where we may not be able to execute a job 231 * if it doesn't fit within the buffer that we allocated up front. 232 * However, it turns out that 16MB is "enough for anybody", and 233 * real-world applications run into allocation failures from the 234 * overall CMA pool before they make scenes complicated enough to run 235 * out of bin space. 236 */ 237 static int bin_bo_alloc(struct vc4_dev *vc4) 238 { 239 struct vc4_v3d *v3d = vc4->v3d; 240 uint32_t size = 16 * 1024 * 1024; 241 int ret = 0; 242 struct list_head list; 243 244 if (!v3d) 245 return -ENODEV; 246 247 /* We may need to try allocating more than once to get a BO 248 * that doesn't cross 256MB. Track the ones we've allocated 249 * that failed so far, so that we can free them when we've got 250 * one that succeeded (if we freed them right away, our next 251 * allocation would probably be the same chunk of memory). 252 */ 253 INIT_LIST_HEAD(&list); 254 255 while (true) { 256 struct vc4_bo *bo = vc4_bo_create(vc4->dev, size, true, 257 VC4_BO_TYPE_BIN); 258 259 if (IS_ERR(bo)) { 260 ret = PTR_ERR(bo); 261 262 dev_err(&v3d->pdev->dev, 263 "Failed to allocate memory for tile binning: " 264 "%d. You may need to enable CMA or give it " 265 "more memory.", 266 ret); 267 break; 268 } 269 270 /* Check if this BO won't trigger the addressing bug. */ 271 if ((bo->base.paddr & 0xf0000000) == 272 ((bo->base.paddr + bo->base.base.size - 1) & 0xf0000000)) { 273 vc4->bin_bo = bo; 274 275 /* Set up for allocating 512KB chunks of 276 * binner memory. The biggest allocation we 277 * need to do is for the initial tile alloc + 278 * tile state buffer. We can render to a 279 * maximum of ((2048*2048) / (32*32) = 4096 280 * tiles in a frame (until we do floating 281 * point rendering, at which point it would be 282 * 8192). Tile state is 48b/tile (rounded to 283 * a page), and tile alloc is 32b/tile 284 * (rounded to a page), plus a page of extra, 285 * for a total of 320kb for our worst-case. 286 * We choose 512kb so that it divides evenly 287 * into our 16MB, and the rest of the 512kb 288 * will be used as storage for the overflow 289 * from the initial 32b CL per bin. 290 */ 291 vc4->bin_alloc_size = 512 * 1024; 292 vc4->bin_alloc_used = 0; 293 vc4->bin_alloc_overflow = 0; 294 WARN_ON_ONCE(sizeof(vc4->bin_alloc_used) * 8 != 295 bo->base.base.size / vc4->bin_alloc_size); 296 297 kref_init(&vc4->bin_bo_kref); 298 299 /* Enable the out-of-memory interrupt to set our 300 * newly-allocated binner BO, potentially from an 301 * already-pending-but-masked interrupt. 302 */ 303 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM); 304 305 break; 306 } 307 308 /* Put it on the list to free later, and try again. */ 309 list_add(&bo->unref_head, &list); 310 } 311 312 /* Free all the BOs we allocated but didn't choose. */ 313 while (!list_empty(&list)) { 314 struct vc4_bo *bo = list_last_entry(&list, 315 struct vc4_bo, unref_head); 316 317 list_del(&bo->unref_head); 318 drm_gem_object_put_unlocked(&bo->base.base); 319 } 320 321 return ret; 322 } 323 324 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used) 325 { 326 int ret = 0; 327 328 mutex_lock(&vc4->bin_bo_lock); 329 330 if (used && *used) 331 goto complete; 332 333 if (vc4->bin_bo) 334 kref_get(&vc4->bin_bo_kref); 335 else 336 ret = bin_bo_alloc(vc4); 337 338 if (ret == 0 && used) 339 *used = true; 340 341 complete: 342 mutex_unlock(&vc4->bin_bo_lock); 343 344 return ret; 345 } 346 347 static void bin_bo_release(struct kref *ref) 348 { 349 struct vc4_dev *vc4 = container_of(ref, struct vc4_dev, bin_bo_kref); 350 351 if (WARN_ON_ONCE(!vc4->bin_bo)) 352 return; 353 354 drm_gem_object_put_unlocked(&vc4->bin_bo->base.base); 355 vc4->bin_bo = NULL; 356 } 357 358 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4) 359 { 360 mutex_lock(&vc4->bin_bo_lock); 361 kref_put(&vc4->bin_bo_kref, bin_bo_release); 362 mutex_unlock(&vc4->bin_bo_lock); 363 } 364 365 #ifdef CONFIG_PM 366 static int vc4_v3d_runtime_suspend(struct device *dev) 367 { 368 struct vc4_v3d *v3d = dev_get_drvdata(dev); 369 struct vc4_dev *vc4 = v3d->vc4; 370 371 vc4_irq_uninstall(vc4->dev); 372 373 clk_disable_unprepare(v3d->clk); 374 375 return 0; 376 } 377 378 static int vc4_v3d_runtime_resume(struct device *dev) 379 { 380 struct vc4_v3d *v3d = dev_get_drvdata(dev); 381 struct vc4_dev *vc4 = v3d->vc4; 382 int ret; 383 384 ret = clk_prepare_enable(v3d->clk); 385 if (ret != 0) 386 return ret; 387 388 vc4_v3d_init_hw(vc4->dev); 389 390 /* We disabled the IRQ as part of vc4_irq_uninstall in suspend. */ 391 enable_irq(vc4->dev->irq); 392 vc4_irq_postinstall(vc4->dev); 393 394 return 0; 395 } 396 #endif 397 398 static int vc4_v3d_bind(struct device *dev, struct device *master, void *data) 399 { 400 struct platform_device *pdev = to_platform_device(dev); 401 struct drm_device *drm = dev_get_drvdata(master); 402 struct vc4_dev *vc4 = to_vc4_dev(drm); 403 struct vc4_v3d *v3d = NULL; 404 int ret; 405 406 v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL); 407 if (!v3d) 408 return -ENOMEM; 409 410 dev_set_drvdata(dev, v3d); 411 412 v3d->pdev = pdev; 413 414 v3d->regs = vc4_ioremap_regs(pdev, 0); 415 if (IS_ERR(v3d->regs)) 416 return PTR_ERR(v3d->regs); 417 v3d->regset.base = v3d->regs; 418 v3d->regset.regs = v3d_regs; 419 v3d->regset.nregs = ARRAY_SIZE(v3d_regs); 420 421 vc4->v3d = v3d; 422 v3d->vc4 = vc4; 423 424 v3d->clk = devm_clk_get(dev, NULL); 425 if (IS_ERR(v3d->clk)) { 426 int ret = PTR_ERR(v3d->clk); 427 428 if (ret == -ENOENT) { 429 /* bcm2835 didn't have a clock reference in the DT. */ 430 ret = 0; 431 v3d->clk = NULL; 432 } else { 433 if (ret != -EPROBE_DEFER) 434 dev_err(dev, "Failed to get V3D clock: %d\n", 435 ret); 436 return ret; 437 } 438 } 439 440 if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) { 441 DRM_ERROR("V3D_IDENT0 read 0x%08x instead of 0x%08x\n", 442 V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0); 443 return -EINVAL; 444 } 445 446 ret = clk_prepare_enable(v3d->clk); 447 if (ret != 0) 448 return ret; 449 450 /* Reset the binner overflow address/size at setup, to be sure 451 * we don't reuse an old one. 452 */ 453 V3D_WRITE(V3D_BPOA, 0); 454 V3D_WRITE(V3D_BPOS, 0); 455 456 vc4_v3d_init_hw(drm); 457 458 ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); 459 if (ret) { 460 DRM_ERROR("Failed to install IRQ handler\n"); 461 return ret; 462 } 463 464 pm_runtime_set_active(dev); 465 pm_runtime_use_autosuspend(dev); 466 pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */ 467 pm_runtime_enable(dev); 468 469 vc4_debugfs_add_file(drm, "v3d_ident", vc4_v3d_debugfs_ident, NULL); 470 vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset); 471 472 return 0; 473 } 474 475 static void vc4_v3d_unbind(struct device *dev, struct device *master, 476 void *data) 477 { 478 struct drm_device *drm = dev_get_drvdata(master); 479 struct vc4_dev *vc4 = to_vc4_dev(drm); 480 481 pm_runtime_disable(dev); 482 483 drm_irq_uninstall(drm); 484 485 /* Disable the binner's overflow memory address, so the next 486 * driver probe (if any) doesn't try to reuse our old 487 * allocation. 488 */ 489 V3D_WRITE(V3D_BPOA, 0); 490 V3D_WRITE(V3D_BPOS, 0); 491 492 vc4->v3d = NULL; 493 } 494 495 static const struct dev_pm_ops vc4_v3d_pm_ops = { 496 SET_RUNTIME_PM_OPS(vc4_v3d_runtime_suspend, vc4_v3d_runtime_resume, NULL) 497 }; 498 499 static const struct component_ops vc4_v3d_ops = { 500 .bind = vc4_v3d_bind, 501 .unbind = vc4_v3d_unbind, 502 }; 503 504 static int vc4_v3d_dev_probe(struct platform_device *pdev) 505 { 506 return component_add(&pdev->dev, &vc4_v3d_ops); 507 } 508 509 static int vc4_v3d_dev_remove(struct platform_device *pdev) 510 { 511 component_del(&pdev->dev, &vc4_v3d_ops); 512 return 0; 513 } 514 515 const struct of_device_id vc4_v3d_dt_match[] = { 516 { .compatible = "brcm,bcm2835-v3d" }, 517 { .compatible = "brcm,cygnus-v3d" }, 518 { .compatible = "brcm,vc4-v3d" }, 519 {} 520 }; 521 522 struct platform_driver vc4_v3d_driver = { 523 .probe = vc4_v3d_dev_probe, 524 .remove = vc4_v3d_dev_remove, 525 .driver = { 526 .name = "vc4_v3d", 527 .of_match_table = vc4_v3d_dt_match, 528 .pm = &vc4_v3d_pm_ops, 529 }, 530 }; 531