1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/pm_runtime.h> 11 #include "vc4_drv.h" 12 #include "vc4_regs.h" 13 14 static const struct debugfs_reg32 v3d_regs[] = { 15 VC4_REG32(V3D_IDENT0), 16 VC4_REG32(V3D_IDENT1), 17 VC4_REG32(V3D_IDENT2), 18 VC4_REG32(V3D_SCRATCH), 19 VC4_REG32(V3D_L2CACTL), 20 VC4_REG32(V3D_SLCACTL), 21 VC4_REG32(V3D_INTCTL), 22 VC4_REG32(V3D_INTENA), 23 VC4_REG32(V3D_INTDIS), 24 VC4_REG32(V3D_CT0CS), 25 VC4_REG32(V3D_CT1CS), 26 VC4_REG32(V3D_CT0EA), 27 VC4_REG32(V3D_CT1EA), 28 VC4_REG32(V3D_CT0CA), 29 VC4_REG32(V3D_CT1CA), 30 VC4_REG32(V3D_CT00RA0), 31 VC4_REG32(V3D_CT01RA0), 32 VC4_REG32(V3D_CT0LC), 33 VC4_REG32(V3D_CT1LC), 34 VC4_REG32(V3D_CT0PC), 35 VC4_REG32(V3D_CT1PC), 36 VC4_REG32(V3D_PCS), 37 VC4_REG32(V3D_BFC), 38 VC4_REG32(V3D_RFC), 39 VC4_REG32(V3D_BPCA), 40 VC4_REG32(V3D_BPCS), 41 VC4_REG32(V3D_BPOA), 42 VC4_REG32(V3D_BPOS), 43 VC4_REG32(V3D_BXCF), 44 VC4_REG32(V3D_SQRSV0), 45 VC4_REG32(V3D_SQRSV1), 46 VC4_REG32(V3D_SQCNTL), 47 VC4_REG32(V3D_SRQPC), 48 VC4_REG32(V3D_SRQUA), 49 VC4_REG32(V3D_SRQUL), 50 VC4_REG32(V3D_SRQCS), 51 VC4_REG32(V3D_VPACNTL), 52 VC4_REG32(V3D_VPMBASE), 53 VC4_REG32(V3D_PCTRC), 54 VC4_REG32(V3D_PCTRE), 55 VC4_REG32(V3D_PCTR(0)), 56 VC4_REG32(V3D_PCTRS(0)), 57 VC4_REG32(V3D_PCTR(1)), 58 VC4_REG32(V3D_PCTRS(1)), 59 VC4_REG32(V3D_PCTR(2)), 60 VC4_REG32(V3D_PCTRS(2)), 61 VC4_REG32(V3D_PCTR(3)), 62 VC4_REG32(V3D_PCTRS(3)), 63 VC4_REG32(V3D_PCTR(4)), 64 VC4_REG32(V3D_PCTRS(4)), 65 VC4_REG32(V3D_PCTR(5)), 66 VC4_REG32(V3D_PCTRS(5)), 67 VC4_REG32(V3D_PCTR(6)), 68 VC4_REG32(V3D_PCTRS(6)), 69 VC4_REG32(V3D_PCTR(7)), 70 VC4_REG32(V3D_PCTRS(7)), 71 VC4_REG32(V3D_PCTR(8)), 72 VC4_REG32(V3D_PCTRS(8)), 73 VC4_REG32(V3D_PCTR(9)), 74 VC4_REG32(V3D_PCTRS(9)), 75 VC4_REG32(V3D_PCTR(10)), 76 VC4_REG32(V3D_PCTRS(10)), 77 VC4_REG32(V3D_PCTR(11)), 78 VC4_REG32(V3D_PCTRS(11)), 79 VC4_REG32(V3D_PCTR(12)), 80 VC4_REG32(V3D_PCTRS(12)), 81 VC4_REG32(V3D_PCTR(13)), 82 VC4_REG32(V3D_PCTRS(13)), 83 VC4_REG32(V3D_PCTR(14)), 84 VC4_REG32(V3D_PCTRS(14)), 85 VC4_REG32(V3D_PCTR(15)), 86 VC4_REG32(V3D_PCTRS(15)), 87 VC4_REG32(V3D_DBGE), 88 VC4_REG32(V3D_FDBGO), 89 VC4_REG32(V3D_FDBGB), 90 VC4_REG32(V3D_FDBGR), 91 VC4_REG32(V3D_FDBGS), 92 VC4_REG32(V3D_ERRSTAT), 93 }; 94 95 static int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused) 96 { 97 struct drm_info_node *node = (struct drm_info_node *)m->private; 98 struct drm_device *dev = node->minor->dev; 99 struct vc4_dev *vc4 = to_vc4_dev(dev); 100 int ret = vc4_v3d_pm_get(vc4); 101 102 if (ret == 0) { 103 uint32_t ident1 = V3D_READ(V3D_IDENT1); 104 uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC); 105 uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS); 106 uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS); 107 108 seq_printf(m, "Revision: %d\n", 109 VC4_GET_FIELD(ident1, V3D_IDENT1_REV)); 110 seq_printf(m, "Slices: %d\n", nslc); 111 seq_printf(m, "TMUs: %d\n", nslc * tups); 112 seq_printf(m, "QPUs: %d\n", nslc * qups); 113 seq_printf(m, "Semaphores: %d\n", 114 VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM)); 115 vc4_v3d_pm_put(vc4); 116 } 117 118 return 0; 119 } 120 121 /** 122 * Wraps pm_runtime_get_sync() in a refcount, so that we can reliably 123 * get the pm_runtime refcount to 0 in vc4_reset(). 124 */ 125 int 126 vc4_v3d_pm_get(struct vc4_dev *vc4) 127 { 128 mutex_lock(&vc4->power_lock); 129 if (vc4->power_refcount++ == 0) { 130 int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev); 131 132 if (ret < 0) { 133 vc4->power_refcount--; 134 mutex_unlock(&vc4->power_lock); 135 return ret; 136 } 137 } 138 mutex_unlock(&vc4->power_lock); 139 140 return 0; 141 } 142 143 void 144 vc4_v3d_pm_put(struct vc4_dev *vc4) 145 { 146 mutex_lock(&vc4->power_lock); 147 if (--vc4->power_refcount == 0) { 148 pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev); 149 pm_runtime_put_autosuspend(&vc4->v3d->pdev->dev); 150 } 151 mutex_unlock(&vc4->power_lock); 152 } 153 154 static void vc4_v3d_init_hw(struct drm_device *dev) 155 { 156 struct vc4_dev *vc4 = to_vc4_dev(dev); 157 158 /* Take all the memory that would have been reserved for user 159 * QPU programs, since we don't have an interface for running 160 * them, anyway. 161 */ 162 V3D_WRITE(V3D_VPMBASE, 0); 163 } 164 165 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4) 166 { 167 struct drm_device *dev = vc4->dev; 168 unsigned long irqflags; 169 int slot; 170 uint64_t seqno = 0; 171 struct vc4_exec_info *exec; 172 173 try_again: 174 spin_lock_irqsave(&vc4->job_lock, irqflags); 175 slot = ffs(~vc4->bin_alloc_used); 176 if (slot != 0) { 177 /* Switch from ffs() bit index to a 0-based index. */ 178 slot--; 179 vc4->bin_alloc_used |= BIT(slot); 180 spin_unlock_irqrestore(&vc4->job_lock, irqflags); 181 return slot; 182 } 183 184 /* Couldn't find an open slot. Wait for render to complete 185 * and try again. 186 */ 187 exec = vc4_last_render_job(vc4); 188 if (exec) 189 seqno = exec->seqno; 190 spin_unlock_irqrestore(&vc4->job_lock, irqflags); 191 192 if (seqno) { 193 int ret = vc4_wait_for_seqno(dev, seqno, ~0ull, true); 194 195 if (ret == 0) 196 goto try_again; 197 198 return ret; 199 } 200 201 return -ENOMEM; 202 } 203 204 /** 205 * bin_bo_alloc() - allocates the memory that will be used for 206 * tile binning. 207 * 208 * The binner has a limitation that the addresses in the tile state 209 * buffer that point into the tile alloc buffer or binner overflow 210 * memory only have 28 bits (256MB), and the top 4 on the bus for 211 * tile alloc references end up coming from the tile state buffer's 212 * address. 213 * 214 * To work around this, we allocate a single large buffer while V3D is 215 * in use, make sure that it has the top 4 bits constant across its 216 * entire extent, and then put the tile state, tile alloc, and binner 217 * overflow memory inside that buffer. 218 * 219 * This creates a limitation where we may not be able to execute a job 220 * if it doesn't fit within the buffer that we allocated up front. 221 * However, it turns out that 16MB is "enough for anybody", and 222 * real-world applications run into allocation failures from the 223 * overall CMA pool before they make scenes complicated enough to run 224 * out of bin space. 225 */ 226 static int bin_bo_alloc(struct vc4_dev *vc4) 227 { 228 struct vc4_v3d *v3d = vc4->v3d; 229 uint32_t size = 16 * 1024 * 1024; 230 int ret = 0; 231 struct list_head list; 232 233 if (!v3d) 234 return -ENODEV; 235 236 /* We may need to try allocating more than once to get a BO 237 * that doesn't cross 256MB. Track the ones we've allocated 238 * that failed so far, so that we can free them when we've got 239 * one that succeeded (if we freed them right away, our next 240 * allocation would probably be the same chunk of memory). 241 */ 242 INIT_LIST_HEAD(&list); 243 244 while (true) { 245 struct vc4_bo *bo = vc4_bo_create(vc4->dev, size, true, 246 VC4_BO_TYPE_BIN); 247 248 if (IS_ERR(bo)) { 249 ret = PTR_ERR(bo); 250 251 dev_err(&v3d->pdev->dev, 252 "Failed to allocate memory for tile binning: " 253 "%d. You may need to enable CMA or give it " 254 "more memory.", 255 ret); 256 break; 257 } 258 259 /* Check if this BO won't trigger the addressing bug. */ 260 if ((bo->base.paddr & 0xf0000000) == 261 ((bo->base.paddr + bo->base.base.size - 1) & 0xf0000000)) { 262 vc4->bin_bo = bo; 263 264 /* Set up for allocating 512KB chunks of 265 * binner memory. The biggest allocation we 266 * need to do is for the initial tile alloc + 267 * tile state buffer. We can render to a 268 * maximum of ((2048*2048) / (32*32) = 4096 269 * tiles in a frame (until we do floating 270 * point rendering, at which point it would be 271 * 8192). Tile state is 48b/tile (rounded to 272 * a page), and tile alloc is 32b/tile 273 * (rounded to a page), plus a page of extra, 274 * for a total of 320kb for our worst-case. 275 * We choose 512kb so that it divides evenly 276 * into our 16MB, and the rest of the 512kb 277 * will be used as storage for the overflow 278 * from the initial 32b CL per bin. 279 */ 280 vc4->bin_alloc_size = 512 * 1024; 281 vc4->bin_alloc_used = 0; 282 vc4->bin_alloc_overflow = 0; 283 WARN_ON_ONCE(sizeof(vc4->bin_alloc_used) * 8 != 284 bo->base.base.size / vc4->bin_alloc_size); 285 286 kref_init(&vc4->bin_bo_kref); 287 288 /* Enable the out-of-memory interrupt to set our 289 * newly-allocated binner BO, potentially from an 290 * already-pending-but-masked interrupt. 291 */ 292 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM); 293 294 break; 295 } 296 297 /* Put it on the list to free later, and try again. */ 298 list_add(&bo->unref_head, &list); 299 } 300 301 /* Free all the BOs we allocated but didn't choose. */ 302 while (!list_empty(&list)) { 303 struct vc4_bo *bo = list_last_entry(&list, 304 struct vc4_bo, unref_head); 305 306 list_del(&bo->unref_head); 307 drm_gem_object_put_unlocked(&bo->base.base); 308 } 309 310 return ret; 311 } 312 313 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used) 314 { 315 int ret = 0; 316 317 mutex_lock(&vc4->bin_bo_lock); 318 319 if (used && *used) 320 goto complete; 321 322 if (vc4->bin_bo) 323 kref_get(&vc4->bin_bo_kref); 324 else 325 ret = bin_bo_alloc(vc4); 326 327 if (ret == 0 && used) 328 *used = true; 329 330 complete: 331 mutex_unlock(&vc4->bin_bo_lock); 332 333 return ret; 334 } 335 336 static void bin_bo_release(struct kref *ref) 337 { 338 struct vc4_dev *vc4 = container_of(ref, struct vc4_dev, bin_bo_kref); 339 340 if (WARN_ON_ONCE(!vc4->bin_bo)) 341 return; 342 343 drm_gem_object_put_unlocked(&vc4->bin_bo->base.base); 344 vc4->bin_bo = NULL; 345 } 346 347 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4) 348 { 349 mutex_lock(&vc4->bin_bo_lock); 350 kref_put(&vc4->bin_bo_kref, bin_bo_release); 351 mutex_unlock(&vc4->bin_bo_lock); 352 } 353 354 #ifdef CONFIG_PM 355 static int vc4_v3d_runtime_suspend(struct device *dev) 356 { 357 struct vc4_v3d *v3d = dev_get_drvdata(dev); 358 struct vc4_dev *vc4 = v3d->vc4; 359 360 vc4_irq_uninstall(vc4->dev); 361 362 clk_disable_unprepare(v3d->clk); 363 364 return 0; 365 } 366 367 static int vc4_v3d_runtime_resume(struct device *dev) 368 { 369 struct vc4_v3d *v3d = dev_get_drvdata(dev); 370 struct vc4_dev *vc4 = v3d->vc4; 371 int ret; 372 373 ret = clk_prepare_enable(v3d->clk); 374 if (ret != 0) 375 return ret; 376 377 vc4_v3d_init_hw(vc4->dev); 378 379 /* We disabled the IRQ as part of vc4_irq_uninstall in suspend. */ 380 enable_irq(vc4->dev->irq); 381 vc4_irq_postinstall(vc4->dev); 382 383 return 0; 384 } 385 #endif 386 387 static int vc4_v3d_bind(struct device *dev, struct device *master, void *data) 388 { 389 struct platform_device *pdev = to_platform_device(dev); 390 struct drm_device *drm = dev_get_drvdata(master); 391 struct vc4_dev *vc4 = to_vc4_dev(drm); 392 struct vc4_v3d *v3d = NULL; 393 int ret; 394 395 v3d = devm_kzalloc(&pdev->dev, sizeof(*v3d), GFP_KERNEL); 396 if (!v3d) 397 return -ENOMEM; 398 399 dev_set_drvdata(dev, v3d); 400 401 v3d->pdev = pdev; 402 403 v3d->regs = vc4_ioremap_regs(pdev, 0); 404 if (IS_ERR(v3d->regs)) 405 return PTR_ERR(v3d->regs); 406 v3d->regset.base = v3d->regs; 407 v3d->regset.regs = v3d_regs; 408 v3d->regset.nregs = ARRAY_SIZE(v3d_regs); 409 410 vc4->v3d = v3d; 411 v3d->vc4 = vc4; 412 413 v3d->clk = devm_clk_get(dev, NULL); 414 if (IS_ERR(v3d->clk)) { 415 int ret = PTR_ERR(v3d->clk); 416 417 if (ret == -ENOENT) { 418 /* bcm2835 didn't have a clock reference in the DT. */ 419 ret = 0; 420 v3d->clk = NULL; 421 } else { 422 if (ret != -EPROBE_DEFER) 423 dev_err(dev, "Failed to get V3D clock: %d\n", 424 ret); 425 return ret; 426 } 427 } 428 429 if (V3D_READ(V3D_IDENT0) != V3D_EXPECTED_IDENT0) { 430 DRM_ERROR("V3D_IDENT0 read 0x%08x instead of 0x%08x\n", 431 V3D_READ(V3D_IDENT0), V3D_EXPECTED_IDENT0); 432 return -EINVAL; 433 } 434 435 ret = clk_prepare_enable(v3d->clk); 436 if (ret != 0) 437 return ret; 438 439 /* Reset the binner overflow address/size at setup, to be sure 440 * we don't reuse an old one. 441 */ 442 V3D_WRITE(V3D_BPOA, 0); 443 V3D_WRITE(V3D_BPOS, 0); 444 445 vc4_v3d_init_hw(drm); 446 447 ret = drm_irq_install(drm, platform_get_irq(pdev, 0)); 448 if (ret) { 449 DRM_ERROR("Failed to install IRQ handler\n"); 450 return ret; 451 } 452 453 pm_runtime_set_active(dev); 454 pm_runtime_use_autosuspend(dev); 455 pm_runtime_set_autosuspend_delay(dev, 40); /* a little over 2 frames. */ 456 pm_runtime_enable(dev); 457 458 vc4_debugfs_add_file(drm, "v3d_ident", vc4_v3d_debugfs_ident, NULL); 459 vc4_debugfs_add_regset32(drm, "v3d_regs", &v3d->regset); 460 461 return 0; 462 } 463 464 static void vc4_v3d_unbind(struct device *dev, struct device *master, 465 void *data) 466 { 467 struct drm_device *drm = dev_get_drvdata(master); 468 struct vc4_dev *vc4 = to_vc4_dev(drm); 469 470 pm_runtime_disable(dev); 471 472 drm_irq_uninstall(drm); 473 474 /* Disable the binner's overflow memory address, so the next 475 * driver probe (if any) doesn't try to reuse our old 476 * allocation. 477 */ 478 V3D_WRITE(V3D_BPOA, 0); 479 V3D_WRITE(V3D_BPOS, 0); 480 481 vc4->v3d = NULL; 482 } 483 484 static const struct dev_pm_ops vc4_v3d_pm_ops = { 485 SET_RUNTIME_PM_OPS(vc4_v3d_runtime_suspend, vc4_v3d_runtime_resume, NULL) 486 }; 487 488 static const struct component_ops vc4_v3d_ops = { 489 .bind = vc4_v3d_bind, 490 .unbind = vc4_v3d_unbind, 491 }; 492 493 static int vc4_v3d_dev_probe(struct platform_device *pdev) 494 { 495 return component_add(&pdev->dev, &vc4_v3d_ops); 496 } 497 498 static int vc4_v3d_dev_remove(struct platform_device *pdev) 499 { 500 component_del(&pdev->dev, &vc4_v3d_ops); 501 return 0; 502 } 503 504 const struct of_device_id vc4_v3d_dt_match[] = { 505 { .compatible = "brcm,bcm2835-v3d" }, 506 { .compatible = "brcm,cygnus-v3d" }, 507 { .compatible = "brcm,vc4-v3d" }, 508 {} 509 }; 510 511 struct platform_driver vc4_v3d_driver = { 512 .probe = vc4_v3d_dev_probe, 513 .remove = vc4_v3d_dev_remove, 514 .driver = { 515 .name = "vc4_v3d", 516 .of_match_table = vc4_v3d_dt_match, 517 .pm = &vc4_v3d_pm_ops, 518 }, 519 }; 520