1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright © 2018 Broadcom 4 * 5 * Authors: 6 * Eric Anholt <eric@anholt.net> 7 * Boris Brezillon <boris.brezillon@bootlin.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/component.h> 12 #include <linux/of_graph.h> 13 #include <linux/of_platform.h> 14 #include <linux/pm_runtime.h> 15 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_fb_cma_helper.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_framebuffer.h> 22 #include <drm/drm_panel.h> 23 #include <drm/drm_probe_helper.h> 24 #include <drm/drm_vblank.h> 25 #include <drm/drm_writeback.h> 26 27 #include "vc4_drv.h" 28 #include "vc4_regs.h" 29 30 /* Base address of the output. Raster formats must be 4-byte aligned, 31 * T and LT must be 16-byte aligned or maybe utile-aligned (docs are 32 * inconsistent, but probably utile). 33 */ 34 #define TXP_DST_PTR 0x00 35 36 /* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's 37 * the width in tiles. 38 */ 39 #define TXP_DST_PITCH 0x04 40 /* For T-tiled imgaes, DST_PITCH should be the number of tiles wide, 41 * shifted up. 42 */ 43 # define TXP_T_TILE_WIDTH_SHIFT 7 44 /* For LT-tiled images, DST_PITCH should be the number of utiles wide, 45 * shifted up. 46 */ 47 # define TXP_LT_TILE_WIDTH_SHIFT 4 48 49 /* Pre-rotation width/height of the image. Must match HVS config. 50 * 51 * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit 52 * and width/height must be tile or utile-aligned as appropriate. If 53 * transposing (rotating), width is limited to 1920. 54 * 55 * Height is limited to various numbers between 4088 and 4095. I'd 56 * just use 4088 to be safe. 57 */ 58 #define TXP_DIM 0x08 59 # define TXP_HEIGHT_SHIFT 16 60 # define TXP_HEIGHT_MASK GENMASK(31, 16) 61 # define TXP_WIDTH_SHIFT 0 62 # define TXP_WIDTH_MASK GENMASK(15, 0) 63 64 #define TXP_DST_CTRL 0x0c 65 /* These bits are set to 0x54 */ 66 #define TXP_PILOT_SHIFT 24 67 #define TXP_PILOT_MASK GENMASK(31, 24) 68 /* Bits 22-23 are set to 0x01 */ 69 #define TXP_VERSION_SHIFT 22 70 #define TXP_VERSION_MASK GENMASK(23, 22) 71 72 /* Powers down the internal memory. */ 73 # define TXP_POWERDOWN BIT(21) 74 75 /* Enables storing the alpha component in 8888/4444, instead of 76 * filling with ~ALPHA_INVERT. 77 */ 78 # define TXP_ALPHA_ENABLE BIT(20) 79 80 /* 4 bits, each enables stores for a channel in each set of 4 bytes. 81 * Set to 0xf for normal operation. 82 */ 83 # define TXP_BYTE_ENABLE_SHIFT 16 84 # define TXP_BYTE_ENABLE_MASK GENMASK(19, 16) 85 86 /* Debug: Generate VSTART again at EOF. */ 87 # define TXP_VSTART_AT_EOF BIT(15) 88 89 /* Debug: Terminate the current frame immediately. Stops AXI 90 * writes. 91 */ 92 # define TXP_ABORT BIT(14) 93 94 # define TXP_DITHER BIT(13) 95 96 /* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for 97 * !TXP_ALPHA_ENABLE. 98 */ 99 # define TXP_ALPHA_INVERT BIT(12) 100 101 /* Note: I've listed the channels here in high bit (in byte 3/2/1) to 102 * low bit (in byte 0) order. 103 */ 104 # define TXP_FORMAT_SHIFT 8 105 # define TXP_FORMAT_MASK GENMASK(11, 8) 106 # define TXP_FORMAT_ABGR4444 0 107 # define TXP_FORMAT_ARGB4444 1 108 # define TXP_FORMAT_BGRA4444 2 109 # define TXP_FORMAT_RGBA4444 3 110 # define TXP_FORMAT_BGR565 6 111 # define TXP_FORMAT_RGB565 7 112 /* 888s are non-rotated, raster-only */ 113 # define TXP_FORMAT_BGR888 8 114 # define TXP_FORMAT_RGB888 9 115 # define TXP_FORMAT_ABGR8888 12 116 # define TXP_FORMAT_ARGB8888 13 117 # define TXP_FORMAT_BGRA8888 14 118 # define TXP_FORMAT_RGBA8888 15 119 120 /* If TFORMAT is set, generates LT instead of T format. */ 121 # define TXP_LINEAR_UTILE BIT(7) 122 123 /* Rotate output by 90 degrees. */ 124 # define TXP_TRANSPOSE BIT(6) 125 126 /* Generate a tiled format for V3D. */ 127 # define TXP_TFORMAT BIT(5) 128 129 /* Generates some undefined test mode output. */ 130 # define TXP_TEST_MODE BIT(4) 131 132 /* Request odd field from HVS. */ 133 # define TXP_FIELD BIT(3) 134 135 /* Raise interrupt when idle. */ 136 # define TXP_EI BIT(2) 137 138 /* Set when generating a frame, clears when idle. */ 139 # define TXP_BUSY BIT(1) 140 141 /* Starts a frame. Self-clearing. */ 142 # define TXP_GO BIT(0) 143 144 /* Number of lines received and committed to memory. */ 145 #define TXP_PROGRESS 0x10 146 147 #define TXP_READ(offset) readl(txp->regs + (offset)) 148 #define TXP_WRITE(offset, val) writel(val, txp->regs + (offset)) 149 150 struct vc4_txp { 151 struct vc4_crtc base; 152 153 struct platform_device *pdev; 154 155 struct drm_writeback_connector connector; 156 157 void __iomem *regs; 158 struct debugfs_regset32 regset; 159 }; 160 161 static inline struct vc4_txp *encoder_to_vc4_txp(struct drm_encoder *encoder) 162 { 163 return container_of(encoder, struct vc4_txp, connector.encoder); 164 } 165 166 static inline struct vc4_txp *connector_to_vc4_txp(struct drm_connector *conn) 167 { 168 return container_of(conn, struct vc4_txp, connector.base); 169 } 170 171 static const struct debugfs_reg32 txp_regs[] = { 172 VC4_REG32(TXP_DST_PTR), 173 VC4_REG32(TXP_DST_PITCH), 174 VC4_REG32(TXP_DIM), 175 VC4_REG32(TXP_DST_CTRL), 176 VC4_REG32(TXP_PROGRESS), 177 }; 178 179 static int vc4_txp_connector_get_modes(struct drm_connector *connector) 180 { 181 struct drm_device *dev = connector->dev; 182 183 return drm_add_modes_noedid(connector, dev->mode_config.max_width, 184 dev->mode_config.max_height); 185 } 186 187 static enum drm_mode_status 188 vc4_txp_connector_mode_valid(struct drm_connector *connector, 189 struct drm_display_mode *mode) 190 { 191 struct drm_device *dev = connector->dev; 192 struct drm_mode_config *mode_config = &dev->mode_config; 193 int w = mode->hdisplay, h = mode->vdisplay; 194 195 if (w < mode_config->min_width || w > mode_config->max_width) 196 return MODE_BAD_HVALUE; 197 198 if (h < mode_config->min_height || h > mode_config->max_height) 199 return MODE_BAD_VVALUE; 200 201 return MODE_OK; 202 } 203 204 static const u32 drm_fmts[] = { 205 DRM_FORMAT_RGB888, 206 DRM_FORMAT_BGR888, 207 DRM_FORMAT_XRGB8888, 208 DRM_FORMAT_XBGR8888, 209 DRM_FORMAT_ARGB8888, 210 DRM_FORMAT_ABGR8888, 211 DRM_FORMAT_RGBX8888, 212 DRM_FORMAT_BGRX8888, 213 DRM_FORMAT_RGBA8888, 214 DRM_FORMAT_BGRA8888, 215 }; 216 217 static const u32 txp_fmts[] = { 218 TXP_FORMAT_RGB888, 219 TXP_FORMAT_BGR888, 220 TXP_FORMAT_ARGB8888, 221 TXP_FORMAT_ABGR8888, 222 TXP_FORMAT_ARGB8888, 223 TXP_FORMAT_ABGR8888, 224 TXP_FORMAT_RGBA8888, 225 TXP_FORMAT_BGRA8888, 226 TXP_FORMAT_RGBA8888, 227 TXP_FORMAT_BGRA8888, 228 }; 229 230 static void vc4_txp_armed(struct drm_crtc_state *state) 231 { 232 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 233 234 vc4_state->txp_armed = true; 235 } 236 237 static int vc4_txp_connector_atomic_check(struct drm_connector *conn, 238 struct drm_atomic_state *state) 239 { 240 struct drm_connector_state *conn_state; 241 struct drm_crtc_state *crtc_state; 242 struct drm_framebuffer *fb; 243 int i; 244 245 conn_state = drm_atomic_get_new_connector_state(state, conn); 246 if (!conn_state->writeback_job) 247 return 0; 248 249 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 250 251 fb = conn_state->writeback_job->fb; 252 if (fb->width != crtc_state->mode.hdisplay || 253 fb->height != crtc_state->mode.vdisplay) { 254 DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n", 255 fb->width, fb->height); 256 return -EINVAL; 257 } 258 259 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { 260 if (fb->format->format == drm_fmts[i]) 261 break; 262 } 263 264 if (i == ARRAY_SIZE(drm_fmts)) 265 return -EINVAL; 266 267 /* Pitch must be aligned on 16 bytes. */ 268 if (fb->pitches[0] & GENMASK(3, 0)) 269 return -EINVAL; 270 271 vc4_txp_armed(crtc_state); 272 273 return 0; 274 } 275 276 static void vc4_txp_connector_atomic_commit(struct drm_connector *conn, 277 struct drm_atomic_state *state) 278 { 279 struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(state, 280 conn); 281 struct vc4_txp *txp = connector_to_vc4_txp(conn); 282 struct drm_gem_cma_object *gem; 283 struct drm_display_mode *mode; 284 struct drm_framebuffer *fb; 285 u32 ctrl; 286 int i; 287 288 if (WARN_ON(!conn_state->writeback_job)) 289 return; 290 291 mode = &conn_state->crtc->state->adjusted_mode; 292 fb = conn_state->writeback_job->fb; 293 294 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { 295 if (fb->format->format == drm_fmts[i]) 296 break; 297 } 298 299 if (WARN_ON(i == ARRAY_SIZE(drm_fmts))) 300 return; 301 302 ctrl = TXP_GO | TXP_EI | 303 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | 304 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); 305 306 if (fb->format->has_alpha) 307 ctrl |= TXP_ALPHA_ENABLE; 308 else 309 /* 310 * If TXP_ALPHA_ENABLE isn't set and TXP_ALPHA_INVERT is, the 311 * hardware will force the output padding to be 0xff. 312 */ 313 ctrl |= TXP_ALPHA_INVERT; 314 315 gem = drm_fb_cma_get_gem_obj(fb, 0); 316 TXP_WRITE(TXP_DST_PTR, gem->paddr + fb->offsets[0]); 317 TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]); 318 TXP_WRITE(TXP_DIM, 319 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | 320 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); 321 322 TXP_WRITE(TXP_DST_CTRL, ctrl); 323 324 drm_writeback_queue_job(&txp->connector, conn_state); 325 } 326 327 static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = { 328 .get_modes = vc4_txp_connector_get_modes, 329 .mode_valid = vc4_txp_connector_mode_valid, 330 .atomic_check = vc4_txp_connector_atomic_check, 331 .atomic_commit = vc4_txp_connector_atomic_commit, 332 }; 333 334 static enum drm_connector_status 335 vc4_txp_connector_detect(struct drm_connector *connector, bool force) 336 { 337 return connector_status_connected; 338 } 339 340 static void vc4_txp_connector_destroy(struct drm_connector *connector) 341 { 342 drm_connector_unregister(connector); 343 drm_connector_cleanup(connector); 344 } 345 346 static const struct drm_connector_funcs vc4_txp_connector_funcs = { 347 .detect = vc4_txp_connector_detect, 348 .fill_modes = drm_helper_probe_single_connector_modes, 349 .destroy = vc4_txp_connector_destroy, 350 .reset = drm_atomic_helper_connector_reset, 351 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 352 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 353 }; 354 355 static void vc4_txp_encoder_disable(struct drm_encoder *encoder) 356 { 357 struct vc4_txp *txp = encoder_to_vc4_txp(encoder); 358 359 if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) { 360 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 361 362 TXP_WRITE(TXP_DST_CTRL, TXP_ABORT); 363 364 while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY && 365 time_before(jiffies, timeout)) 366 ; 367 368 WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY); 369 } 370 371 TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN); 372 } 373 374 static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = { 375 .disable = vc4_txp_encoder_disable, 376 }; 377 378 static int vc4_txp_enable_vblank(struct drm_crtc *crtc) 379 { 380 return 0; 381 } 382 383 static void vc4_txp_disable_vblank(struct drm_crtc *crtc) {} 384 385 static const struct drm_crtc_funcs vc4_txp_crtc_funcs = { 386 .set_config = drm_atomic_helper_set_config, 387 .destroy = vc4_crtc_destroy, 388 .page_flip = vc4_page_flip, 389 .reset = vc4_crtc_reset, 390 .atomic_duplicate_state = vc4_crtc_duplicate_state, 391 .atomic_destroy_state = vc4_crtc_destroy_state, 392 .enable_vblank = vc4_txp_enable_vblank, 393 .disable_vblank = vc4_txp_disable_vblank, 394 }; 395 396 static int vc4_txp_atomic_check(struct drm_crtc *crtc, 397 struct drm_atomic_state *state) 398 { 399 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 400 crtc); 401 int ret; 402 403 ret = vc4_hvs_atomic_check(crtc, state); 404 if (ret) 405 return ret; 406 407 crtc_state->no_vblank = true; 408 409 return 0; 410 } 411 412 static void vc4_txp_atomic_enable(struct drm_crtc *crtc, 413 struct drm_atomic_state *state) 414 { 415 drm_crtc_vblank_on(crtc); 416 vc4_hvs_atomic_enable(crtc, state); 417 } 418 419 static void vc4_txp_atomic_disable(struct drm_crtc *crtc, 420 struct drm_atomic_state *state) 421 { 422 struct drm_device *dev = crtc->dev; 423 424 /* Disable vblank irq handling before crtc is disabled. */ 425 drm_crtc_vblank_off(crtc); 426 427 vc4_hvs_atomic_disable(crtc, state); 428 429 /* 430 * Make sure we issue a vblank event after disabling the CRTC if 431 * someone was waiting it. 432 */ 433 if (crtc->state->event) { 434 unsigned long flags; 435 436 spin_lock_irqsave(&dev->event_lock, flags); 437 drm_crtc_send_vblank_event(crtc, crtc->state->event); 438 crtc->state->event = NULL; 439 spin_unlock_irqrestore(&dev->event_lock, flags); 440 } 441 } 442 443 static const struct drm_crtc_helper_funcs vc4_txp_crtc_helper_funcs = { 444 .atomic_check = vc4_txp_atomic_check, 445 .atomic_begin = vc4_hvs_atomic_begin, 446 .atomic_flush = vc4_hvs_atomic_flush, 447 .atomic_enable = vc4_txp_atomic_enable, 448 .atomic_disable = vc4_txp_atomic_disable, 449 }; 450 451 static irqreturn_t vc4_txp_interrupt(int irq, void *data) 452 { 453 struct vc4_txp *txp = data; 454 struct vc4_crtc *vc4_crtc = &txp->base; 455 456 TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI); 457 vc4_crtc_handle_vblank(vc4_crtc); 458 drm_writeback_signal_completion(&txp->connector, 0); 459 460 return IRQ_HANDLED; 461 } 462 463 static const struct vc4_crtc_data vc4_txp_crtc_data = { 464 .hvs_available_channels = BIT(2), 465 .hvs_output = 2, 466 }; 467 468 static int vc4_txp_bind(struct device *dev, struct device *master, void *data) 469 { 470 struct platform_device *pdev = to_platform_device(dev); 471 struct drm_device *drm = dev_get_drvdata(master); 472 struct vc4_dev *vc4 = to_vc4_dev(drm); 473 struct vc4_crtc *vc4_crtc; 474 struct vc4_txp *txp; 475 struct drm_crtc *crtc; 476 struct drm_encoder *encoder; 477 int ret, irq; 478 479 irq = platform_get_irq(pdev, 0); 480 if (irq < 0) 481 return irq; 482 483 txp = devm_kzalloc(dev, sizeof(*txp), GFP_KERNEL); 484 if (!txp) 485 return -ENOMEM; 486 vc4_crtc = &txp->base; 487 crtc = &vc4_crtc->base; 488 489 vc4_crtc->pdev = pdev; 490 vc4_crtc->data = &vc4_txp_crtc_data; 491 vc4_crtc->feeds_txp = true; 492 493 txp->pdev = pdev; 494 495 txp->regs = vc4_ioremap_regs(pdev, 0); 496 if (IS_ERR(txp->regs)) 497 return PTR_ERR(txp->regs); 498 txp->regset.base = txp->regs; 499 txp->regset.regs = txp_regs; 500 txp->regset.nregs = ARRAY_SIZE(txp_regs); 501 502 drm_connector_helper_add(&txp->connector.base, 503 &vc4_txp_connector_helper_funcs); 504 ret = drm_writeback_connector_init(drm, &txp->connector, 505 &vc4_txp_connector_funcs, 506 &vc4_txp_encoder_helper_funcs, 507 drm_fmts, ARRAY_SIZE(drm_fmts), 508 0); 509 if (ret) 510 return ret; 511 512 ret = vc4_crtc_init(drm, vc4_crtc, 513 &vc4_txp_crtc_funcs, &vc4_txp_crtc_helper_funcs); 514 if (ret) 515 return ret; 516 517 encoder = &txp->connector.encoder; 518 encoder->possible_crtcs = drm_crtc_mask(crtc); 519 520 ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0, 521 dev_name(dev), txp); 522 if (ret) 523 return ret; 524 525 dev_set_drvdata(dev, txp); 526 vc4->txp = txp; 527 528 vc4_debugfs_add_regset32(drm, "txp_regs", &txp->regset); 529 530 return 0; 531 } 532 533 static void vc4_txp_unbind(struct device *dev, struct device *master, 534 void *data) 535 { 536 struct drm_device *drm = dev_get_drvdata(master); 537 struct vc4_dev *vc4 = to_vc4_dev(drm); 538 struct vc4_txp *txp = dev_get_drvdata(dev); 539 540 vc4_txp_connector_destroy(&txp->connector.base); 541 542 vc4->txp = NULL; 543 } 544 545 static const struct component_ops vc4_txp_ops = { 546 .bind = vc4_txp_bind, 547 .unbind = vc4_txp_unbind, 548 }; 549 550 static int vc4_txp_probe(struct platform_device *pdev) 551 { 552 return component_add(&pdev->dev, &vc4_txp_ops); 553 } 554 555 static int vc4_txp_remove(struct platform_device *pdev) 556 { 557 component_del(&pdev->dev, &vc4_txp_ops); 558 return 0; 559 } 560 561 static const struct of_device_id vc4_txp_dt_match[] = { 562 { .compatible = "brcm,bcm2835-txp" }, 563 { /* sentinel */ }, 564 }; 565 566 struct platform_driver vc4_txp_driver = { 567 .probe = vc4_txp_probe, 568 .remove = vc4_txp_remove, 569 .driver = { 570 .name = "vc4_txp", 571 .of_match_table = vc4_txp_dt_match, 572 }, 573 }; 574