1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright © 2018 Broadcom 4 * 5 * Authors: 6 * Eric Anholt <eric@anholt.net> 7 * Boris Brezillon <boris.brezillon@bootlin.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/component.h> 12 #include <linux/of_graph.h> 13 #include <linux/of_platform.h> 14 #include <linux/pm_runtime.h> 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_edid.h> 18 #include <drm/drm_fb_cma_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_panel.h> 21 #include <drm/drm_probe_helper.h> 22 #include <drm/drm_writeback.h> 23 24 #include "vc4_drv.h" 25 #include "vc4_regs.h" 26 27 /* Base address of the output. Raster formats must be 4-byte aligned, 28 * T and LT must be 16-byte aligned or maybe utile-aligned (docs are 29 * inconsistent, but probably utile). 30 */ 31 #define TXP_DST_PTR 0x00 32 33 /* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's 34 * the width in tiles. 35 */ 36 #define TXP_DST_PITCH 0x04 37 /* For T-tiled imgaes, DST_PITCH should be the number of tiles wide, 38 * shifted up. 39 */ 40 # define TXP_T_TILE_WIDTH_SHIFT 7 41 /* For LT-tiled images, DST_PITCH should be the number of utiles wide, 42 * shifted up. 43 */ 44 # define TXP_LT_TILE_WIDTH_SHIFT 4 45 46 /* Pre-rotation width/height of the image. Must match HVS config. 47 * 48 * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit 49 * and width/height must be tile or utile-aligned as appropriate. If 50 * transposing (rotating), width is limited to 1920. 51 * 52 * Height is limited to various numbers between 4088 and 4095. I'd 53 * just use 4088 to be safe. 54 */ 55 #define TXP_DIM 0x08 56 # define TXP_HEIGHT_SHIFT 16 57 # define TXP_HEIGHT_MASK GENMASK(31, 16) 58 # define TXP_WIDTH_SHIFT 0 59 # define TXP_WIDTH_MASK GENMASK(15, 0) 60 61 #define TXP_DST_CTRL 0x0c 62 /* These bits are set to 0x54 */ 63 #define TXP_PILOT_SHIFT 24 64 #define TXP_PILOT_MASK GENMASK(31, 24) 65 /* Bits 22-23 are set to 0x01 */ 66 #define TXP_VERSION_SHIFT 22 67 #define TXP_VERSION_MASK GENMASK(23, 22) 68 69 /* Powers down the internal memory. */ 70 # define TXP_POWERDOWN BIT(21) 71 72 /* Enables storing the alpha component in 8888/4444, instead of 73 * filling with ~ALPHA_INVERT. 74 */ 75 # define TXP_ALPHA_ENABLE BIT(20) 76 77 /* 4 bits, each enables stores for a channel in each set of 4 bytes. 78 * Set to 0xf for normal operation. 79 */ 80 # define TXP_BYTE_ENABLE_SHIFT 16 81 # define TXP_BYTE_ENABLE_MASK GENMASK(19, 16) 82 83 /* Debug: Generate VSTART again at EOF. */ 84 # define TXP_VSTART_AT_EOF BIT(15) 85 86 /* Debug: Terminate the current frame immediately. Stops AXI 87 * writes. 88 */ 89 # define TXP_ABORT BIT(14) 90 91 # define TXP_DITHER BIT(13) 92 93 /* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for 94 * !TXP_ALPHA_ENABLE. 95 */ 96 # define TXP_ALPHA_INVERT BIT(12) 97 98 /* Note: I've listed the channels here in high bit (in byte 3/2/1) to 99 * low bit (in byte 0) order. 100 */ 101 # define TXP_FORMAT_SHIFT 8 102 # define TXP_FORMAT_MASK GENMASK(11, 8) 103 # define TXP_FORMAT_ABGR4444 0 104 # define TXP_FORMAT_ARGB4444 1 105 # define TXP_FORMAT_BGRA4444 2 106 # define TXP_FORMAT_RGBA4444 3 107 # define TXP_FORMAT_BGR565 6 108 # define TXP_FORMAT_RGB565 7 109 /* 888s are non-rotated, raster-only */ 110 # define TXP_FORMAT_BGR888 8 111 # define TXP_FORMAT_RGB888 9 112 # define TXP_FORMAT_ABGR8888 12 113 # define TXP_FORMAT_ARGB8888 13 114 # define TXP_FORMAT_BGRA8888 14 115 # define TXP_FORMAT_RGBA8888 15 116 117 /* If TFORMAT is set, generates LT instead of T format. */ 118 # define TXP_LINEAR_UTILE BIT(7) 119 120 /* Rotate output by 90 degrees. */ 121 # define TXP_TRANSPOSE BIT(6) 122 123 /* Generate a tiled format for V3D. */ 124 # define TXP_TFORMAT BIT(5) 125 126 /* Generates some undefined test mode output. */ 127 # define TXP_TEST_MODE BIT(4) 128 129 /* Request odd field from HVS. */ 130 # define TXP_FIELD BIT(3) 131 132 /* Raise interrupt when idle. */ 133 # define TXP_EI BIT(2) 134 135 /* Set when generating a frame, clears when idle. */ 136 # define TXP_BUSY BIT(1) 137 138 /* Starts a frame. Self-clearing. */ 139 # define TXP_GO BIT(0) 140 141 /* Number of lines received and committed to memory. */ 142 #define TXP_PROGRESS 0x10 143 144 #define TXP_READ(offset) readl(txp->regs + (offset)) 145 #define TXP_WRITE(offset, val) writel(val, txp->regs + (offset)) 146 147 struct vc4_txp { 148 struct platform_device *pdev; 149 150 struct drm_writeback_connector connector; 151 152 void __iomem *regs; 153 struct debugfs_regset32 regset; 154 }; 155 156 static inline struct vc4_txp *encoder_to_vc4_txp(struct drm_encoder *encoder) 157 { 158 return container_of(encoder, struct vc4_txp, connector.encoder); 159 } 160 161 static inline struct vc4_txp *connector_to_vc4_txp(struct drm_connector *conn) 162 { 163 return container_of(conn, struct vc4_txp, connector.base); 164 } 165 166 static const struct debugfs_reg32 txp_regs[] = { 167 VC4_REG32(TXP_DST_PTR), 168 VC4_REG32(TXP_DST_PITCH), 169 VC4_REG32(TXP_DIM), 170 VC4_REG32(TXP_DST_CTRL), 171 VC4_REG32(TXP_PROGRESS), 172 }; 173 174 static int vc4_txp_connector_get_modes(struct drm_connector *connector) 175 { 176 struct drm_device *dev = connector->dev; 177 178 return drm_add_modes_noedid(connector, dev->mode_config.max_width, 179 dev->mode_config.max_height); 180 } 181 182 static enum drm_mode_status 183 vc4_txp_connector_mode_valid(struct drm_connector *connector, 184 struct drm_display_mode *mode) 185 { 186 struct drm_device *dev = connector->dev; 187 struct drm_mode_config *mode_config = &dev->mode_config; 188 int w = mode->hdisplay, h = mode->vdisplay; 189 190 if (w < mode_config->min_width || w > mode_config->max_width) 191 return MODE_BAD_HVALUE; 192 193 if (h < mode_config->min_height || h > mode_config->max_height) 194 return MODE_BAD_VVALUE; 195 196 return MODE_OK; 197 } 198 199 static const u32 drm_fmts[] = { 200 DRM_FORMAT_RGB888, 201 DRM_FORMAT_BGR888, 202 DRM_FORMAT_XRGB8888, 203 DRM_FORMAT_XBGR8888, 204 DRM_FORMAT_ARGB8888, 205 DRM_FORMAT_ABGR8888, 206 DRM_FORMAT_RGBX8888, 207 DRM_FORMAT_BGRX8888, 208 DRM_FORMAT_RGBA8888, 209 DRM_FORMAT_BGRA8888, 210 }; 211 212 static const u32 txp_fmts[] = { 213 TXP_FORMAT_RGB888, 214 TXP_FORMAT_BGR888, 215 TXP_FORMAT_ARGB8888, 216 TXP_FORMAT_ABGR8888, 217 TXP_FORMAT_ARGB8888, 218 TXP_FORMAT_ABGR8888, 219 TXP_FORMAT_RGBA8888, 220 TXP_FORMAT_BGRA8888, 221 TXP_FORMAT_RGBA8888, 222 TXP_FORMAT_BGRA8888, 223 }; 224 225 static int vc4_txp_connector_atomic_check(struct drm_connector *conn, 226 struct drm_atomic_state *state) 227 { 228 struct drm_connector_state *conn_state; 229 struct drm_crtc_state *crtc_state; 230 struct drm_framebuffer *fb; 231 int i; 232 233 conn_state = drm_atomic_get_new_connector_state(state, conn); 234 if (!conn_state->writeback_job) 235 return 0; 236 237 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 238 239 fb = conn_state->writeback_job->fb; 240 if (fb->width != crtc_state->mode.hdisplay || 241 fb->height != crtc_state->mode.vdisplay) { 242 DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n", 243 fb->width, fb->height); 244 return -EINVAL; 245 } 246 247 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { 248 if (fb->format->format == drm_fmts[i]) 249 break; 250 } 251 252 if (i == ARRAY_SIZE(drm_fmts)) 253 return -EINVAL; 254 255 /* Pitch must be aligned on 16 bytes. */ 256 if (fb->pitches[0] & GENMASK(3, 0)) 257 return -EINVAL; 258 259 vc4_crtc_txp_armed(crtc_state); 260 261 return 0; 262 } 263 264 static void vc4_txp_connector_atomic_commit(struct drm_connector *conn, 265 struct drm_connector_state *conn_state) 266 { 267 struct vc4_txp *txp = connector_to_vc4_txp(conn); 268 struct drm_gem_cma_object *gem; 269 struct drm_display_mode *mode; 270 struct drm_framebuffer *fb; 271 u32 ctrl; 272 int i; 273 274 if (WARN_ON(!conn_state->writeback_job)) 275 return; 276 277 mode = &conn_state->crtc->state->adjusted_mode; 278 fb = conn_state->writeback_job->fb; 279 280 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { 281 if (fb->format->format == drm_fmts[i]) 282 break; 283 } 284 285 if (WARN_ON(i == ARRAY_SIZE(drm_fmts))) 286 return; 287 288 ctrl = TXP_GO | TXP_VSTART_AT_EOF | TXP_EI | 289 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | 290 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); 291 292 if (fb->format->has_alpha) 293 ctrl |= TXP_ALPHA_ENABLE; 294 295 gem = drm_fb_cma_get_gem_obj(fb, 0); 296 TXP_WRITE(TXP_DST_PTR, gem->paddr + fb->offsets[0]); 297 TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]); 298 TXP_WRITE(TXP_DIM, 299 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | 300 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); 301 302 TXP_WRITE(TXP_DST_CTRL, ctrl); 303 304 drm_writeback_queue_job(&txp->connector, conn_state); 305 } 306 307 static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = { 308 .get_modes = vc4_txp_connector_get_modes, 309 .mode_valid = vc4_txp_connector_mode_valid, 310 .atomic_check = vc4_txp_connector_atomic_check, 311 .atomic_commit = vc4_txp_connector_atomic_commit, 312 }; 313 314 static enum drm_connector_status 315 vc4_txp_connector_detect(struct drm_connector *connector, bool force) 316 { 317 return connector_status_connected; 318 } 319 320 static void vc4_txp_connector_destroy(struct drm_connector *connector) 321 { 322 drm_connector_unregister(connector); 323 drm_connector_cleanup(connector); 324 } 325 326 static const struct drm_connector_funcs vc4_txp_connector_funcs = { 327 .detect = vc4_txp_connector_detect, 328 .fill_modes = drm_helper_probe_single_connector_modes, 329 .destroy = vc4_txp_connector_destroy, 330 .reset = drm_atomic_helper_connector_reset, 331 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 332 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 333 }; 334 335 static void vc4_txp_encoder_disable(struct drm_encoder *encoder) 336 { 337 struct vc4_txp *txp = encoder_to_vc4_txp(encoder); 338 339 if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) { 340 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 341 342 TXP_WRITE(TXP_DST_CTRL, TXP_ABORT); 343 344 while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY && 345 time_before(jiffies, timeout)) 346 ; 347 348 WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY); 349 } 350 351 TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN); 352 } 353 354 static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = { 355 .disable = vc4_txp_encoder_disable, 356 }; 357 358 static irqreturn_t vc4_txp_interrupt(int irq, void *data) 359 { 360 struct vc4_txp *txp = data; 361 362 TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI); 363 vc4_crtc_handle_vblank(to_vc4_crtc(txp->connector.base.state->crtc)); 364 drm_writeback_signal_completion(&txp->connector, 0); 365 366 return IRQ_HANDLED; 367 } 368 369 static int vc4_txp_bind(struct device *dev, struct device *master, void *data) 370 { 371 struct platform_device *pdev = to_platform_device(dev); 372 struct drm_device *drm = dev_get_drvdata(master); 373 struct vc4_dev *vc4 = to_vc4_dev(drm); 374 struct vc4_txp *txp; 375 int ret, irq; 376 377 irq = platform_get_irq(pdev, 0); 378 if (irq < 0) 379 return irq; 380 381 txp = devm_kzalloc(dev, sizeof(*txp), GFP_KERNEL); 382 if (!txp) 383 return -ENOMEM; 384 385 txp->pdev = pdev; 386 387 txp->regs = vc4_ioremap_regs(pdev, 0); 388 if (IS_ERR(txp->regs)) 389 return PTR_ERR(txp->regs); 390 txp->regset.base = txp->regs; 391 txp->regset.regs = txp_regs; 392 txp->regset.nregs = ARRAY_SIZE(txp_regs); 393 394 drm_connector_helper_add(&txp->connector.base, 395 &vc4_txp_connector_helper_funcs); 396 ret = drm_writeback_connector_init(drm, &txp->connector, 397 &vc4_txp_connector_funcs, 398 &vc4_txp_encoder_helper_funcs, 399 drm_fmts, ARRAY_SIZE(drm_fmts)); 400 if (ret) 401 return ret; 402 403 ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0, 404 dev_name(dev), txp); 405 if (ret) 406 return ret; 407 408 dev_set_drvdata(dev, txp); 409 vc4->txp = txp; 410 411 vc4_debugfs_add_regset32(drm, "txp_regs", &txp->regset); 412 413 return 0; 414 } 415 416 static void vc4_txp_unbind(struct device *dev, struct device *master, 417 void *data) 418 { 419 struct drm_device *drm = dev_get_drvdata(master); 420 struct vc4_dev *vc4 = to_vc4_dev(drm); 421 struct vc4_txp *txp = dev_get_drvdata(dev); 422 423 vc4_txp_connector_destroy(&txp->connector.base); 424 425 vc4->txp = NULL; 426 } 427 428 static const struct component_ops vc4_txp_ops = { 429 .bind = vc4_txp_bind, 430 .unbind = vc4_txp_unbind, 431 }; 432 433 static int vc4_txp_probe(struct platform_device *pdev) 434 { 435 return component_add(&pdev->dev, &vc4_txp_ops); 436 } 437 438 static int vc4_txp_remove(struct platform_device *pdev) 439 { 440 component_del(&pdev->dev, &vc4_txp_ops); 441 return 0; 442 } 443 444 static const struct of_device_id vc4_txp_dt_match[] = { 445 { .compatible = "brcm,bcm2835-txp" }, 446 { /* sentinel */ }, 447 }; 448 449 struct platform_driver vc4_txp_driver = { 450 .probe = vc4_txp_probe, 451 .remove = vc4_txp_remove, 452 .driver = { 453 .name = "vc4_txp", 454 .of_match_table = vc4_txp_dt_match, 455 }, 456 }; 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