1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright © 2018 Broadcom 4 * 5 * Authors: 6 * Eric Anholt <eric@anholt.net> 7 * Boris Brezillon <boris.brezillon@bootlin.com> 8 */ 9 10 #include <drm/drm_atomic_helper.h> 11 #include <drm/drm_fb_cma_helper.h> 12 #include <drm/drm_crtc_helper.h> 13 #include <drm/drm_edid.h> 14 #include <drm/drm_panel.h> 15 #include <drm/drm_writeback.h> 16 #include <linux/clk.h> 17 #include <linux/component.h> 18 #include <linux/of_graph.h> 19 #include <linux/of_platform.h> 20 #include <linux/pm_runtime.h> 21 22 #include "vc4_drv.h" 23 #include "vc4_regs.h" 24 25 /* Base address of the output. Raster formats must be 4-byte aligned, 26 * T and LT must be 16-byte aligned or maybe utile-aligned (docs are 27 * inconsistent, but probably utile). 28 */ 29 #define TXP_DST_PTR 0x00 30 31 /* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's 32 * the width in tiles. 33 */ 34 #define TXP_DST_PITCH 0x04 35 /* For T-tiled imgaes, DST_PITCH should be the number of tiles wide, 36 * shifted up. 37 */ 38 # define TXP_T_TILE_WIDTH_SHIFT 7 39 /* For LT-tiled images, DST_PITCH should be the number of utiles wide, 40 * shifted up. 41 */ 42 # define TXP_LT_TILE_WIDTH_SHIFT 4 43 44 /* Pre-rotation width/height of the image. Must match HVS config. 45 * 46 * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit 47 * and width/height must be tile or utile-aligned as appropriate. If 48 * transposing (rotating), width is limited to 1920. 49 * 50 * Height is limited to various numbers between 4088 and 4095. I'd 51 * just use 4088 to be safe. 52 */ 53 #define TXP_DIM 0x08 54 # define TXP_HEIGHT_SHIFT 16 55 # define TXP_HEIGHT_MASK GENMASK(31, 16) 56 # define TXP_WIDTH_SHIFT 0 57 # define TXP_WIDTH_MASK GENMASK(15, 0) 58 59 #define TXP_DST_CTRL 0x0c 60 /* These bits are set to 0x54 */ 61 #define TXP_PILOT_SHIFT 24 62 #define TXP_PILOT_MASK GENMASK(31, 24) 63 /* Bits 22-23 are set to 0x01 */ 64 #define TXP_VERSION_SHIFT 22 65 #define TXP_VERSION_MASK GENMASK(23, 22) 66 67 /* Powers down the internal memory. */ 68 # define TXP_POWERDOWN BIT(21) 69 70 /* Enables storing the alpha component in 8888/4444, instead of 71 * filling with ~ALPHA_INVERT. 72 */ 73 # define TXP_ALPHA_ENABLE BIT(20) 74 75 /* 4 bits, each enables stores for a channel in each set of 4 bytes. 76 * Set to 0xf for normal operation. 77 */ 78 # define TXP_BYTE_ENABLE_SHIFT 16 79 # define TXP_BYTE_ENABLE_MASK GENMASK(19, 16) 80 81 /* Debug: Generate VSTART again at EOF. */ 82 # define TXP_VSTART_AT_EOF BIT(15) 83 84 /* Debug: Terminate the current frame immediately. Stops AXI 85 * writes. 86 */ 87 # define TXP_ABORT BIT(14) 88 89 # define TXP_DITHER BIT(13) 90 91 /* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for 92 * !TXP_ALPHA_ENABLE. 93 */ 94 # define TXP_ALPHA_INVERT BIT(12) 95 96 /* Note: I've listed the channels here in high bit (in byte 3/2/1) to 97 * low bit (in byte 0) order. 98 */ 99 # define TXP_FORMAT_SHIFT 8 100 # define TXP_FORMAT_MASK GENMASK(11, 8) 101 # define TXP_FORMAT_ABGR4444 0 102 # define TXP_FORMAT_ARGB4444 1 103 # define TXP_FORMAT_BGRA4444 2 104 # define TXP_FORMAT_RGBA4444 3 105 # define TXP_FORMAT_BGR565 6 106 # define TXP_FORMAT_RGB565 7 107 /* 888s are non-rotated, raster-only */ 108 # define TXP_FORMAT_BGR888 8 109 # define TXP_FORMAT_RGB888 9 110 # define TXP_FORMAT_ABGR8888 12 111 # define TXP_FORMAT_ARGB8888 13 112 # define TXP_FORMAT_BGRA8888 14 113 # define TXP_FORMAT_RGBA8888 15 114 115 /* If TFORMAT is set, generates LT instead of T format. */ 116 # define TXP_LINEAR_UTILE BIT(7) 117 118 /* Rotate output by 90 degrees. */ 119 # define TXP_TRANSPOSE BIT(6) 120 121 /* Generate a tiled format for V3D. */ 122 # define TXP_TFORMAT BIT(5) 123 124 /* Generates some undefined test mode output. */ 125 # define TXP_TEST_MODE BIT(4) 126 127 /* Request odd field from HVS. */ 128 # define TXP_FIELD BIT(3) 129 130 /* Raise interrupt when idle. */ 131 # define TXP_EI BIT(2) 132 133 /* Set when generating a frame, clears when idle. */ 134 # define TXP_BUSY BIT(1) 135 136 /* Starts a frame. Self-clearing. */ 137 # define TXP_GO BIT(0) 138 139 /* Number of lines received and committed to memory. */ 140 #define TXP_PROGRESS 0x10 141 142 #define TXP_READ(offset) readl(txp->regs + (offset)) 143 #define TXP_WRITE(offset, val) writel(val, txp->regs + (offset)) 144 145 struct vc4_txp { 146 struct platform_device *pdev; 147 148 struct drm_writeback_connector connector; 149 150 void __iomem *regs; 151 }; 152 153 static inline struct vc4_txp *encoder_to_vc4_txp(struct drm_encoder *encoder) 154 { 155 return container_of(encoder, struct vc4_txp, connector.encoder); 156 } 157 158 static inline struct vc4_txp *connector_to_vc4_txp(struct drm_connector *conn) 159 { 160 return container_of(conn, struct vc4_txp, connector.base); 161 } 162 163 #define TXP_REG(reg) { reg, #reg } 164 static const struct { 165 u32 reg; 166 const char *name; 167 } txp_regs[] = { 168 TXP_REG(TXP_DST_PTR), 169 TXP_REG(TXP_DST_PITCH), 170 TXP_REG(TXP_DIM), 171 TXP_REG(TXP_DST_CTRL), 172 TXP_REG(TXP_PROGRESS), 173 }; 174 175 #ifdef CONFIG_DEBUG_FS 176 int vc4_txp_debugfs_regs(struct seq_file *m, void *unused) 177 { 178 struct drm_info_node *node = (struct drm_info_node *)m->private; 179 struct drm_device *dev = node->minor->dev; 180 struct vc4_dev *vc4 = to_vc4_dev(dev); 181 struct vc4_txp *txp = vc4->txp; 182 int i; 183 184 if (!txp) 185 return 0; 186 187 for (i = 0; i < ARRAY_SIZE(txp_regs); i++) { 188 seq_printf(m, "%s (0x%04x): 0x%08x\n", 189 txp_regs[i].name, txp_regs[i].reg, 190 TXP_READ(txp_regs[i].reg)); 191 } 192 193 return 0; 194 } 195 #endif 196 197 static int vc4_txp_connector_get_modes(struct drm_connector *connector) 198 { 199 struct drm_device *dev = connector->dev; 200 201 return drm_add_modes_noedid(connector, dev->mode_config.max_width, 202 dev->mode_config.max_height); 203 } 204 205 static enum drm_mode_status 206 vc4_txp_connector_mode_valid(struct drm_connector *connector, 207 struct drm_display_mode *mode) 208 { 209 struct drm_device *dev = connector->dev; 210 struct drm_mode_config *mode_config = &dev->mode_config; 211 int w = mode->hdisplay, h = mode->vdisplay; 212 213 if (w < mode_config->min_width || w > mode_config->max_width) 214 return MODE_BAD_HVALUE; 215 216 if (h < mode_config->min_height || h > mode_config->max_height) 217 return MODE_BAD_VVALUE; 218 219 return MODE_OK; 220 } 221 222 static const u32 drm_fmts[] = { 223 DRM_FORMAT_RGB888, 224 DRM_FORMAT_BGR888, 225 DRM_FORMAT_XRGB8888, 226 DRM_FORMAT_XBGR8888, 227 DRM_FORMAT_ARGB8888, 228 DRM_FORMAT_ABGR8888, 229 DRM_FORMAT_RGBX8888, 230 DRM_FORMAT_BGRX8888, 231 DRM_FORMAT_RGBA8888, 232 DRM_FORMAT_BGRA8888, 233 }; 234 235 static const u32 txp_fmts[] = { 236 TXP_FORMAT_RGB888, 237 TXP_FORMAT_BGR888, 238 TXP_FORMAT_ARGB8888, 239 TXP_FORMAT_ABGR8888, 240 TXP_FORMAT_ARGB8888, 241 TXP_FORMAT_ABGR8888, 242 TXP_FORMAT_RGBA8888, 243 TXP_FORMAT_BGRA8888, 244 TXP_FORMAT_RGBA8888, 245 TXP_FORMAT_BGRA8888, 246 }; 247 248 static int vc4_txp_connector_atomic_check(struct drm_connector *conn, 249 struct drm_connector_state *conn_state) 250 { 251 struct drm_crtc_state *crtc_state; 252 struct drm_gem_cma_object *gem; 253 struct drm_framebuffer *fb; 254 int i; 255 256 if (!conn_state->writeback_job || !conn_state->writeback_job->fb) 257 return 0; 258 259 crtc_state = drm_atomic_get_new_crtc_state(conn_state->state, 260 conn_state->crtc); 261 262 fb = conn_state->writeback_job->fb; 263 if (fb->width != crtc_state->mode.hdisplay || 264 fb->height != crtc_state->mode.vdisplay) { 265 DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n", 266 fb->width, fb->height); 267 return -EINVAL; 268 } 269 270 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { 271 if (fb->format->format == drm_fmts[i]) 272 break; 273 } 274 275 if (i == ARRAY_SIZE(drm_fmts)) 276 return -EINVAL; 277 278 gem = drm_fb_cma_get_gem_obj(fb, 0); 279 280 /* Pitch must be aligned on 16 bytes. */ 281 if (fb->pitches[0] & GENMASK(3, 0)) 282 return -EINVAL; 283 284 vc4_crtc_txp_armed(crtc_state); 285 286 return 0; 287 } 288 289 static void vc4_txp_connector_atomic_commit(struct drm_connector *conn, 290 struct drm_connector_state *conn_state) 291 { 292 struct vc4_txp *txp = connector_to_vc4_txp(conn); 293 struct drm_gem_cma_object *gem; 294 struct drm_display_mode *mode; 295 struct drm_framebuffer *fb; 296 u32 ctrl; 297 int i; 298 299 if (WARN_ON(!conn_state->writeback_job || 300 !conn_state->writeback_job->fb)) 301 return; 302 303 mode = &conn_state->crtc->state->adjusted_mode; 304 fb = conn_state->writeback_job->fb; 305 306 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { 307 if (fb->format->format == drm_fmts[i]) 308 break; 309 } 310 311 if (WARN_ON(i == ARRAY_SIZE(drm_fmts))) 312 return; 313 314 ctrl = TXP_GO | TXP_VSTART_AT_EOF | TXP_EI | 315 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | 316 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); 317 318 if (fb->format->has_alpha) 319 ctrl |= TXP_ALPHA_ENABLE; 320 321 gem = drm_fb_cma_get_gem_obj(fb, 0); 322 TXP_WRITE(TXP_DST_PTR, gem->paddr + fb->offsets[0]); 323 TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]); 324 TXP_WRITE(TXP_DIM, 325 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | 326 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); 327 328 TXP_WRITE(TXP_DST_CTRL, ctrl); 329 330 drm_writeback_queue_job(&txp->connector, conn_state->writeback_job); 331 } 332 333 static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = { 334 .get_modes = vc4_txp_connector_get_modes, 335 .mode_valid = vc4_txp_connector_mode_valid, 336 .atomic_check = vc4_txp_connector_atomic_check, 337 .atomic_commit = vc4_txp_connector_atomic_commit, 338 }; 339 340 static enum drm_connector_status 341 vc4_txp_connector_detect(struct drm_connector *connector, bool force) 342 { 343 return connector_status_connected; 344 } 345 346 static void vc4_txp_connector_destroy(struct drm_connector *connector) 347 { 348 drm_connector_unregister(connector); 349 drm_connector_cleanup(connector); 350 } 351 352 static const struct drm_connector_funcs vc4_txp_connector_funcs = { 353 .detect = vc4_txp_connector_detect, 354 .fill_modes = drm_helper_probe_single_connector_modes, 355 .destroy = vc4_txp_connector_destroy, 356 .reset = drm_atomic_helper_connector_reset, 357 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 358 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 359 }; 360 361 static void vc4_txp_encoder_disable(struct drm_encoder *encoder) 362 { 363 struct vc4_txp *txp = encoder_to_vc4_txp(encoder); 364 365 if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) { 366 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 367 368 TXP_WRITE(TXP_DST_CTRL, TXP_ABORT); 369 370 while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY && 371 time_before(jiffies, timeout)) 372 ; 373 374 WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY); 375 } 376 377 TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN); 378 } 379 380 static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = { 381 .disable = vc4_txp_encoder_disable, 382 }; 383 384 static irqreturn_t vc4_txp_interrupt(int irq, void *data) 385 { 386 struct vc4_txp *txp = data; 387 388 TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI); 389 vc4_crtc_handle_vblank(to_vc4_crtc(txp->connector.base.state->crtc)); 390 drm_writeback_signal_completion(&txp->connector, 0); 391 392 return IRQ_HANDLED; 393 } 394 395 static int vc4_txp_bind(struct device *dev, struct device *master, void *data) 396 { 397 struct platform_device *pdev = to_platform_device(dev); 398 struct drm_device *drm = dev_get_drvdata(master); 399 struct vc4_dev *vc4 = to_vc4_dev(drm); 400 struct vc4_txp *txp; 401 int ret, irq; 402 403 irq = platform_get_irq(pdev, 0); 404 if (irq < 0) 405 return irq; 406 407 txp = devm_kzalloc(dev, sizeof(*txp), GFP_KERNEL); 408 if (!txp) 409 return -ENOMEM; 410 411 txp->pdev = pdev; 412 413 txp->regs = vc4_ioremap_regs(pdev, 0); 414 if (IS_ERR(txp->regs)) 415 return PTR_ERR(txp->regs); 416 417 drm_connector_helper_add(&txp->connector.base, 418 &vc4_txp_connector_helper_funcs); 419 ret = drm_writeback_connector_init(drm, &txp->connector, 420 &vc4_txp_connector_funcs, 421 &vc4_txp_encoder_helper_funcs, 422 drm_fmts, ARRAY_SIZE(drm_fmts)); 423 if (ret) 424 return ret; 425 426 ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0, 427 dev_name(dev), txp); 428 if (ret) 429 return ret; 430 431 dev_set_drvdata(dev, txp); 432 vc4->txp = txp; 433 434 return 0; 435 } 436 437 static void vc4_txp_unbind(struct device *dev, struct device *master, 438 void *data) 439 { 440 struct drm_device *drm = dev_get_drvdata(master); 441 struct vc4_dev *vc4 = to_vc4_dev(drm); 442 struct vc4_txp *txp = dev_get_drvdata(dev); 443 444 vc4_txp_connector_destroy(&txp->connector.base); 445 446 vc4->txp = NULL; 447 } 448 449 static const struct component_ops vc4_txp_ops = { 450 .bind = vc4_txp_bind, 451 .unbind = vc4_txp_unbind, 452 }; 453 454 static int vc4_txp_probe(struct platform_device *pdev) 455 { 456 return component_add(&pdev->dev, &vc4_txp_ops); 457 } 458 459 static int vc4_txp_remove(struct platform_device *pdev) 460 { 461 component_del(&pdev->dev, &vc4_txp_ops); 462 return 0; 463 } 464 465 static const struct of_device_id vc4_txp_dt_match[] = { 466 { .compatible = "brcm,bcm2835-txp" }, 467 { /* sentinel */ }, 468 }; 469 470 struct platform_driver vc4_txp_driver = { 471 .probe = vc4_txp_probe, 472 .remove = vc4_txp_remove, 473 .driver = { 474 .name = "vc4_txp", 475 .of_match_table = vc4_txp_dt_match, 476 }, 477 }; 478