1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright © 2018 Broadcom 4 * 5 * Authors: 6 * Eric Anholt <eric@anholt.net> 7 * Boris Brezillon <boris.brezillon@bootlin.com> 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/component.h> 12 #include <linux/of_graph.h> 13 #include <linux/of_platform.h> 14 #include <linux/pm_runtime.h> 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_edid.h> 18 #include <drm/drm_fb_cma_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_panel.h> 21 #include <drm/drm_probe_helper.h> 22 #include <drm/drm_vblank.h> 23 #include <drm/drm_writeback.h> 24 25 #include "vc4_drv.h" 26 #include "vc4_regs.h" 27 28 /* Base address of the output. Raster formats must be 4-byte aligned, 29 * T and LT must be 16-byte aligned or maybe utile-aligned (docs are 30 * inconsistent, but probably utile). 31 */ 32 #define TXP_DST_PTR 0x00 33 34 /* Pitch in bytes for raster images, 16-byte aligned. For tiled, it's 35 * the width in tiles. 36 */ 37 #define TXP_DST_PITCH 0x04 38 /* For T-tiled imgaes, DST_PITCH should be the number of tiles wide, 39 * shifted up. 40 */ 41 # define TXP_T_TILE_WIDTH_SHIFT 7 42 /* For LT-tiled images, DST_PITCH should be the number of utiles wide, 43 * shifted up. 44 */ 45 # define TXP_LT_TILE_WIDTH_SHIFT 4 46 47 /* Pre-rotation width/height of the image. Must match HVS config. 48 * 49 * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit 50 * and width/height must be tile or utile-aligned as appropriate. If 51 * transposing (rotating), width is limited to 1920. 52 * 53 * Height is limited to various numbers between 4088 and 4095. I'd 54 * just use 4088 to be safe. 55 */ 56 #define TXP_DIM 0x08 57 # define TXP_HEIGHT_SHIFT 16 58 # define TXP_HEIGHT_MASK GENMASK(31, 16) 59 # define TXP_WIDTH_SHIFT 0 60 # define TXP_WIDTH_MASK GENMASK(15, 0) 61 62 #define TXP_DST_CTRL 0x0c 63 /* These bits are set to 0x54 */ 64 #define TXP_PILOT_SHIFT 24 65 #define TXP_PILOT_MASK GENMASK(31, 24) 66 /* Bits 22-23 are set to 0x01 */ 67 #define TXP_VERSION_SHIFT 22 68 #define TXP_VERSION_MASK GENMASK(23, 22) 69 70 /* Powers down the internal memory. */ 71 # define TXP_POWERDOWN BIT(21) 72 73 /* Enables storing the alpha component in 8888/4444, instead of 74 * filling with ~ALPHA_INVERT. 75 */ 76 # define TXP_ALPHA_ENABLE BIT(20) 77 78 /* 4 bits, each enables stores for a channel in each set of 4 bytes. 79 * Set to 0xf for normal operation. 80 */ 81 # define TXP_BYTE_ENABLE_SHIFT 16 82 # define TXP_BYTE_ENABLE_MASK GENMASK(19, 16) 83 84 /* Debug: Generate VSTART again at EOF. */ 85 # define TXP_VSTART_AT_EOF BIT(15) 86 87 /* Debug: Terminate the current frame immediately. Stops AXI 88 * writes. 89 */ 90 # define TXP_ABORT BIT(14) 91 92 # define TXP_DITHER BIT(13) 93 94 /* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for 95 * !TXP_ALPHA_ENABLE. 96 */ 97 # define TXP_ALPHA_INVERT BIT(12) 98 99 /* Note: I've listed the channels here in high bit (in byte 3/2/1) to 100 * low bit (in byte 0) order. 101 */ 102 # define TXP_FORMAT_SHIFT 8 103 # define TXP_FORMAT_MASK GENMASK(11, 8) 104 # define TXP_FORMAT_ABGR4444 0 105 # define TXP_FORMAT_ARGB4444 1 106 # define TXP_FORMAT_BGRA4444 2 107 # define TXP_FORMAT_RGBA4444 3 108 # define TXP_FORMAT_BGR565 6 109 # define TXP_FORMAT_RGB565 7 110 /* 888s are non-rotated, raster-only */ 111 # define TXP_FORMAT_BGR888 8 112 # define TXP_FORMAT_RGB888 9 113 # define TXP_FORMAT_ABGR8888 12 114 # define TXP_FORMAT_ARGB8888 13 115 # define TXP_FORMAT_BGRA8888 14 116 # define TXP_FORMAT_RGBA8888 15 117 118 /* If TFORMAT is set, generates LT instead of T format. */ 119 # define TXP_LINEAR_UTILE BIT(7) 120 121 /* Rotate output by 90 degrees. */ 122 # define TXP_TRANSPOSE BIT(6) 123 124 /* Generate a tiled format for V3D. */ 125 # define TXP_TFORMAT BIT(5) 126 127 /* Generates some undefined test mode output. */ 128 # define TXP_TEST_MODE BIT(4) 129 130 /* Request odd field from HVS. */ 131 # define TXP_FIELD BIT(3) 132 133 /* Raise interrupt when idle. */ 134 # define TXP_EI BIT(2) 135 136 /* Set when generating a frame, clears when idle. */ 137 # define TXP_BUSY BIT(1) 138 139 /* Starts a frame. Self-clearing. */ 140 # define TXP_GO BIT(0) 141 142 /* Number of lines received and committed to memory. */ 143 #define TXP_PROGRESS 0x10 144 145 #define TXP_READ(offset) readl(txp->regs + (offset)) 146 #define TXP_WRITE(offset, val) writel(val, txp->regs + (offset)) 147 148 struct vc4_txp { 149 struct vc4_crtc base; 150 151 struct platform_device *pdev; 152 153 struct drm_writeback_connector connector; 154 155 void __iomem *regs; 156 struct debugfs_regset32 regset; 157 }; 158 159 static inline struct vc4_txp *encoder_to_vc4_txp(struct drm_encoder *encoder) 160 { 161 return container_of(encoder, struct vc4_txp, connector.encoder); 162 } 163 164 static inline struct vc4_txp *connector_to_vc4_txp(struct drm_connector *conn) 165 { 166 return container_of(conn, struct vc4_txp, connector.base); 167 } 168 169 static const struct debugfs_reg32 txp_regs[] = { 170 VC4_REG32(TXP_DST_PTR), 171 VC4_REG32(TXP_DST_PITCH), 172 VC4_REG32(TXP_DIM), 173 VC4_REG32(TXP_DST_CTRL), 174 VC4_REG32(TXP_PROGRESS), 175 }; 176 177 static int vc4_txp_connector_get_modes(struct drm_connector *connector) 178 { 179 struct drm_device *dev = connector->dev; 180 181 return drm_add_modes_noedid(connector, dev->mode_config.max_width, 182 dev->mode_config.max_height); 183 } 184 185 static enum drm_mode_status 186 vc4_txp_connector_mode_valid(struct drm_connector *connector, 187 struct drm_display_mode *mode) 188 { 189 struct drm_device *dev = connector->dev; 190 struct drm_mode_config *mode_config = &dev->mode_config; 191 int w = mode->hdisplay, h = mode->vdisplay; 192 193 if (w < mode_config->min_width || w > mode_config->max_width) 194 return MODE_BAD_HVALUE; 195 196 if (h < mode_config->min_height || h > mode_config->max_height) 197 return MODE_BAD_VVALUE; 198 199 return MODE_OK; 200 } 201 202 static const u32 drm_fmts[] = { 203 DRM_FORMAT_RGB888, 204 DRM_FORMAT_BGR888, 205 DRM_FORMAT_XRGB8888, 206 DRM_FORMAT_XBGR8888, 207 DRM_FORMAT_ARGB8888, 208 DRM_FORMAT_ABGR8888, 209 DRM_FORMAT_RGBX8888, 210 DRM_FORMAT_BGRX8888, 211 DRM_FORMAT_RGBA8888, 212 DRM_FORMAT_BGRA8888, 213 }; 214 215 static const u32 txp_fmts[] = { 216 TXP_FORMAT_RGB888, 217 TXP_FORMAT_BGR888, 218 TXP_FORMAT_ARGB8888, 219 TXP_FORMAT_ABGR8888, 220 TXP_FORMAT_ARGB8888, 221 TXP_FORMAT_ABGR8888, 222 TXP_FORMAT_RGBA8888, 223 TXP_FORMAT_BGRA8888, 224 TXP_FORMAT_RGBA8888, 225 TXP_FORMAT_BGRA8888, 226 }; 227 228 static void vc4_txp_armed(struct drm_crtc_state *state) 229 { 230 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 231 232 vc4_state->txp_armed = true; 233 } 234 235 static int vc4_txp_connector_atomic_check(struct drm_connector *conn, 236 struct drm_atomic_state *state) 237 { 238 struct drm_connector_state *conn_state; 239 struct drm_crtc_state *crtc_state; 240 struct drm_framebuffer *fb; 241 int i; 242 243 conn_state = drm_atomic_get_new_connector_state(state, conn); 244 if (!conn_state->writeback_job) 245 return 0; 246 247 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 248 249 fb = conn_state->writeback_job->fb; 250 if (fb->width != crtc_state->mode.hdisplay || 251 fb->height != crtc_state->mode.vdisplay) { 252 DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n", 253 fb->width, fb->height); 254 return -EINVAL; 255 } 256 257 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { 258 if (fb->format->format == drm_fmts[i]) 259 break; 260 } 261 262 if (i == ARRAY_SIZE(drm_fmts)) 263 return -EINVAL; 264 265 /* Pitch must be aligned on 16 bytes. */ 266 if (fb->pitches[0] & GENMASK(3, 0)) 267 return -EINVAL; 268 269 vc4_txp_armed(crtc_state); 270 271 return 0; 272 } 273 274 static void vc4_txp_connector_atomic_commit(struct drm_connector *conn, 275 struct drm_connector_state *conn_state) 276 { 277 struct vc4_txp *txp = connector_to_vc4_txp(conn); 278 struct drm_gem_cma_object *gem; 279 struct drm_display_mode *mode; 280 struct drm_framebuffer *fb; 281 u32 ctrl; 282 int i; 283 284 if (WARN_ON(!conn_state->writeback_job)) 285 return; 286 287 mode = &conn_state->crtc->state->adjusted_mode; 288 fb = conn_state->writeback_job->fb; 289 290 for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) { 291 if (fb->format->format == drm_fmts[i]) 292 break; 293 } 294 295 if (WARN_ON(i == ARRAY_SIZE(drm_fmts))) 296 return; 297 298 ctrl = TXP_GO | TXP_VSTART_AT_EOF | TXP_EI | 299 VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) | 300 VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT); 301 302 if (fb->format->has_alpha) 303 ctrl |= TXP_ALPHA_ENABLE; 304 305 gem = drm_fb_cma_get_gem_obj(fb, 0); 306 TXP_WRITE(TXP_DST_PTR, gem->paddr + fb->offsets[0]); 307 TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]); 308 TXP_WRITE(TXP_DIM, 309 VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) | 310 VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT)); 311 312 TXP_WRITE(TXP_DST_CTRL, ctrl); 313 314 drm_writeback_queue_job(&txp->connector, conn_state); 315 } 316 317 static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = { 318 .get_modes = vc4_txp_connector_get_modes, 319 .mode_valid = vc4_txp_connector_mode_valid, 320 .atomic_check = vc4_txp_connector_atomic_check, 321 .atomic_commit = vc4_txp_connector_atomic_commit, 322 }; 323 324 static enum drm_connector_status 325 vc4_txp_connector_detect(struct drm_connector *connector, bool force) 326 { 327 return connector_status_connected; 328 } 329 330 static void vc4_txp_connector_destroy(struct drm_connector *connector) 331 { 332 drm_connector_unregister(connector); 333 drm_connector_cleanup(connector); 334 } 335 336 static const struct drm_connector_funcs vc4_txp_connector_funcs = { 337 .detect = vc4_txp_connector_detect, 338 .fill_modes = drm_helper_probe_single_connector_modes, 339 .destroy = vc4_txp_connector_destroy, 340 .reset = drm_atomic_helper_connector_reset, 341 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 342 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 343 }; 344 345 static void vc4_txp_encoder_disable(struct drm_encoder *encoder) 346 { 347 struct vc4_txp *txp = encoder_to_vc4_txp(encoder); 348 349 if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) { 350 unsigned long timeout = jiffies + msecs_to_jiffies(1000); 351 352 TXP_WRITE(TXP_DST_CTRL, TXP_ABORT); 353 354 while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY && 355 time_before(jiffies, timeout)) 356 ; 357 358 WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY); 359 } 360 361 TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN); 362 } 363 364 static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = { 365 .disable = vc4_txp_encoder_disable, 366 }; 367 368 static int vc4_txp_enable_vblank(struct drm_crtc *crtc) 369 { 370 return 0; 371 } 372 373 static void vc4_txp_disable_vblank(struct drm_crtc *crtc) {} 374 375 static const struct drm_crtc_funcs vc4_txp_crtc_funcs = { 376 .set_config = drm_atomic_helper_set_config, 377 .destroy = vc4_crtc_destroy, 378 .page_flip = vc4_page_flip, 379 .reset = vc4_crtc_reset, 380 .atomic_duplicate_state = vc4_crtc_duplicate_state, 381 .atomic_destroy_state = vc4_crtc_destroy_state, 382 .gamma_set = drm_atomic_helper_legacy_gamma_set, 383 .enable_vblank = vc4_txp_enable_vblank, 384 .disable_vblank = vc4_txp_disable_vblank, 385 }; 386 387 static int vc4_txp_atomic_check(struct drm_crtc *crtc, 388 struct drm_crtc_state *state) 389 { 390 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 391 int ret; 392 393 ret = vc4_hvs_atomic_check(crtc, state); 394 if (ret) 395 return ret; 396 397 state->no_vblank = true; 398 vc4_state->feed_txp = true; 399 400 return 0; 401 } 402 403 static void vc4_txp_atomic_enable(struct drm_crtc *crtc, 404 struct drm_crtc_state *old_state) 405 { 406 drm_crtc_vblank_on(crtc); 407 vc4_hvs_atomic_enable(crtc, old_state); 408 } 409 410 static void vc4_txp_atomic_disable(struct drm_crtc *crtc, 411 struct drm_crtc_state *old_state) 412 { 413 struct drm_device *dev = crtc->dev; 414 415 /* Disable vblank irq handling before crtc is disabled. */ 416 drm_crtc_vblank_off(crtc); 417 418 vc4_hvs_atomic_disable(crtc, old_state); 419 420 /* 421 * Make sure we issue a vblank event after disabling the CRTC if 422 * someone was waiting it. 423 */ 424 if (crtc->state->event) { 425 unsigned long flags; 426 427 spin_lock_irqsave(&dev->event_lock, flags); 428 drm_crtc_send_vblank_event(crtc, crtc->state->event); 429 crtc->state->event = NULL; 430 spin_unlock_irqrestore(&dev->event_lock, flags); 431 } 432 } 433 434 static const struct drm_crtc_helper_funcs vc4_txp_crtc_helper_funcs = { 435 .atomic_check = vc4_txp_atomic_check, 436 .atomic_flush = vc4_hvs_atomic_flush, 437 .atomic_enable = vc4_txp_atomic_enable, 438 .atomic_disable = vc4_txp_atomic_disable, 439 }; 440 441 static irqreturn_t vc4_txp_interrupt(int irq, void *data) 442 { 443 struct vc4_txp *txp = data; 444 struct vc4_crtc *vc4_crtc = &txp->base; 445 446 TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI); 447 vc4_crtc_handle_vblank(vc4_crtc); 448 drm_writeback_signal_completion(&txp->connector, 0); 449 450 return IRQ_HANDLED; 451 } 452 453 static const struct vc4_crtc_data vc4_txp_crtc_data = { 454 .hvs_available_channels = BIT(2), 455 .hvs_output = 2, 456 }; 457 458 static int vc4_txp_bind(struct device *dev, struct device *master, void *data) 459 { 460 struct platform_device *pdev = to_platform_device(dev); 461 struct drm_device *drm = dev_get_drvdata(master); 462 struct vc4_dev *vc4 = to_vc4_dev(drm); 463 struct vc4_crtc *vc4_crtc; 464 struct vc4_txp *txp; 465 struct drm_crtc *crtc; 466 struct drm_encoder *encoder; 467 int ret, irq; 468 469 irq = platform_get_irq(pdev, 0); 470 if (irq < 0) 471 return irq; 472 473 txp = devm_kzalloc(dev, sizeof(*txp), GFP_KERNEL); 474 if (!txp) 475 return -ENOMEM; 476 vc4_crtc = &txp->base; 477 crtc = &vc4_crtc->base; 478 479 vc4_crtc->pdev = pdev; 480 vc4_crtc->data = &vc4_txp_crtc_data; 481 482 txp->pdev = pdev; 483 484 txp->regs = vc4_ioremap_regs(pdev, 0); 485 if (IS_ERR(txp->regs)) 486 return PTR_ERR(txp->regs); 487 txp->regset.base = txp->regs; 488 txp->regset.regs = txp_regs; 489 txp->regset.nregs = ARRAY_SIZE(txp_regs); 490 491 drm_connector_helper_add(&txp->connector.base, 492 &vc4_txp_connector_helper_funcs); 493 ret = drm_writeback_connector_init(drm, &txp->connector, 494 &vc4_txp_connector_funcs, 495 &vc4_txp_encoder_helper_funcs, 496 drm_fmts, ARRAY_SIZE(drm_fmts)); 497 if (ret) 498 return ret; 499 500 ret = vc4_crtc_init(drm, vc4_crtc, 501 &vc4_txp_crtc_funcs, &vc4_txp_crtc_helper_funcs); 502 if (ret) 503 return ret; 504 505 encoder = &txp->connector.encoder; 506 encoder->possible_crtcs |= drm_crtc_mask(crtc); 507 508 ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0, 509 dev_name(dev), txp); 510 if (ret) 511 return ret; 512 513 dev_set_drvdata(dev, txp); 514 vc4->txp = txp; 515 516 vc4_debugfs_add_regset32(drm, "txp_regs", &txp->regset); 517 518 return 0; 519 } 520 521 static void vc4_txp_unbind(struct device *dev, struct device *master, 522 void *data) 523 { 524 struct drm_device *drm = dev_get_drvdata(master); 525 struct vc4_dev *vc4 = to_vc4_dev(drm); 526 struct vc4_txp *txp = dev_get_drvdata(dev); 527 528 vc4_txp_connector_destroy(&txp->connector.base); 529 530 vc4->txp = NULL; 531 } 532 533 static const struct component_ops vc4_txp_ops = { 534 .bind = vc4_txp_bind, 535 .unbind = vc4_txp_unbind, 536 }; 537 538 static int vc4_txp_probe(struct platform_device *pdev) 539 { 540 return component_add(&pdev->dev, &vc4_txp_ops); 541 } 542 543 static int vc4_txp_remove(struct platform_device *pdev) 544 { 545 component_del(&pdev->dev, &vc4_txp_ops); 546 return 0; 547 } 548 549 static const struct of_device_id vc4_txp_dt_match[] = { 550 { .compatible = "brcm,bcm2835-txp" }, 551 { /* sentinel */ }, 552 }; 553 554 struct platform_driver vc4_txp_driver = { 555 .probe = vc4_txp_probe, 556 .remove = vc4_txp_remove, 557 .driver = { 558 .name = "vc4_txp", 559 .of_match_table = vc4_txp_dt_match, 560 }, 561 }; 562