1 /* 2 * Copyright © 2014-2015 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Render command list generation 26 * 27 * In the V3D hardware, render command lists are what load and store 28 * tiles of a framebuffer and optionally call out to binner-generated 29 * command lists to do the 3D drawing for that tile. 30 * 31 * In the VC4 driver, render command list generation is performed by the 32 * kernel instead of userspace. We do this because validating a 33 * user-submitted command list is hard to get right and has high CPU overhead, 34 * while the number of valid configurations for render command lists is 35 * actually fairly low. 36 */ 37 38 #include "uapi/drm/vc4_drm.h" 39 #include "vc4_drv.h" 40 #include "vc4_packet.h" 41 42 struct vc4_rcl_setup { 43 struct drm_gem_cma_object *color_read; 44 struct drm_gem_cma_object *color_write; 45 struct drm_gem_cma_object *zs_read; 46 struct drm_gem_cma_object *zs_write; 47 struct drm_gem_cma_object *msaa_color_write; 48 struct drm_gem_cma_object *msaa_zs_write; 49 50 struct drm_gem_cma_object *rcl; 51 u32 next_offset; 52 53 u32 next_write_bo_index; 54 }; 55 56 static inline void rcl_u8(struct vc4_rcl_setup *setup, u8 val) 57 { 58 *(u8 *)(setup->rcl->vaddr + setup->next_offset) = val; 59 setup->next_offset += 1; 60 } 61 62 static inline void rcl_u16(struct vc4_rcl_setup *setup, u16 val) 63 { 64 *(u16 *)(setup->rcl->vaddr + setup->next_offset) = val; 65 setup->next_offset += 2; 66 } 67 68 static inline void rcl_u32(struct vc4_rcl_setup *setup, u32 val) 69 { 70 *(u32 *)(setup->rcl->vaddr + setup->next_offset) = val; 71 setup->next_offset += 4; 72 } 73 74 /* 75 * Emits a no-op STORE_TILE_BUFFER_GENERAL. 76 * 77 * If we emit a PACKET_TILE_COORDINATES, it must be followed by a store of 78 * some sort before another load is triggered. 79 */ 80 static void vc4_store_before_load(struct vc4_rcl_setup *setup) 81 { 82 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); 83 rcl_u16(setup, 84 VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE, 85 VC4_LOADSTORE_TILE_BUFFER_BUFFER) | 86 VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR | 87 VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR | 88 VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR); 89 rcl_u32(setup, 0); /* no address, since we're in None mode */ 90 } 91 92 /* 93 * Calculates the physical address of the start of a tile in a RCL surface. 94 * 95 * Unlike the other load/store packets, 96 * VC4_PACKET_LOAD/STORE_FULL_RES_TILE_BUFFER don't look at the tile 97 * coordinates packet, and instead just store to the address given. 98 */ 99 static uint32_t vc4_full_res_offset(struct vc4_exec_info *exec, 100 struct drm_gem_cma_object *bo, 101 struct drm_vc4_submit_rcl_surface *surf, 102 uint8_t x, uint8_t y) 103 { 104 return bo->paddr + surf->offset + VC4_TILE_BUFFER_SIZE * 105 (DIV_ROUND_UP(exec->args->width, 32) * y + x); 106 } 107 108 /* 109 * Emits a PACKET_TILE_COORDINATES if one isn't already pending. 110 * 111 * The tile coordinates packet triggers a pending load if there is one, are 112 * used for clipping during rendering, and determine where loads/stores happen 113 * relative to their base address. 114 */ 115 static void vc4_tile_coordinates(struct vc4_rcl_setup *setup, 116 uint32_t x, uint32_t y) 117 { 118 rcl_u8(setup, VC4_PACKET_TILE_COORDINATES); 119 rcl_u8(setup, x); 120 rcl_u8(setup, y); 121 } 122 123 static void emit_tile(struct vc4_exec_info *exec, 124 struct vc4_rcl_setup *setup, 125 uint8_t x, uint8_t y, bool first, bool last) 126 { 127 struct drm_vc4_submit_cl *args = exec->args; 128 bool has_bin = args->bin_cl_size != 0; 129 130 /* Note that the load doesn't actually occur until the 131 * tile coords packet is processed, and only one load 132 * may be outstanding at a time. 133 */ 134 if (setup->color_read) { 135 if (args->color_read.flags & 136 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 137 rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER); 138 rcl_u32(setup, 139 vc4_full_res_offset(exec, setup->color_read, 140 &args->color_read, x, y) | 141 VC4_LOADSTORE_FULL_RES_DISABLE_ZS); 142 } else { 143 rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); 144 rcl_u16(setup, args->color_read.bits); 145 rcl_u32(setup, setup->color_read->paddr + 146 args->color_read.offset); 147 } 148 } 149 150 if (setup->zs_read) { 151 if (args->zs_read.flags & 152 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 153 rcl_u8(setup, VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER); 154 rcl_u32(setup, 155 vc4_full_res_offset(exec, setup->zs_read, 156 &args->zs_read, x, y) | 157 VC4_LOADSTORE_FULL_RES_DISABLE_COLOR); 158 } else { 159 if (setup->color_read) { 160 /* Exec previous load. */ 161 vc4_tile_coordinates(setup, x, y); 162 vc4_store_before_load(setup); 163 } 164 165 rcl_u8(setup, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL); 166 rcl_u16(setup, args->zs_read.bits); 167 rcl_u32(setup, setup->zs_read->paddr + 168 args->zs_read.offset); 169 } 170 } 171 172 /* Clipping depends on tile coordinates having been 173 * emitted, so we always need one here. 174 */ 175 vc4_tile_coordinates(setup, x, y); 176 177 /* Wait for the binner before jumping to the first 178 * tile's lists. 179 */ 180 if (first && has_bin) 181 rcl_u8(setup, VC4_PACKET_WAIT_ON_SEMAPHORE); 182 183 if (has_bin) { 184 rcl_u8(setup, VC4_PACKET_BRANCH_TO_SUB_LIST); 185 rcl_u32(setup, (exec->tile_bo->paddr + 186 exec->tile_alloc_offset + 187 (y * exec->bin_tiles_x + x) * 32)); 188 } 189 190 if (setup->msaa_color_write) { 191 bool last_tile_write = (!setup->msaa_zs_write && 192 !setup->zs_write && 193 !setup->color_write); 194 uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_ZS; 195 196 if (!last_tile_write) 197 bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL; 198 else if (last) 199 bits |= VC4_LOADSTORE_FULL_RES_EOF; 200 rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER); 201 rcl_u32(setup, 202 vc4_full_res_offset(exec, setup->msaa_color_write, 203 &args->msaa_color_write, x, y) | 204 bits); 205 } 206 207 if (setup->msaa_zs_write) { 208 bool last_tile_write = (!setup->zs_write && 209 !setup->color_write); 210 uint32_t bits = VC4_LOADSTORE_FULL_RES_DISABLE_COLOR; 211 212 if (setup->msaa_color_write) 213 vc4_tile_coordinates(setup, x, y); 214 if (!last_tile_write) 215 bits |= VC4_LOADSTORE_FULL_RES_DISABLE_CLEAR_ALL; 216 else if (last) 217 bits |= VC4_LOADSTORE_FULL_RES_EOF; 218 rcl_u8(setup, VC4_PACKET_STORE_FULL_RES_TILE_BUFFER); 219 rcl_u32(setup, 220 vc4_full_res_offset(exec, setup->msaa_zs_write, 221 &args->msaa_zs_write, x, y) | 222 bits); 223 } 224 225 if (setup->zs_write) { 226 bool last_tile_write = !setup->color_write; 227 228 if (setup->msaa_color_write || setup->msaa_zs_write) 229 vc4_tile_coordinates(setup, x, y); 230 231 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); 232 rcl_u16(setup, args->zs_write.bits | 233 (last_tile_write ? 234 0 : VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR)); 235 rcl_u32(setup, 236 (setup->zs_write->paddr + args->zs_write.offset) | 237 ((last && last_tile_write) ? 238 VC4_LOADSTORE_TILE_BUFFER_EOF : 0)); 239 } 240 241 if (setup->color_write) { 242 if (setup->msaa_color_write || setup->msaa_zs_write || 243 setup->zs_write) { 244 vc4_tile_coordinates(setup, x, y); 245 } 246 247 if (last) 248 rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER_AND_EOF); 249 else 250 rcl_u8(setup, VC4_PACKET_STORE_MS_TILE_BUFFER); 251 } 252 } 253 254 static int vc4_create_rcl_bo(struct drm_device *dev, struct vc4_exec_info *exec, 255 struct vc4_rcl_setup *setup) 256 { 257 struct drm_vc4_submit_cl *args = exec->args; 258 bool has_bin = args->bin_cl_size != 0; 259 uint8_t min_x_tile = args->min_x_tile; 260 uint8_t min_y_tile = args->min_y_tile; 261 uint8_t max_x_tile = args->max_x_tile; 262 uint8_t max_y_tile = args->max_y_tile; 263 uint8_t xtiles = max_x_tile - min_x_tile + 1; 264 uint8_t ytiles = max_y_tile - min_y_tile + 1; 265 uint8_t x, y; 266 uint32_t size, loop_body_size; 267 268 size = VC4_PACKET_TILE_RENDERING_MODE_CONFIG_SIZE; 269 loop_body_size = VC4_PACKET_TILE_COORDINATES_SIZE; 270 271 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) { 272 size += VC4_PACKET_CLEAR_COLORS_SIZE + 273 VC4_PACKET_TILE_COORDINATES_SIZE + 274 VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; 275 } 276 277 if (setup->color_read) { 278 if (args->color_read.flags & 279 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 280 loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE; 281 } else { 282 loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; 283 } 284 } 285 if (setup->zs_read) { 286 if (args->zs_read.flags & 287 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 288 loop_body_size += VC4_PACKET_LOAD_FULL_RES_TILE_BUFFER_SIZE; 289 } else { 290 if (setup->color_read && 291 !(args->color_read.flags & 292 VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES)) { 293 loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE; 294 loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; 295 } 296 loop_body_size += VC4_PACKET_LOAD_TILE_BUFFER_GENERAL_SIZE; 297 } 298 } 299 300 if (has_bin) { 301 size += VC4_PACKET_WAIT_ON_SEMAPHORE_SIZE; 302 loop_body_size += VC4_PACKET_BRANCH_TO_SUB_LIST_SIZE; 303 } 304 305 if (setup->msaa_color_write) 306 loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE; 307 if (setup->msaa_zs_write) 308 loop_body_size += VC4_PACKET_STORE_FULL_RES_TILE_BUFFER_SIZE; 309 310 if (setup->zs_write) 311 loop_body_size += VC4_PACKET_STORE_TILE_BUFFER_GENERAL_SIZE; 312 if (setup->color_write) 313 loop_body_size += VC4_PACKET_STORE_MS_TILE_BUFFER_SIZE; 314 315 /* We need a VC4_PACKET_TILE_COORDINATES in between each store. */ 316 loop_body_size += VC4_PACKET_TILE_COORDINATES_SIZE * 317 ((setup->msaa_color_write != NULL) + 318 (setup->msaa_zs_write != NULL) + 319 (setup->color_write != NULL) + 320 (setup->zs_write != NULL) - 1); 321 322 size += xtiles * ytiles * loop_body_size; 323 324 setup->rcl = &vc4_bo_create(dev, size, true)->base; 325 if (IS_ERR(setup->rcl)) 326 return PTR_ERR(setup->rcl); 327 list_add_tail(&to_vc4_bo(&setup->rcl->base)->unref_head, 328 &exec->unref_list); 329 330 /* The tile buffer gets cleared when the previous tile is stored. If 331 * the clear values changed between frames, then the tile buffer has 332 * stale clear values in it, so we have to do a store in None mode (no 333 * writes) so that we trigger the tile buffer clear. 334 */ 335 if (args->flags & VC4_SUBMIT_CL_USE_CLEAR_COLOR) { 336 rcl_u8(setup, VC4_PACKET_CLEAR_COLORS); 337 rcl_u32(setup, args->clear_color[0]); 338 rcl_u32(setup, args->clear_color[1]); 339 rcl_u32(setup, args->clear_z); 340 rcl_u8(setup, args->clear_s); 341 342 vc4_tile_coordinates(setup, 0, 0); 343 344 rcl_u8(setup, VC4_PACKET_STORE_TILE_BUFFER_GENERAL); 345 rcl_u16(setup, VC4_LOADSTORE_TILE_BUFFER_NONE); 346 rcl_u32(setup, 0); /* no address, since we're in None mode */ 347 } 348 349 rcl_u8(setup, VC4_PACKET_TILE_RENDERING_MODE_CONFIG); 350 rcl_u32(setup, 351 (setup->color_write ? (setup->color_write->paddr + 352 args->color_write.offset) : 353 0)); 354 rcl_u16(setup, args->width); 355 rcl_u16(setup, args->height); 356 rcl_u16(setup, args->color_write.bits); 357 358 for (y = min_y_tile; y <= max_y_tile; y++) { 359 for (x = min_x_tile; x <= max_x_tile; x++) { 360 bool first = (x == min_x_tile && y == min_y_tile); 361 bool last = (x == max_x_tile && y == max_y_tile); 362 363 emit_tile(exec, setup, x, y, first, last); 364 } 365 } 366 367 BUG_ON(setup->next_offset != size); 368 exec->ct1ca = setup->rcl->paddr; 369 exec->ct1ea = setup->rcl->paddr + setup->next_offset; 370 371 return 0; 372 } 373 374 static int vc4_full_res_bounds_check(struct vc4_exec_info *exec, 375 struct drm_gem_cma_object *obj, 376 struct drm_vc4_submit_rcl_surface *surf) 377 { 378 struct drm_vc4_submit_cl *args = exec->args; 379 u32 render_tiles_stride = DIV_ROUND_UP(exec->args->width, 32); 380 381 if (surf->offset > obj->base.size) { 382 DRM_ERROR("surface offset %d > BO size %zd\n", 383 surf->offset, obj->base.size); 384 return -EINVAL; 385 } 386 387 if ((obj->base.size - surf->offset) / VC4_TILE_BUFFER_SIZE < 388 render_tiles_stride * args->max_y_tile + args->max_x_tile) { 389 DRM_ERROR("MSAA tile %d, %d out of bounds " 390 "(bo size %zd, offset %d).\n", 391 args->max_x_tile, args->max_y_tile, 392 obj->base.size, 393 surf->offset); 394 return -EINVAL; 395 } 396 397 return 0; 398 } 399 400 static int vc4_rcl_msaa_surface_setup(struct vc4_exec_info *exec, 401 struct drm_gem_cma_object **obj, 402 struct drm_vc4_submit_rcl_surface *surf) 403 { 404 if (surf->flags != 0 || surf->bits != 0) { 405 DRM_ERROR("MSAA surface had nonzero flags/bits\n"); 406 return -EINVAL; 407 } 408 409 if (surf->hindex == ~0) 410 return 0; 411 412 *obj = vc4_use_bo(exec, surf->hindex); 413 if (!*obj) 414 return -EINVAL; 415 416 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj; 417 418 if (surf->offset & 0xf) { 419 DRM_ERROR("MSAA write must be 16b aligned.\n"); 420 return -EINVAL; 421 } 422 423 return vc4_full_res_bounds_check(exec, *obj, surf); 424 } 425 426 static int vc4_rcl_surface_setup(struct vc4_exec_info *exec, 427 struct drm_gem_cma_object **obj, 428 struct drm_vc4_submit_rcl_surface *surf, 429 bool is_write) 430 { 431 uint8_t tiling = VC4_GET_FIELD(surf->bits, 432 VC4_LOADSTORE_TILE_BUFFER_TILING); 433 uint8_t buffer = VC4_GET_FIELD(surf->bits, 434 VC4_LOADSTORE_TILE_BUFFER_BUFFER); 435 uint8_t format = VC4_GET_FIELD(surf->bits, 436 VC4_LOADSTORE_TILE_BUFFER_FORMAT); 437 int cpp; 438 int ret; 439 440 if (surf->flags & ~VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 441 DRM_ERROR("Extra flags set\n"); 442 return -EINVAL; 443 } 444 445 if (surf->hindex == ~0) 446 return 0; 447 448 *obj = vc4_use_bo(exec, surf->hindex); 449 if (!*obj) 450 return -EINVAL; 451 452 if (is_write) 453 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj; 454 455 if (surf->flags & VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES) { 456 if (surf == &exec->args->zs_write) { 457 DRM_ERROR("general zs write may not be a full-res.\n"); 458 return -EINVAL; 459 } 460 461 if (surf->bits != 0) { 462 DRM_ERROR("load/store general bits set with " 463 "full res load/store.\n"); 464 return -EINVAL; 465 } 466 467 ret = vc4_full_res_bounds_check(exec, *obj, surf); 468 if (ret) 469 return ret; 470 471 return 0; 472 } 473 474 if (surf->bits & ~(VC4_LOADSTORE_TILE_BUFFER_TILING_MASK | 475 VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK | 476 VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK)) { 477 DRM_ERROR("Unknown bits in load/store: 0x%04x\n", 478 surf->bits); 479 return -EINVAL; 480 } 481 482 if (tiling > VC4_TILING_FORMAT_LT) { 483 DRM_ERROR("Bad tiling format\n"); 484 return -EINVAL; 485 } 486 487 if (buffer == VC4_LOADSTORE_TILE_BUFFER_ZS) { 488 if (format != 0) { 489 DRM_ERROR("No color format should be set for ZS\n"); 490 return -EINVAL; 491 } 492 cpp = 4; 493 } else if (buffer == VC4_LOADSTORE_TILE_BUFFER_COLOR) { 494 switch (format) { 495 case VC4_LOADSTORE_TILE_BUFFER_BGR565: 496 case VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER: 497 cpp = 2; 498 break; 499 case VC4_LOADSTORE_TILE_BUFFER_RGBA8888: 500 cpp = 4; 501 break; 502 default: 503 DRM_ERROR("Bad tile buffer format\n"); 504 return -EINVAL; 505 } 506 } else { 507 DRM_ERROR("Bad load/store buffer %d.\n", buffer); 508 return -EINVAL; 509 } 510 511 if (surf->offset & 0xf) { 512 DRM_ERROR("load/store buffer must be 16b aligned.\n"); 513 return -EINVAL; 514 } 515 516 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, 517 exec->args->width, exec->args->height, cpp)) { 518 return -EINVAL; 519 } 520 521 return 0; 522 } 523 524 static int 525 vc4_rcl_render_config_surface_setup(struct vc4_exec_info *exec, 526 struct vc4_rcl_setup *setup, 527 struct drm_gem_cma_object **obj, 528 struct drm_vc4_submit_rcl_surface *surf) 529 { 530 uint8_t tiling = VC4_GET_FIELD(surf->bits, 531 VC4_RENDER_CONFIG_MEMORY_FORMAT); 532 uint8_t format = VC4_GET_FIELD(surf->bits, 533 VC4_RENDER_CONFIG_FORMAT); 534 int cpp; 535 536 if (surf->flags != 0) { 537 DRM_ERROR("No flags supported on render config.\n"); 538 return -EINVAL; 539 } 540 541 if (surf->bits & ~(VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK | 542 VC4_RENDER_CONFIG_FORMAT_MASK | 543 VC4_RENDER_CONFIG_MS_MODE_4X | 544 VC4_RENDER_CONFIG_DECIMATE_MODE_4X)) { 545 DRM_ERROR("Unknown bits in render config: 0x%04x\n", 546 surf->bits); 547 return -EINVAL; 548 } 549 550 if (surf->hindex == ~0) 551 return 0; 552 553 *obj = vc4_use_bo(exec, surf->hindex); 554 if (!*obj) 555 return -EINVAL; 556 557 exec->rcl_write_bo[exec->rcl_write_bo_count++] = *obj; 558 559 if (tiling > VC4_TILING_FORMAT_LT) { 560 DRM_ERROR("Bad tiling format\n"); 561 return -EINVAL; 562 } 563 564 switch (format) { 565 case VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED: 566 case VC4_RENDER_CONFIG_FORMAT_BGR565: 567 cpp = 2; 568 break; 569 case VC4_RENDER_CONFIG_FORMAT_RGBA8888: 570 cpp = 4; 571 break; 572 default: 573 DRM_ERROR("Bad tile buffer format\n"); 574 return -EINVAL; 575 } 576 577 if (!vc4_check_tex_size(exec, *obj, surf->offset, tiling, 578 exec->args->width, exec->args->height, cpp)) { 579 return -EINVAL; 580 } 581 582 return 0; 583 } 584 585 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec) 586 { 587 struct vc4_rcl_setup setup = {0}; 588 struct drm_vc4_submit_cl *args = exec->args; 589 bool has_bin = args->bin_cl_size != 0; 590 int ret; 591 592 if (args->min_x_tile > args->max_x_tile || 593 args->min_y_tile > args->max_y_tile) { 594 DRM_ERROR("Bad render tile set (%d,%d)-(%d,%d)\n", 595 args->min_x_tile, args->min_y_tile, 596 args->max_x_tile, args->max_y_tile); 597 return -EINVAL; 598 } 599 600 if (has_bin && 601 (args->max_x_tile > exec->bin_tiles_x || 602 args->max_y_tile > exec->bin_tiles_y)) { 603 DRM_ERROR("Render tiles (%d,%d) outside of bin config " 604 "(%d,%d)\n", 605 args->max_x_tile, args->max_y_tile, 606 exec->bin_tiles_x, exec->bin_tiles_y); 607 return -EINVAL; 608 } 609 610 ret = vc4_rcl_render_config_surface_setup(exec, &setup, 611 &setup.color_write, 612 &args->color_write); 613 if (ret) 614 return ret; 615 616 ret = vc4_rcl_surface_setup(exec, &setup.color_read, &args->color_read, 617 false); 618 if (ret) 619 return ret; 620 621 ret = vc4_rcl_surface_setup(exec, &setup.zs_read, &args->zs_read, 622 false); 623 if (ret) 624 return ret; 625 626 ret = vc4_rcl_surface_setup(exec, &setup.zs_write, &args->zs_write, 627 true); 628 if (ret) 629 return ret; 630 631 ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_color_write, 632 &args->msaa_color_write); 633 if (ret) 634 return ret; 635 636 ret = vc4_rcl_msaa_surface_setup(exec, &setup.msaa_zs_write, 637 &args->msaa_zs_write); 638 if (ret) 639 return ret; 640 641 /* We shouldn't even have the job submitted to us if there's no 642 * surface to write out. 643 */ 644 if (!setup.color_write && !setup.zs_write && 645 !setup.msaa_color_write && !setup.msaa_zs_write) { 646 DRM_ERROR("RCL requires color or Z/S write\n"); 647 return -EINVAL; 648 } 649 650 return vc4_create_rcl_bo(dev, exec, &setup); 651 } 652