1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright © 2014-2015 Broadcom 4 */ 5 6 #ifndef VC4_REGS_H 7 #define VC4_REGS_H 8 9 #include <linux/bitfield.h> 10 #include <linux/bitops.h> 11 12 #define VC4_MASK(high, low) ((u32)GENMASK(high, low)) 13 /* Using the GNU statement expression extension */ 14 #define VC4_SET_FIELD(value, field) \ 15 ({ \ 16 WARN_ON(!FIELD_FIT(field##_MASK, value)); \ 17 FIELD_PREP(field##_MASK, value); \ 18 }) 19 20 #define VC4_GET_FIELD(word, field) FIELD_GET(field##_MASK, word) 21 22 #define V3D_IDENT0 0x00000 23 # define V3D_EXPECTED_IDENT0 \ 24 ((2 << 24) | \ 25 ('V' << 0) | \ 26 ('3' << 8) | \ 27 ('D' << 16)) 28 29 #define V3D_IDENT1 0x00004 30 /* Multiples of 1kb */ 31 # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28) 32 # define V3D_IDENT1_VPM_SIZE_SHIFT 28 33 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16) 34 # define V3D_IDENT1_NSEM_SHIFT 16 35 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12) 36 # define V3D_IDENT1_TUPS_SHIFT 12 37 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8) 38 # define V3D_IDENT1_QUPS_SHIFT 8 39 # define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4) 40 # define V3D_IDENT1_NSLC_SHIFT 4 41 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0) 42 # define V3D_IDENT1_REV_SHIFT 0 43 44 #define V3D_IDENT2 0x00008 45 #define V3D_SCRATCH 0x00010 46 #define V3D_L2CACTL 0x00020 47 # define V3D_L2CACTL_L2CCLR BIT(2) 48 # define V3D_L2CACTL_L2CDIS BIT(1) 49 # define V3D_L2CACTL_L2CENA BIT(0) 50 51 #define V3D_SLCACTL 0x00024 52 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24) 53 # define V3D_SLCACTL_T1CC_SHIFT 24 54 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16) 55 # define V3D_SLCACTL_T0CC_SHIFT 16 56 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8) 57 # define V3D_SLCACTL_UCC_SHIFT 8 58 # define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0) 59 # define V3D_SLCACTL_ICC_SHIFT 0 60 61 #define V3D_INTCTL 0x00030 62 #define V3D_INTENA 0x00034 63 #define V3D_INTDIS 0x00038 64 # define V3D_INT_SPILLUSE BIT(3) 65 # define V3D_INT_OUTOMEM BIT(2) 66 # define V3D_INT_FLDONE BIT(1) 67 # define V3D_INT_FRDONE BIT(0) 68 69 #define V3D_CT0CS 0x00100 70 #define V3D_CT1CS 0x00104 71 #define V3D_CTNCS(n) (V3D_CT0CS + 4 * n) 72 # define V3D_CTRSTA BIT(15) 73 # define V3D_CTSEMA BIT(12) 74 # define V3D_CTRTSD BIT(8) 75 # define V3D_CTRUN BIT(5) 76 # define V3D_CTSUBS BIT(4) 77 # define V3D_CTERR BIT(3) 78 # define V3D_CTMODE BIT(0) 79 80 #define V3D_CT0EA 0x00108 81 #define V3D_CT1EA 0x0010c 82 #define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n)) 83 #define V3D_CT0CA 0x00110 84 #define V3D_CT1CA 0x00114 85 #define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n)) 86 #define V3D_CT00RA0 0x00118 87 #define V3D_CT01RA0 0x0011c 88 #define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n)) 89 #define V3D_CT0LC 0x00120 90 #define V3D_CT1LC 0x00124 91 #define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n)) 92 #define V3D_CT0PC 0x00128 93 #define V3D_CT1PC 0x0012c 94 #define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n)) 95 96 #define V3D_PCS 0x00130 97 # define V3D_BMOOM BIT(8) 98 # define V3D_RMBUSY BIT(3) 99 # define V3D_RMACTIVE BIT(2) 100 # define V3D_BMBUSY BIT(1) 101 # define V3D_BMACTIVE BIT(0) 102 103 #define V3D_BFC 0x00134 104 #define V3D_RFC 0x00138 105 #define V3D_BPCA 0x00300 106 #define V3D_BPCS 0x00304 107 #define V3D_BPOA 0x00308 108 #define V3D_BPOS 0x0030c 109 #define V3D_BXCF 0x00310 110 #define V3D_SQRSV0 0x00410 111 #define V3D_SQRSV1 0x00414 112 #define V3D_SQCNTL 0x00418 113 #define V3D_SRQPC 0x00430 114 #define V3D_SRQUA 0x00434 115 #define V3D_SRQUL 0x00438 116 #define V3D_SRQCS 0x0043c 117 #define V3D_VPACNTL 0x00500 118 #define V3D_VPMBASE 0x00504 119 #define V3D_PCTRC 0x00670 120 #define V3D_PCTRE 0x00674 121 # define V3D_PCTRE_EN BIT(31) 122 #define V3D_PCTR(x) (0x00680 + ((x) * 8)) 123 #define V3D_PCTRS(x) (0x00684 + ((x) * 8)) 124 #define V3D_DBGE 0x00f00 125 #define V3D_FDBGO 0x00f04 126 #define V3D_FDBGB 0x00f08 127 #define V3D_FDBGR 0x00f0c 128 #define V3D_FDBGS 0x00f10 129 #define V3D_ERRSTAT 0x00f20 130 131 #define PV_CONTROL 0x00 132 # define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21) 133 # define PV_CONTROL_FORMAT_SHIFT 21 134 # define PV_CONTROL_FORMAT_24 0 135 # define PV_CONTROL_FORMAT_DSIV_16 1 136 # define PV_CONTROL_FORMAT_DSIC_16 2 137 # define PV_CONTROL_FORMAT_DSIV_18 3 138 # define PV_CONTROL_FORMAT_DSIV_24 4 139 140 # define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15) 141 # define PV_CONTROL_FIFO_LEVEL_SHIFT 15 142 # define PV_CONTROL_CLR_AT_START BIT(14) 143 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13) 144 # define PV_CONTROL_WAIT_HSTART BIT(12) 145 # define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4) 146 # define PV_CONTROL_PIXEL_REP_SHIFT 4 147 # define PV_CONTROL_CLK_SELECT_DSI 0 148 # define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1 149 # define PV_CONTROL_CLK_SELECT_VEC 2 150 # define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2) 151 # define PV_CONTROL_CLK_SELECT_SHIFT 2 152 # define PV_CONTROL_FIFO_CLR BIT(1) 153 # define PV_CONTROL_EN BIT(0) 154 155 #define PV_V_CONTROL 0x04 156 # define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6) 157 # define PV_VCONTROL_ODD_DELAY_SHIFT 6 158 # define PV_VCONTROL_ODD_FIRST BIT(5) 159 # define PV_VCONTROL_INTERLACE BIT(4) 160 # define PV_VCONTROL_DSI BIT(3) 161 # define PV_VCONTROL_COMMAND BIT(2) 162 # define PV_VCONTROL_CONTINUOUS BIT(1) 163 # define PV_VCONTROL_VIDEN BIT(0) 164 165 #define PV_VSYNCD_EVEN 0x08 166 167 #define PV_HORZA 0x0c 168 # define PV_HORZA_HBP_MASK VC4_MASK(31, 16) 169 # define PV_HORZA_HBP_SHIFT 16 170 # define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0) 171 # define PV_HORZA_HSYNC_SHIFT 0 172 173 #define PV_HORZB 0x10 174 # define PV_HORZB_HFP_MASK VC4_MASK(31, 16) 175 # define PV_HORZB_HFP_SHIFT 16 176 # define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0) 177 # define PV_HORZB_HACTIVE_SHIFT 0 178 179 #define PV_VERTA 0x14 180 # define PV_VERTA_VBP_MASK VC4_MASK(31, 16) 181 # define PV_VERTA_VBP_SHIFT 16 182 # define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0) 183 # define PV_VERTA_VSYNC_SHIFT 0 184 185 #define PV_VERTB 0x18 186 # define PV_VERTB_VFP_MASK VC4_MASK(31, 16) 187 # define PV_VERTB_VFP_SHIFT 16 188 # define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0) 189 # define PV_VERTB_VACTIVE_SHIFT 0 190 191 #define PV_VERTA_EVEN 0x1c 192 #define PV_VERTB_EVEN 0x20 193 194 #define PV_INTEN 0x24 195 #define PV_INTSTAT 0x28 196 # define PV_INT_VID_IDLE BIT(9) 197 # define PV_INT_VFP_END BIT(8) 198 # define PV_INT_VFP_START BIT(7) 199 # define PV_INT_VACT_START BIT(6) 200 # define PV_INT_VBP_START BIT(5) 201 # define PV_INT_VSYNC_START BIT(4) 202 # define PV_INT_HFP_START BIT(3) 203 # define PV_INT_HACT_START BIT(2) 204 # define PV_INT_HBP_START BIT(1) 205 # define PV_INT_HSYNC_START BIT(0) 206 207 #define PV_STAT 0x2c 208 209 #define PV_HACT_ACT 0x30 210 211 #define SCALER_CHANNELS_COUNT 3 212 213 #define SCALER_DISPCTRL 0x00000000 214 /* Global register for clock gating the HVS */ 215 # define SCALER_DISPCTRL_ENABLE BIT(31) 216 # define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18) 217 # define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18 218 219 /* Enables Display 0 short line and underrun contribution to 220 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are 221 * always enabled. 222 */ 223 # define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x)) 224 /* Enables Display 0 end-of-line-N contribution to 225 * SCALER_DISPSTAT_IRQDISP0 226 */ 227 # define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2)) 228 /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */ 229 # define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2)) 230 231 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) 232 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5) 233 # define SCALER_DISPCTRL_DMAEIRQ BIT(4) 234 /* Enables interrupt generation on the enabled EOF/EOLN/EISLUR 235 * bits and short frames.. 236 */ 237 # define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x)) 238 /* Enables interrupt generation on scaler profiler interrupt. */ 239 # define SCALER_DISPCTRL_SCLEIRQ BIT(0) 240 241 #define SCALER_DISPSTAT 0x00000004 242 # define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14) 243 # define SCALER_DISPSTAT_RESP_SHIFT 14 244 # define SCALER_DISPSTAT_RESP_OKAY 0 245 # define SCALER_DISPSTAT_RESP_EXOKAY 1 246 # define SCALER_DISPSTAT_RESP_SLVERR 2 247 # define SCALER_DISPSTAT_RESP_DECERR 3 248 249 # define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8)) 250 /* Set when the DISPEOLN line is done compositing. */ 251 # define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8)) 252 /* Set when VSTART is seen but there are still pixels in the current 253 * output line. 254 */ 255 # define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8)) 256 /* Set when HSTART is seen but there are still pixels in the current 257 * output line. 258 */ 259 # define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8)) 260 /* Set when the the downstream tries to read from the display FIFO 261 * while it's empty. 262 */ 263 # define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8)) 264 /* Set when the display mode changes from RUN to EOF */ 265 # define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8)) 266 267 # define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \ 268 8 + ((x) * 8)) 269 270 /* Set on AXI invalid DMA ID error. */ 271 # define SCALER_DISPSTAT_DMA_ERROR BIT(7) 272 /* Set on AXI slave read decode error */ 273 # define SCALER_DISPSTAT_IRQSLVRD BIT(6) 274 /* Set on AXI slave write decode error */ 275 # define SCALER_DISPSTAT_IRQSLVWR BIT(5) 276 /* Set when SCALER_DISPSTAT_DMA_ERROR is set, or 277 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY. 278 */ 279 # define SCALER_DISPSTAT_IRQDMA BIT(4) 280 /* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their 281 * corresponding interrupt bit is enabled in DISPCTRL. 282 */ 283 # define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x)) 284 /* On read, the profiler interrupt. On write, clear *all* interrupt bits. */ 285 # define SCALER_DISPSTAT_IRQSCL BIT(0) 286 287 #define SCALER_DISPID 0x00000008 288 #define SCALER_DISPECTRL 0x0000000c 289 #define SCALER_DISPPROF 0x00000010 290 #define SCALER_DISPDITHER 0x00000014 291 #define SCALER_DISPEOLN 0x00000018 292 #define SCALER_DISPLIST0 0x00000020 293 #define SCALER_DISPLIST1 0x00000024 294 #define SCALER_DISPLIST2 0x00000028 295 #define SCALER_DISPLSTAT 0x0000002c 296 #define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \ 297 (x) * (SCALER_DISPLIST1 - \ 298 SCALER_DISPLIST0)) 299 300 #define SCALER_DISPLACT0 0x00000030 301 #define SCALER_DISPLACT1 0x00000034 302 #define SCALER_DISPLACT2 0x00000038 303 #define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \ 304 (x) * (SCALER_DISPLACT1 - \ 305 SCALER_DISPLACT0)) 306 307 #define SCALER_DISPCTRL0 0x00000040 308 # define SCALER_DISPCTRLX_ENABLE BIT(31) 309 # define SCALER_DISPCTRLX_RESET BIT(30) 310 /* Generates a single frame when VSTART is seen and stops at the last 311 * pixel read from the FIFO. 312 */ 313 # define SCALER_DISPCTRLX_ONESHOT BIT(29) 314 /* Processes a single context in the dlist and then task switch, 315 * instead of an entire line. 316 */ 317 # define SCALER_DISPCTRLX_ONECTX BIT(28) 318 /* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */ 319 # define SCALER_DISPCTRLX_FIFO32 BIT(27) 320 /* Turns on output to the DISPSLAVE register instead of the normal 321 * FIFO. 322 */ 323 # define SCALER_DISPCTRLX_FIFOREG BIT(26) 324 325 # define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12) 326 # define SCALER_DISPCTRLX_WIDTH_SHIFT 12 327 # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0) 328 # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0 329 330 #define SCALER_DISPBKGND0 0x00000044 331 # define SCALER_DISPBKGND_AUTOHS BIT(31) 332 # define SCALER_DISPBKGND_INTERLACE BIT(30) 333 # define SCALER_DISPBKGND_GAMMA BIT(29) 334 # define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25) 335 # define SCALER_DISPBKGND_TESTMODE_SHIFT 25 336 /* Enables filling the scaler line with the RGB value in the low 24 337 * bits before compositing. Costs cycles, so should be skipped if 338 * opaque display planes will cover everything. 339 */ 340 # define SCALER_DISPBKGND_FILL BIT(24) 341 342 #define SCALER_DISPSTAT0 0x00000048 343 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30) 344 # define SCALER_DISPSTATX_MODE_SHIFT 30 345 # define SCALER_DISPSTATX_MODE_DISABLED 0 346 # define SCALER_DISPSTATX_MODE_INIT 1 347 # define SCALER_DISPSTATX_MODE_RUN 2 348 # define SCALER_DISPSTATX_MODE_EOF 3 349 # define SCALER_DISPSTATX_FULL BIT(29) 350 # define SCALER_DISPSTATX_EMPTY BIT(28) 351 # define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12) 352 # define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12 353 # define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0) 354 # define SCALER_DISPSTATX_LINE_SHIFT 0 355 356 #define SCALER_DISPBASE0 0x0000004c 357 /* Last pixel in the COB (display FIFO memory) allocated to this HVS 358 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the 359 * next COB base). 360 */ 361 # define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16) 362 # define SCALER_DISPBASEX_TOP_SHIFT 16 363 /* First pixel in the COB (display FIFO memory) allocated to this HVS 364 * channel. Must be 4-pixel aligned. 365 */ 366 # define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0) 367 # define SCALER_DISPBASEX_BASE_SHIFT 0 368 369 #define SCALER_DISPCTRL1 0x00000050 370 #define SCALER_DISPBKGND1 0x00000054 371 #define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \ 372 (x) * (SCALER_DISPBKGND1 - \ 373 SCALER_DISPBKGND0)) 374 #define SCALER_DISPSTAT1 0x00000058 375 #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ 376 (x) * (SCALER_DISPSTAT1 - \ 377 SCALER_DISPSTAT0)) 378 #define SCALER_DISPBASE1 0x0000005c 379 #define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \ 380 (x) * (SCALER_DISPBASE1 - \ 381 SCALER_DISPBASE0)) 382 #define SCALER_DISPCTRL2 0x00000060 383 #define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \ 384 (x) * (SCALER_DISPCTRL1 - \ 385 SCALER_DISPCTRL0)) 386 #define SCALER_DISPBKGND2 0x00000064 387 #define SCALER_DISPSTAT2 0x00000068 388 #define SCALER_DISPBASE2 0x0000006c 389 #define SCALER_DISPALPHA2 0x00000070 390 #define SCALER_GAMADDR 0x00000078 391 # define SCALER_GAMADDR_AUTOINC BIT(31) 392 /* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma 393 * enabled. 394 */ 395 # define SCALER_GAMADDR_SRAMENB BIT(30) 396 397 #define SCALER_OLEDOFFS 0x00000080 398 /* Clamps R to [16,235] and G/B to [16,240]. */ 399 # define SCALER_OLEDOFFS_YUVCLAMP BIT(31) 400 401 /* Chooses which display FIFO the matrix applies to. */ 402 # define SCALER_OLEDOFFS_DISPFIFO_MASK VC4_MASK(25, 24) 403 # define SCALER_OLEDOFFS_DISPFIFO_SHIFT 24 404 # define SCALER_OLEDOFFS_DISPFIFO_DISABLED 0 405 # define SCALER_OLEDOFFS_DISPFIFO_0 1 406 # define SCALER_OLEDOFFS_DISPFIFO_1 2 407 # define SCALER_OLEDOFFS_DISPFIFO_2 3 408 409 /* Offsets are 8-bit 2s-complement. */ 410 # define SCALER_OLEDOFFS_RED_MASK VC4_MASK(23, 16) 411 # define SCALER_OLEDOFFS_RED_SHIFT 16 412 # define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8) 413 # define SCALER_OLEDOFFS_GREEN_SHIFT 8 414 # define SCALER_OLEDOFFS_BLUE_MASK VC4_MASK(7, 0) 415 # define SCALER_OLEDOFFS_BLUE_SHIFT 0 416 417 /* The coefficients are S0.9 fractions. */ 418 #define SCALER_OLEDCOEF0 0x00000084 419 # define SCALER_OLEDCOEF0_B_TO_R_MASK VC4_MASK(29, 20) 420 # define SCALER_OLEDCOEF0_B_TO_R_SHIFT 20 421 # define SCALER_OLEDCOEF0_B_TO_G_MASK VC4_MASK(19, 10) 422 # define SCALER_OLEDCOEF0_B_TO_G_SHIFT 10 423 # define SCALER_OLEDCOEF0_B_TO_B_MASK VC4_MASK(9, 0) 424 # define SCALER_OLEDCOEF0_B_TO_B_SHIFT 0 425 426 #define SCALER_OLEDCOEF1 0x00000088 427 # define SCALER_OLEDCOEF1_G_TO_R_MASK VC4_MASK(29, 20) 428 # define SCALER_OLEDCOEF1_G_TO_R_SHIFT 20 429 # define SCALER_OLEDCOEF1_G_TO_G_MASK VC4_MASK(19, 10) 430 # define SCALER_OLEDCOEF1_G_TO_G_SHIFT 10 431 # define SCALER_OLEDCOEF1_G_TO_B_MASK VC4_MASK(9, 0) 432 # define SCALER_OLEDCOEF1_G_TO_B_SHIFT 0 433 434 #define SCALER_OLEDCOEF2 0x0000008c 435 # define SCALER_OLEDCOEF2_R_TO_R_MASK VC4_MASK(29, 20) 436 # define SCALER_OLEDCOEF2_R_TO_R_SHIFT 20 437 # define SCALER_OLEDCOEF2_R_TO_G_MASK VC4_MASK(19, 10) 438 # define SCALER_OLEDCOEF2_R_TO_G_SHIFT 10 439 # define SCALER_OLEDCOEF2_R_TO_B_MASK VC4_MASK(9, 0) 440 # define SCALER_OLEDCOEF2_R_TO_B_SHIFT 0 441 442 /* Slave addresses for DMAing from HVS composition output to other 443 * devices. The top bits are valid only in !FIFO32 mode. 444 */ 445 #define SCALER_DISPSLAVE0 0x000000c0 446 #define SCALER_DISPSLAVE1 0x000000c9 447 #define SCALER_DISPSLAVE2 0x000000d0 448 # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31) 449 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30) 450 /* Set when the current line has been read and an HSTART is required. */ 451 # define SCALER_DISPSLAVE_EOL BIT(26) 452 /* Set when the display FIFO is empty. */ 453 # define SCALER_DISPSLAVE_EMPTY BIT(25) 454 /* Set when there is RGB data ready to read. */ 455 # define SCALER_DISPSLAVE_VALID BIT(24) 456 # define SCALER_DISPSLAVE_RGB_MASK VC4_MASK(23, 0) 457 # define SCALER_DISPSLAVE_RGB_SHIFT 0 458 459 #define SCALER_GAMDATA 0x000000e0 460 #define SCALER_DLIST_START 0x00002000 461 #define SCALER_DLIST_SIZE 0x00004000 462 463 #define VC4_HDMI_CORE_REV 0x000 464 465 #define VC4_HDMI_SW_RESET_CONTROL 0x004 466 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1) 467 # define VC4_HDMI_SW_RESET_HDMI BIT(0) 468 469 #define VC4_HDMI_HOTPLUG_INT 0x008 470 471 #define VC4_HDMI_HOTPLUG 0x00c 472 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0) 473 474 /* 3 bits per field, where each field maps from that corresponding MAI 475 * bus channel to the given HDMI channel. 476 */ 477 #define VC4_HDMI_MAI_CHANNEL_MAP 0x090 478 479 #define VC4_HDMI_MAI_CONFIG 0x094 480 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27) 481 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26) 482 # define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0) 483 # define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0 484 485 /* Last received format word on the MAI bus. */ 486 #define VC4_HDMI_MAI_FORMAT 0x098 487 488 #define VC4_HDMI_AUDIO_PACKET_CONFIG 0x09c 489 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29) 490 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24) 491 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19) 492 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18) 493 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10) 494 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10 495 /* If set, then multichannel, otherwise 2 channel. */ 496 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9) 497 /* If set, then AUDIO_LAYOUT overrides audio_cea_mask */ 498 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8) 499 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0) 500 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0 501 502 #define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0 503 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16) 504 505 #define VC4_HDMI_RAM_PACKET_STATUS 0x0a4 506 507 #define VC4_HDMI_CRP_CFG 0x0a8 508 /* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead 509 * of pixel clock. 510 */ 511 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26) 512 /* When set, no CRP packets will be sent. */ 513 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25) 514 /* If set, generates CTS values based on N, audio clock, and video 515 * clock. N must be divisible by 128. 516 */ 517 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24) 518 # define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0) 519 # define VC4_HDMI_CRP_CFG_N_SHIFT 0 520 521 /* 20-bit fields containing CTS values to be transmitted if !EXTERNAL_CTS_EN */ 522 #define VC4_HDMI_CTS_0 0x0ac 523 #define VC4_HDMI_CTS_1 0x0b0 524 /* 20-bit fields containing number of clocks to send CTS0/1 before 525 * switching to the other one. 526 */ 527 #define VC4_HDMI_CTS_PERIOD_0 0x0b4 528 #define VC4_HDMI_CTS_PERIOD_1 0x0b8 529 530 #define VC4_HDMI_HORZA 0x0c4 531 # define VC4_HDMI_HORZA_VPOS BIT(14) 532 # define VC4_HDMI_HORZA_HPOS BIT(13) 533 /* Horizontal active pixels (hdisplay). */ 534 # define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0) 535 # define VC4_HDMI_HORZA_HAP_SHIFT 0 536 537 #define VC4_HDMI_HORZB 0x0c8 538 /* Horizontal pack porch (htotal - hsync_end). */ 539 # define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20) 540 # define VC4_HDMI_HORZB_HBP_SHIFT 20 541 /* Horizontal sync pulse (hsync_end - hsync_start). */ 542 # define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10) 543 # define VC4_HDMI_HORZB_HSP_SHIFT 10 544 /* Horizontal front porch (hsync_start - hdisplay). */ 545 # define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0) 546 # define VC4_HDMI_HORZB_HFP_SHIFT 0 547 548 #define VC4_HDMI_FIFO_CTL 0x05c 549 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14) 550 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13) 551 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7) 552 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6) 553 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5) 554 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4) 555 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3) 556 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2) 557 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1) 558 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0) 559 # define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff 560 561 #define VC4_HDMI_SCHEDULER_CONTROL 0x0c0 562 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15) 563 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5) 564 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3) 565 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1) 566 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0) 567 568 #define VC4_HDMI_VERTA0 0x0cc 569 #define VC4_HDMI_VERTA1 0x0d4 570 /* Vertical sync pulse (vsync_end - vsync_start). */ 571 # define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20) 572 # define VC4_HDMI_VERTA_VSP_SHIFT 20 573 /* Vertical front porch (vsync_start - vdisplay). */ 574 # define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13) 575 # define VC4_HDMI_VERTA_VFP_SHIFT 13 576 /* Vertical active lines (vdisplay). */ 577 # define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 578 # define VC4_HDMI_VERTA_VAL_SHIFT 0 579 580 #define VC4_HDMI_VERTB0 0x0d0 581 #define VC4_HDMI_VERTB1 0x0d8 582 /* Vertical sync pulse offset (for interlaced) */ 583 # define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9) 584 # define VC4_HDMI_VERTB_VSPO_SHIFT 9 585 /* Vertical pack porch (vtotal - vsync_end). */ 586 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0) 587 # define VC4_HDMI_VERTB_VBP_SHIFT 0 588 589 #define VC4_HDMI_CEC_CNTRL_1 0x0e8 590 /* Set when the transmission has ended. */ 591 # define VC4_HDMI_CEC_TX_EOM BIT(31) 592 /* If set, transmission was acked on the 1st or 2nd attempt (only one 593 * retry is attempted). If in continuous mode, this means TX needs to 594 * be filled if !TX_EOM. 595 */ 596 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30) 597 # define VC4_HDMI_CEC_RX_EOM BIT(29) 598 # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28) 599 /* Number of bytes received for the message. */ 600 # define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24) 601 # define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24 602 /* Sets continuous receive mode. Generates interrupt after each 8 603 * bytes to signal that RX_DATA should be consumed, and at RX_EOM. 604 * 605 * If disabled, maximum 16 bytes will be received (including header), 606 * and interrupt at RX_EOM. Later bytes will be acked but not put 607 * into the RX_DATA. 608 */ 609 # define VC4_HDMI_CEC_RX_CONTINUE BIT(23) 610 # define VC4_HDMI_CEC_TX_CONTINUE BIT(22) 611 /* Set this after a CEC interrupt. */ 612 # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21) 613 /* Starts a TX. Will wait for appropriate idel time before CEC 614 * activity. Must be cleared in between transmits. 615 */ 616 # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20) 617 # define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16) 618 # define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16 619 /* Device's CEC address */ 620 # define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12) 621 # define VC4_HDMI_CEC_ADDR_SHIFT 12 622 /* Divides off of HSM clock to generate CEC bit clock. */ 623 /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */ 624 # define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0) 625 # define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0 626 627 /* Set these fields to how many bit clock cycles get to that many 628 * microseconds. 629 */ 630 #define VC4_HDMI_CEC_CNTRL_2 0x0ec 631 # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24) 632 # define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24 633 # define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17) 634 # define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17 635 # define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11) 636 # define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11 637 # define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5) 638 # define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5 639 # define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0) 640 # define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0 641 642 #define VC4_HDMI_CEC_CNTRL_3 0x0f0 643 # define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24) 644 # define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24 645 # define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16) 646 # define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16 647 # define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8) 648 # define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8 649 # define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0) 650 # define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0 651 652 #define VC4_HDMI_CEC_CNTRL_4 0x0f4 653 # define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24) 654 # define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24 655 # define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16) 656 # define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16 657 # define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8) 658 # define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8 659 # define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0) 660 # define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0 661 662 #define VC4_HDMI_CEC_CNTRL_5 0x0f8 663 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27) 664 # define VC4_HDMI_CEC_RX_SW_RESET BIT(26) 665 # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25) 666 # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24) 667 # define VC4_HDMI_CEC_RX_CEC_INT BIT(23) 668 # define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16) 669 # define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16 670 # define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8) 671 # define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8 672 # define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0) 673 # define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0 674 675 /* Transmit data, first byte is low byte of the 32-bit reg. MSB of 676 * each byte transmitted first. 677 */ 678 #define VC4_HDMI_CEC_TX_DATA_1 0x0fc 679 #define VC4_HDMI_CEC_TX_DATA_2 0x100 680 #define VC4_HDMI_CEC_TX_DATA_3 0x104 681 #define VC4_HDMI_CEC_TX_DATA_4 0x108 682 #define VC4_HDMI_CEC_RX_DATA_1 0x10c 683 #define VC4_HDMI_CEC_RX_DATA_2 0x110 684 #define VC4_HDMI_CEC_RX_DATA_3 0x114 685 #define VC4_HDMI_CEC_RX_DATA_4 0x118 686 687 #define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0 688 689 #define VC4_HDMI_TX_PHY_CTL0 0x2c4 690 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25) 691 692 /* Interrupt status bits */ 693 #define VC4_HDMI_CPU_STATUS 0x340 694 #define VC4_HDMI_CPU_SET 0x344 695 #define VC4_HDMI_CPU_CLEAR 0x348 696 # define VC4_HDMI_CPU_CEC BIT(6) 697 # define VC4_HDMI_CPU_HOTPLUG BIT(0) 698 699 #define VC4_HDMI_CPU_MASK_STATUS 0x34c 700 #define VC4_HDMI_CPU_MASK_SET 0x350 701 #define VC4_HDMI_CPU_MASK_CLEAR 0x354 702 703 #define VC4_HDMI_GCP(x) (0x400 + ((x) * 0x4)) 704 #define VC4_HDMI_RAM_PACKET(x) (0x400 + ((x) * 0x24)) 705 #define VC4_HDMI_PACKET_STRIDE 0x24 706 707 #define VC4_HD_M_CTL 0x00c 708 /* Debug: Current receive value on the CEC pad. */ 709 # define VC4_HD_CECRXD BIT(9) 710 /* Debug: Override CEC output to 0. */ 711 # define VC4_HD_CECOVR BIT(8) 712 # define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6) 713 # define VC4_HD_M_RAM_STANDBY (3 << 4) 714 # define VC4_HD_M_SW_RST BIT(2) 715 # define VC4_HD_M_ENABLE BIT(0) 716 717 #define VC4_HD_MAI_CTL 0x014 718 /* Set when audio stream is received at a slower rate than the 719 * sampling period, so MAI fifo goes empty. Write 1 to clear. 720 */ 721 # define VC4_HD_MAI_CTL_DLATE BIT(15) 722 # define VC4_HD_MAI_CTL_BUSY BIT(14) 723 # define VC4_HD_MAI_CTL_CHALIGN BIT(13) 724 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12) 725 # define VC4_HD_MAI_CTL_FULL BIT(11) 726 # define VC4_HD_MAI_CTL_EMPTY BIT(10) 727 # define VC4_HD_MAI_CTL_FLUSH BIT(9) 728 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing 729 * through. 730 */ 731 # define VC4_HD_MAI_CTL_PAREN BIT(8) 732 # define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4) 733 # define VC4_HD_MAI_CTL_CHNUM_SHIFT 4 734 # define VC4_HD_MAI_CTL_ENABLE BIT(3) 735 /* Underflow error status bit, write 1 to clear. */ 736 # define VC4_HD_MAI_CTL_ERRORE BIT(2) 737 /* Overflow error status bit, write 1 to clear. */ 738 # define VC4_HD_MAI_CTL_ERRORF BIT(1) 739 /* Single-shot reset bit. Read value is undefined. */ 740 # define VC4_HD_MAI_CTL_RESET BIT(0) 741 742 #define VC4_HD_MAI_THR 0x018 743 # define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24) 744 # define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24 745 # define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16) 746 # define VC4_HD_MAI_THR_PANICLOW_SHIFT 16 747 # define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8) 748 # define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8 749 # define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0) 750 # define VC4_HD_MAI_THR_DREQLOW_SHIFT 0 751 752 /* Format header to be placed on the MAI data. Unused. */ 753 #define VC4_HD_MAI_FMT 0x01c 754 755 /* Register for DMAing in audio data to be transported over the MAI 756 * bus to the Falcon core. 757 */ 758 #define VC4_HD_MAI_DATA 0x020 759 760 /* Divider from HDMI HSM clock to MAI serial clock. Sampling period 761 * converges to N / (M + 1) cycles. 762 */ 763 #define VC4_HD_MAI_SMP 0x02c 764 # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8) 765 # define VC4_HD_MAI_SMP_N_SHIFT 8 766 # define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0) 767 # define VC4_HD_MAI_SMP_M_SHIFT 0 768 769 #define VC4_HD_VID_CTL 0x038 770 # define VC4_HD_VID_CTL_ENABLE BIT(31) 771 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30) 772 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29) 773 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28) 774 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27) 775 776 #define VC4_HD_CSC_CTL 0x040 777 # define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5) 778 # define VC4_HD_CSC_CTL_ORDER_SHIFT 5 779 # define VC4_HD_CSC_CTL_ORDER_RGB 0 780 # define VC4_HD_CSC_CTL_ORDER_BGR 1 781 # define VC4_HD_CSC_CTL_ORDER_BRG 2 782 # define VC4_HD_CSC_CTL_ORDER_GRB 3 783 # define VC4_HD_CSC_CTL_ORDER_GBR 4 784 # define VC4_HD_CSC_CTL_ORDER_RBG 5 785 # define VC4_HD_CSC_CTL_PADMSB BIT(4) 786 # define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2) 787 # define VC4_HD_CSC_CTL_MODE_SHIFT 2 788 # define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0 789 # define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1 790 # define VC4_HD_CSC_CTL_MODE_CUSTOM 3 791 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1) 792 # define VC4_HD_CSC_CTL_ENABLE BIT(0) 793 794 #define VC4_HD_CSC_12_11 0x044 795 #define VC4_HD_CSC_14_13 0x048 796 #define VC4_HD_CSC_22_21 0x04c 797 #define VC4_HD_CSC_24_23 0x050 798 #define VC4_HD_CSC_32_31 0x054 799 #define VC4_HD_CSC_34_33 0x058 800 801 #define VC4_HD_FRAME_COUNT 0x068 802 803 /* HVS display list information. */ 804 #define HVS_BOOTLOADER_DLIST_END 32 805 806 enum hvs_pixel_format { 807 /* 8bpp */ 808 HVS_PIXEL_FORMAT_RGB332 = 0, 809 /* 16bpp */ 810 HVS_PIXEL_FORMAT_RGBA4444 = 1, 811 HVS_PIXEL_FORMAT_RGB555 = 2, 812 HVS_PIXEL_FORMAT_RGBA5551 = 3, 813 HVS_PIXEL_FORMAT_RGB565 = 4, 814 /* 24bpp */ 815 HVS_PIXEL_FORMAT_RGB888 = 5, 816 HVS_PIXEL_FORMAT_RGBA6666 = 6, 817 /* 32bpp */ 818 HVS_PIXEL_FORMAT_RGBA8888 = 7, 819 820 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8, 821 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9, 822 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10, 823 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11, 824 HVS_PIXEL_FORMAT_H264 = 12, 825 HVS_PIXEL_FORMAT_PALETTE = 13, 826 HVS_PIXEL_FORMAT_YUV444_RGB = 14, 827 HVS_PIXEL_FORMAT_AYUV444_RGB = 15, 828 }; 829 830 /* Note: the LSB is the rightmost character shown. Only valid for 831 * HVS_PIXEL_FORMAT_RGB8888, not RGB888. 832 */ 833 #define HVS_PIXEL_ORDER_RGBA 0 834 #define HVS_PIXEL_ORDER_BGRA 1 835 #define HVS_PIXEL_ORDER_ARGB 2 836 #define HVS_PIXEL_ORDER_ABGR 3 837 838 #define HVS_PIXEL_ORDER_XBRG 0 839 #define HVS_PIXEL_ORDER_XRBG 1 840 #define HVS_PIXEL_ORDER_XRGB 2 841 #define HVS_PIXEL_ORDER_XBGR 3 842 843 #define HVS_PIXEL_ORDER_XYCBCR 0 844 #define HVS_PIXEL_ORDER_XYCRCB 1 845 #define HVS_PIXEL_ORDER_YXCBCR 2 846 #define HVS_PIXEL_ORDER_YXCRCB 3 847 848 #define SCALER_CTL0_END BIT(31) 849 #define SCALER_CTL0_VALID BIT(30) 850 851 #define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24) 852 #define SCALER_CTL0_SIZE_SHIFT 24 853 854 #define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20) 855 #define SCALER_CTL0_TILING_SHIFT 20 856 #define SCALER_CTL0_TILING_LINEAR 0 857 #define SCALER_CTL0_TILING_64B 1 858 #define SCALER_CTL0_TILING_128B 2 859 #define SCALER_CTL0_TILING_256B_OR_T 3 860 861 #define SCALER_CTL0_ALPHA_MASK BIT(19) 862 #define SCALER_CTL0_HFLIP BIT(16) 863 #define SCALER_CTL0_VFLIP BIT(15) 864 865 #define SCALER_CTL0_KEY_MODE_MASK VC4_MASK(18, 17) 866 #define SCALER_CTL0_KEY_MODE_SHIFT 17 867 #define SCALER_CTL0_KEY_DISABLED 0 868 #define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB 1 869 #define SCALER_CTL0_KEY_MATCH 2 /* turn transparent */ 870 #define SCALER_CTL0_KEY_REPLACE 3 /* replace with value from key mask word 2 */ 871 872 #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13) 873 #define SCALER_CTL0_ORDER_SHIFT 13 874 875 #define SCALER_CTL0_RGBA_EXPAND_MASK VC4_MASK(12, 11) 876 #define SCALER_CTL0_RGBA_EXPAND_SHIFT 11 877 #define SCALER_CTL0_RGBA_EXPAND_ZERO 0 878 #define SCALER_CTL0_RGBA_EXPAND_LSB 1 879 #define SCALER_CTL0_RGBA_EXPAND_MSB 2 880 #define SCALER_CTL0_RGBA_EXPAND_ROUND 3 881 882 #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8) 883 #define SCALER_CTL0_SCL1_SHIFT 8 884 885 #define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5) 886 #define SCALER_CTL0_SCL0_SHIFT 5 887 888 #define SCALER_CTL0_SCL_H_PPF_V_PPF 0 889 #define SCALER_CTL0_SCL_H_TPZ_V_PPF 1 890 #define SCALER_CTL0_SCL_H_PPF_V_TPZ 2 891 #define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3 892 #define SCALER_CTL0_SCL_H_PPF_V_NONE 4 893 #define SCALER_CTL0_SCL_H_NONE_V_PPF 5 894 #define SCALER_CTL0_SCL_H_NONE_V_TPZ 6 895 #define SCALER_CTL0_SCL_H_TPZ_V_NONE 7 896 897 /* Set to indicate no scaling. */ 898 #define SCALER_CTL0_UNITY BIT(4) 899 900 #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0) 901 #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0 902 903 #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24) 904 #define SCALER_POS0_FIXED_ALPHA_SHIFT 24 905 906 #define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12) 907 #define SCALER_POS0_START_Y_SHIFT 12 908 909 #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0) 910 #define SCALER_POS0_START_X_SHIFT 0 911 912 #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16) 913 #define SCALER_POS1_SCL_HEIGHT_SHIFT 16 914 915 #define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0) 916 #define SCALER_POS1_SCL_WIDTH_SHIFT 0 917 918 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30) 919 #define SCALER_POS2_ALPHA_MODE_SHIFT 30 920 #define SCALER_POS2_ALPHA_MODE_PIPELINE 0 921 #define SCALER_POS2_ALPHA_MODE_FIXED 1 922 #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2 923 #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3 924 #define SCALER_POS2_ALPHA_PREMULT BIT(29) 925 #define SCALER_POS2_ALPHA_MIX BIT(28) 926 927 #define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16) 928 #define SCALER_POS2_HEIGHT_SHIFT 16 929 930 #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0) 931 #define SCALER_POS2_WIDTH_SHIFT 0 932 933 /* Color Space Conversion words. Some values are S2.8 signed 934 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1, 935 * 0x2: 2, 0x3: -1} 936 */ 937 /* bottom 8 bits of S2.8 contribution of Cr to Blue */ 938 #define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24) 939 #define SCALER_CSC0_COEF_CR_BLU_SHIFT 24 940 /* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */ 941 #define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16) 942 #define SCALER_CSC0_COEF_YY_OFS_SHIFT 16 943 /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */ 944 #define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8) 945 #define SCALER_CSC0_COEF_CB_OFS_SHIFT 8 946 /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */ 947 #define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0) 948 #define SCALER_CSC0_COEF_CR_OFS_SHIFT 0 949 #define SCALER_CSC0_ITR_R_601_5 0x00f00000 950 #define SCALER_CSC0_ITR_R_709_3 0x00f00000 951 #define SCALER_CSC0_JPEG_JFIF 0x00000000 952 953 /* S2.8 contribution of Cb to Green */ 954 #define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22) 955 #define SCALER_CSC1_COEF_CB_GRN_SHIFT 22 956 /* S2.8 contribution of Cr to Green */ 957 #define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12) 958 #define SCALER_CSC1_COEF_CR_GRN_SHIFT 12 959 /* S2.8 contribution of Y to all of RGB */ 960 #define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2) 961 #define SCALER_CSC1_COEF_YY_ALL_SHIFT 2 962 /* top 2 bits of S2.8 contribution of Cr to Blue */ 963 #define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0) 964 #define SCALER_CSC1_COEF_CR_BLU_SHIFT 0 965 #define SCALER_CSC1_ITR_R_601_5 0xe73304a8 966 #define SCALER_CSC1_ITR_R_709_3 0xf2b784a8 967 #define SCALER_CSC1_JPEG_JFIF 0xea34a400 968 969 /* S2.8 contribution of Cb to Red */ 970 #define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20) 971 #define SCALER_CSC2_COEF_CB_RED_SHIFT 20 972 /* S2.8 contribution of Cr to Red */ 973 #define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10) 974 #define SCALER_CSC2_COEF_CR_RED_SHIFT 10 975 /* S2.8 contribution of Cb to Blue */ 976 #define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10) 977 #define SCALER_CSC2_COEF_CB_BLU_SHIFT 10 978 #define SCALER_CSC2_ITR_R_601_5 0x00066204 979 #define SCALER_CSC2_ITR_R_709_3 0x00072a1c 980 #define SCALER_CSC2_JPEG_JFIF 0x000599c5 981 982 #define SCALER_TPZ0_VERT_RECALC BIT(31) 983 #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8) 984 #define SCALER_TPZ0_SCALE_SHIFT 8 985 #define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0) 986 #define SCALER_TPZ0_IPHASE_SHIFT 0 987 #define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0) 988 #define SCALER_TPZ1_RECIP_SHIFT 0 989 990 /* Skips interpolating coefficients to 64 phases, so just 8 are used. 991 * Required for nearest neighbor. 992 */ 993 #define SCALER_PPF_NOINTERP BIT(31) 994 /* Replaes the highest valued coefficient with one that makes all 4 995 * sum to unity. 996 */ 997 #define SCALER_PPF_AGC BIT(30) 998 #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8) 999 #define SCALER_PPF_SCALE_SHIFT 8 1000 #define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0) 1001 #define SCALER_PPF_IPHASE_SHIFT 0 1002 1003 #define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0) 1004 #define SCALER_PPF_KERNEL_OFFSET_SHIFT 0 1005 #define SCALER_PPF_KERNEL_UNCACHED BIT(31) 1006 1007 /* PITCH0/1/2 fields for raster. */ 1008 #define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0) 1009 #define SCALER_SRC_PITCH_SHIFT 0 1010 1011 /* PITCH0/1/2 fields for tiled (SAND). */ 1012 #define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16) 1013 #define SCALER_TILE_SKIP_0_SHIFT 16 1014 #define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0) 1015 #define SCALER_TILE_HEIGHT_SHIFT 0 1016 1017 /* Common PITCH0 fields */ 1018 #define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26) 1019 #define SCALER_PITCH0_SINK_PIX_SHIFT 26 1020 1021 /* PITCH0 fields for T-tiled. */ 1022 #define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16) 1023 #define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16 1024 #define SCALER_PITCH0_TILE_LINE_DIR BIT(15) 1025 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14) 1026 /* Y offset within a tile. */ 1027 #define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8) 1028 #define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8 1029 #define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0) 1030 #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0 1031 1032 #endif /* VC4_REGS_H */ 1033