1 /* 2 * Copyright © 2014-2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef VC4_REGS_H 10 #define VC4_REGS_H 11 12 #include <linux/bitops.h> 13 14 #define VC4_MASK(high, low) ((u32)GENMASK(high, low)) 15 /* Using the GNU statement expression extension */ 16 #define VC4_SET_FIELD(value, field) \ 17 ({ \ 18 uint32_t fieldval = (value) << field##_SHIFT; \ 19 WARN_ON((fieldval & ~field##_MASK) != 0); \ 20 fieldval & field##_MASK; \ 21 }) 22 23 #define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >> \ 24 field##_SHIFT) 25 26 #define V3D_IDENT0 0x00000 27 # define V3D_EXPECTED_IDENT0 \ 28 ((2 << 24) | \ 29 ('V' << 0) | \ 30 ('3' << 8) | \ 31 ('D' << 16)) 32 33 #define V3D_IDENT1 0x00004 34 /* Multiples of 1kb */ 35 # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28) 36 # define V3D_IDENT1_VPM_SIZE_SHIFT 28 37 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16) 38 # define V3D_IDENT1_NSEM_SHIFT 16 39 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12) 40 # define V3D_IDENT1_TUPS_SHIFT 12 41 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8) 42 # define V3D_IDENT1_QUPS_SHIFT 8 43 # define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4) 44 # define V3D_IDENT1_NSLC_SHIFT 4 45 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0) 46 # define V3D_IDENT1_REV_SHIFT 0 47 48 #define V3D_IDENT2 0x00008 49 #define V3D_SCRATCH 0x00010 50 #define V3D_L2CACTL 0x00020 51 # define V3D_L2CACTL_L2CCLR BIT(2) 52 # define V3D_L2CACTL_L2CDIS BIT(1) 53 # define V3D_L2CACTL_L2CENA BIT(0) 54 55 #define V3D_SLCACTL 0x00024 56 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24) 57 # define V3D_SLCACTL_T1CC_SHIFT 24 58 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16) 59 # define V3D_SLCACTL_T0CC_SHIFT 16 60 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8) 61 # define V3D_SLCACTL_UCC_SHIFT 8 62 # define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0) 63 # define V3D_SLCACTL_ICC_SHIFT 0 64 65 #define V3D_INTCTL 0x00030 66 #define V3D_INTENA 0x00034 67 #define V3D_INTDIS 0x00038 68 # define V3D_INT_SPILLUSE BIT(3) 69 # define V3D_INT_OUTOMEM BIT(2) 70 # define V3D_INT_FLDONE BIT(1) 71 # define V3D_INT_FRDONE BIT(0) 72 73 #define V3D_CT0CS 0x00100 74 #define V3D_CT1CS 0x00104 75 #define V3D_CTNCS(n) (V3D_CT0CS + 4 * n) 76 # define V3D_CTRSTA BIT(15) 77 # define V3D_CTSEMA BIT(12) 78 # define V3D_CTRTSD BIT(8) 79 # define V3D_CTRUN BIT(5) 80 # define V3D_CTSUBS BIT(4) 81 # define V3D_CTERR BIT(3) 82 # define V3D_CTMODE BIT(0) 83 84 #define V3D_CT0EA 0x00108 85 #define V3D_CT1EA 0x0010c 86 #define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n)) 87 #define V3D_CT0CA 0x00110 88 #define V3D_CT1CA 0x00114 89 #define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n)) 90 #define V3D_CT00RA0 0x00118 91 #define V3D_CT01RA0 0x0011c 92 #define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n)) 93 #define V3D_CT0LC 0x00120 94 #define V3D_CT1LC 0x00124 95 #define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n)) 96 #define V3D_CT0PC 0x00128 97 #define V3D_CT1PC 0x0012c 98 #define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n)) 99 100 #define V3D_PCS 0x00130 101 # define V3D_BMOOM BIT(8) 102 # define V3D_RMBUSY BIT(3) 103 # define V3D_RMACTIVE BIT(2) 104 # define V3D_BMBUSY BIT(1) 105 # define V3D_BMACTIVE BIT(0) 106 107 #define V3D_BFC 0x00134 108 #define V3D_RFC 0x00138 109 #define V3D_BPCA 0x00300 110 #define V3D_BPCS 0x00304 111 #define V3D_BPOA 0x00308 112 #define V3D_BPOS 0x0030c 113 #define V3D_BXCF 0x00310 114 #define V3D_SQRSV0 0x00410 115 #define V3D_SQRSV1 0x00414 116 #define V3D_SQCNTL 0x00418 117 #define V3D_SRQPC 0x00430 118 #define V3D_SRQUA 0x00434 119 #define V3D_SRQUL 0x00438 120 #define V3D_SRQCS 0x0043c 121 #define V3D_VPACNTL 0x00500 122 #define V3D_VPMBASE 0x00504 123 #define V3D_PCTRC 0x00670 124 #define V3D_PCTRE 0x00674 125 #define V3D_PCTR0 0x00680 126 #define V3D_PCTRS0 0x00684 127 #define V3D_PCTR1 0x00688 128 #define V3D_PCTRS1 0x0068c 129 #define V3D_PCTR2 0x00690 130 #define V3D_PCTRS2 0x00694 131 #define V3D_PCTR3 0x00698 132 #define V3D_PCTRS3 0x0069c 133 #define V3D_PCTR4 0x006a0 134 #define V3D_PCTRS4 0x006a4 135 #define V3D_PCTR5 0x006a8 136 #define V3D_PCTRS5 0x006ac 137 #define V3D_PCTR6 0x006b0 138 #define V3D_PCTRS6 0x006b4 139 #define V3D_PCTR7 0x006b8 140 #define V3D_PCTRS7 0x006bc 141 #define V3D_PCTR8 0x006c0 142 #define V3D_PCTRS8 0x006c4 143 #define V3D_PCTR9 0x006c8 144 #define V3D_PCTRS9 0x006cc 145 #define V3D_PCTR10 0x006d0 146 #define V3D_PCTRS10 0x006d4 147 #define V3D_PCTR11 0x006d8 148 #define V3D_PCTRS11 0x006dc 149 #define V3D_PCTR12 0x006e0 150 #define V3D_PCTRS12 0x006e4 151 #define V3D_PCTR13 0x006e8 152 #define V3D_PCTRS13 0x006ec 153 #define V3D_PCTR14 0x006f0 154 #define V3D_PCTRS14 0x006f4 155 #define V3D_PCTR15 0x006f8 156 #define V3D_PCTRS15 0x006fc 157 #define V3D_DBGE 0x00f00 158 #define V3D_FDBGO 0x00f04 159 #define V3D_FDBGB 0x00f08 160 #define V3D_FDBGR 0x00f0c 161 #define V3D_FDBGS 0x00f10 162 #define V3D_ERRSTAT 0x00f20 163 164 #define PV_CONTROL 0x00 165 # define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21) 166 # define PV_CONTROL_FORMAT_SHIFT 21 167 # define PV_CONTROL_FORMAT_24 0 168 # define PV_CONTROL_FORMAT_DSIV_16 1 169 # define PV_CONTROL_FORMAT_DSIC_16 2 170 # define PV_CONTROL_FORMAT_DSIV_18 3 171 # define PV_CONTROL_FORMAT_DSIV_24 4 172 173 # define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15) 174 # define PV_CONTROL_FIFO_LEVEL_SHIFT 15 175 # define PV_CONTROL_CLR_AT_START BIT(14) 176 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13) 177 # define PV_CONTROL_WAIT_HSTART BIT(12) 178 # define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4) 179 # define PV_CONTROL_PIXEL_REP_SHIFT 4 180 # define PV_CONTROL_CLK_SELECT_DSI 0 181 # define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1 182 # define PV_CONTROL_CLK_SELECT_VEC 2 183 # define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2) 184 # define PV_CONTROL_CLK_SELECT_SHIFT 2 185 # define PV_CONTROL_FIFO_CLR BIT(1) 186 # define PV_CONTROL_EN BIT(0) 187 188 #define PV_V_CONTROL 0x04 189 # define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6) 190 # define PV_VCONTROL_ODD_DELAY_SHIFT 6 191 # define PV_VCONTROL_ODD_FIRST BIT(5) 192 # define PV_VCONTROL_INTERLACE BIT(4) 193 # define PV_VCONTROL_DSI BIT(3) 194 # define PV_VCONTROL_COMMAND BIT(2) 195 # define PV_VCONTROL_CONTINUOUS BIT(1) 196 # define PV_VCONTROL_VIDEN BIT(0) 197 198 #define PV_VSYNCD_EVEN 0x08 199 200 #define PV_HORZA 0x0c 201 # define PV_HORZA_HBP_MASK VC4_MASK(31, 16) 202 # define PV_HORZA_HBP_SHIFT 16 203 # define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0) 204 # define PV_HORZA_HSYNC_SHIFT 0 205 206 #define PV_HORZB 0x10 207 # define PV_HORZB_HFP_MASK VC4_MASK(31, 16) 208 # define PV_HORZB_HFP_SHIFT 16 209 # define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0) 210 # define PV_HORZB_HACTIVE_SHIFT 0 211 212 #define PV_VERTA 0x14 213 # define PV_VERTA_VBP_MASK VC4_MASK(31, 16) 214 # define PV_VERTA_VBP_SHIFT 16 215 # define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0) 216 # define PV_VERTA_VSYNC_SHIFT 0 217 218 #define PV_VERTB 0x18 219 # define PV_VERTB_VFP_MASK VC4_MASK(31, 16) 220 # define PV_VERTB_VFP_SHIFT 16 221 # define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0) 222 # define PV_VERTB_VACTIVE_SHIFT 0 223 224 #define PV_VERTA_EVEN 0x1c 225 #define PV_VERTB_EVEN 0x20 226 227 #define PV_INTEN 0x24 228 #define PV_INTSTAT 0x28 229 # define PV_INT_VID_IDLE BIT(9) 230 # define PV_INT_VFP_END BIT(8) 231 # define PV_INT_VFP_START BIT(7) 232 # define PV_INT_VACT_START BIT(6) 233 # define PV_INT_VBP_START BIT(5) 234 # define PV_INT_VSYNC_START BIT(4) 235 # define PV_INT_HFP_START BIT(3) 236 # define PV_INT_HACT_START BIT(2) 237 # define PV_INT_HBP_START BIT(1) 238 # define PV_INT_HSYNC_START BIT(0) 239 240 #define PV_STAT 0x2c 241 242 #define PV_HACT_ACT 0x30 243 244 #define SCALER_DISPCTRL 0x00000000 245 /* Global register for clock gating the HVS */ 246 # define SCALER_DISPCTRL_ENABLE BIT(31) 247 # define SCALER_DISPCTRL_DSP2EISLUR BIT(15) 248 # define SCALER_DISPCTRL_DSP1EISLUR BIT(14) 249 # define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18) 250 # define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18 251 252 /* Enables Display 0 short line and underrun contribution to 253 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are 254 * always enabled. 255 */ 256 # define SCALER_DISPCTRL_DSP0EISLUR BIT(13) 257 # define SCALER_DISPCTRL_DSP2EIEOLN BIT(12) 258 # define SCALER_DISPCTRL_DSP2EIEOF BIT(11) 259 # define SCALER_DISPCTRL_DSP1EIEOLN BIT(10) 260 # define SCALER_DISPCTRL_DSP1EIEOF BIT(9) 261 /* Enables Display 0 end-of-line-N contribution to 262 * SCALER_DISPSTAT_IRQDISP0 263 */ 264 # define SCALER_DISPCTRL_DSP0EIEOLN BIT(8) 265 /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */ 266 # define SCALER_DISPCTRL_DSP0EIEOF BIT(7) 267 268 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) 269 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5) 270 # define SCALER_DISPCTRL_DMAEIRQ BIT(4) 271 # define SCALER_DISPCTRL_DISP2EIRQ BIT(3) 272 # define SCALER_DISPCTRL_DISP1EIRQ BIT(2) 273 /* Enables interrupt generation on the enabled EOF/EOLN/EISLUR 274 * bits and short frames.. 275 */ 276 # define SCALER_DISPCTRL_DISP0EIRQ BIT(1) 277 /* Enables interrupt generation on scaler profiler interrupt. */ 278 # define SCALER_DISPCTRL_SCLEIRQ BIT(0) 279 280 #define SCALER_DISPSTAT 0x00000004 281 # define SCALER_DISPSTAT_COBLOW2 BIT(29) 282 # define SCALER_DISPSTAT_EOLN2 BIT(28) 283 # define SCALER_DISPSTAT_ESFRAME2 BIT(27) 284 # define SCALER_DISPSTAT_ESLINE2 BIT(26) 285 # define SCALER_DISPSTAT_EUFLOW2 BIT(25) 286 # define SCALER_DISPSTAT_EOF2 BIT(24) 287 288 # define SCALER_DISPSTAT_COBLOW1 BIT(21) 289 # define SCALER_DISPSTAT_EOLN1 BIT(20) 290 # define SCALER_DISPSTAT_ESFRAME1 BIT(19) 291 # define SCALER_DISPSTAT_ESLINE1 BIT(18) 292 # define SCALER_DISPSTAT_EUFLOW1 BIT(17) 293 # define SCALER_DISPSTAT_EOF1 BIT(16) 294 295 # define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14) 296 # define SCALER_DISPSTAT_RESP_SHIFT 14 297 # define SCALER_DISPSTAT_RESP_OKAY 0 298 # define SCALER_DISPSTAT_RESP_EXOKAY 1 299 # define SCALER_DISPSTAT_RESP_SLVERR 2 300 # define SCALER_DISPSTAT_RESP_DECERR 3 301 302 # define SCALER_DISPSTAT_COBLOW0 BIT(13) 303 /* Set when the DISPEOLN line is done compositing. */ 304 # define SCALER_DISPSTAT_EOLN0 BIT(12) 305 /* Set when VSTART is seen but there are still pixels in the current 306 * output line. 307 */ 308 # define SCALER_DISPSTAT_ESFRAME0 BIT(11) 309 /* Set when HSTART is seen but there are still pixels in the current 310 * output line. 311 */ 312 # define SCALER_DISPSTAT_ESLINE0 BIT(10) 313 /* Set when the the downstream tries to read from the display FIFO 314 * while it's empty. 315 */ 316 # define SCALER_DISPSTAT_EUFLOW0 BIT(9) 317 /* Set when the display mode changes from RUN to EOF */ 318 # define SCALER_DISPSTAT_EOF0 BIT(8) 319 320 /* Set on AXI invalid DMA ID error. */ 321 # define SCALER_DISPSTAT_DMA_ERROR BIT(7) 322 /* Set on AXI slave read decode error */ 323 # define SCALER_DISPSTAT_IRQSLVRD BIT(6) 324 /* Set on AXI slave write decode error */ 325 # define SCALER_DISPSTAT_IRQSLVWR BIT(5) 326 /* Set when SCALER_DISPSTAT_DMA_ERROR is set, or 327 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY. 328 */ 329 # define SCALER_DISPSTAT_IRQDMA BIT(4) 330 # define SCALER_DISPSTAT_IRQDISP2 BIT(3) 331 # define SCALER_DISPSTAT_IRQDISP1 BIT(2) 332 /* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their 333 * corresponding interrupt bit is enabled in DISPCTRL. 334 */ 335 # define SCALER_DISPSTAT_IRQDISP0 BIT(1) 336 /* On read, the profiler interrupt. On write, clear *all* interrupt bits. */ 337 # define SCALER_DISPSTAT_IRQSCL BIT(0) 338 339 #define SCALER_DISPID 0x00000008 340 #define SCALER_DISPECTRL 0x0000000c 341 #define SCALER_DISPPROF 0x00000010 342 #define SCALER_DISPDITHER 0x00000014 343 #define SCALER_DISPEOLN 0x00000018 344 #define SCALER_DISPLIST0 0x00000020 345 #define SCALER_DISPLIST1 0x00000024 346 #define SCALER_DISPLIST2 0x00000028 347 #define SCALER_DISPLSTAT 0x0000002c 348 #define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \ 349 (x) * (SCALER_DISPLIST1 - \ 350 SCALER_DISPLIST0)) 351 352 #define SCALER_DISPLACT0 0x00000030 353 #define SCALER_DISPLACT1 0x00000034 354 #define SCALER_DISPLACT2 0x00000038 355 #define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \ 356 (x) * (SCALER_DISPLACT1 - \ 357 SCALER_DISPLACT0)) 358 359 #define SCALER_DISPCTRL0 0x00000040 360 # define SCALER_DISPCTRLX_ENABLE BIT(31) 361 # define SCALER_DISPCTRLX_RESET BIT(30) 362 # define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12) 363 # define SCALER_DISPCTRLX_WIDTH_SHIFT 12 364 # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0) 365 # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0 366 367 #define SCALER_DISPBKGND0 0x00000044 368 # define SCALER_DISPBKGND_AUTOHS BIT(31) 369 # define SCALER_DISPBKGND_INTERLACE BIT(30) 370 # define SCALER_DISPBKGND_GAMMA BIT(29) 371 # define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25) 372 # define SCALER_DISPBKGND_TESTMODE_SHIFT 25 373 /* Enables filling the scaler line with the RGB value in the low 24 374 * bits before compositing. Costs cycles, so should be skipped if 375 * opaque display planes will cover everything. 376 */ 377 # define SCALER_DISPBKGND_FILL BIT(24) 378 379 #define SCALER_DISPSTAT0 0x00000048 380 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30) 381 # define SCALER_DISPSTATX_MODE_SHIFT 30 382 # define SCALER_DISPSTATX_MODE_DISABLED 0 383 # define SCALER_DISPSTATX_MODE_INIT 1 384 # define SCALER_DISPSTATX_MODE_RUN 2 385 # define SCALER_DISPSTATX_MODE_EOF 3 386 # define SCALER_DISPSTATX_FULL BIT(29) 387 # define SCALER_DISPSTATX_EMPTY BIT(28) 388 # define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12) 389 # define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12 390 # define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0) 391 # define SCALER_DISPSTATX_LINE_SHIFT 0 392 393 #define SCALER_DISPBASE0 0x0000004c 394 /* Last pixel in the COB (display FIFO memory) allocated to this HVS 395 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the 396 * next COB base). 397 */ 398 # define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16) 399 # define SCALER_DISPBASEX_TOP_SHIFT 16 400 /* First pixel in the COB (display FIFO memory) allocated to this HVS 401 * channel. Must be 4-pixel aligned. 402 */ 403 # define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0) 404 # define SCALER_DISPBASEX_BASE_SHIFT 0 405 406 #define SCALER_DISPCTRL1 0x00000050 407 #define SCALER_DISPBKGND1 0x00000054 408 #define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \ 409 (x) * (SCALER_DISPBKGND1 - \ 410 SCALER_DISPBKGND0)) 411 #define SCALER_DISPSTAT1 0x00000058 412 #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ 413 (x) * (SCALER_DISPSTAT1 - \ 414 SCALER_DISPSTAT0)) 415 #define SCALER_DISPBASE1 0x0000005c 416 #define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \ 417 (x) * (SCALER_DISPBASE1 - \ 418 SCALER_DISPBASE0)) 419 #define SCALER_DISPCTRL2 0x00000060 420 #define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \ 421 (x) * (SCALER_DISPCTRL1 - \ 422 SCALER_DISPCTRL0)) 423 #define SCALER_DISPBKGND2 0x00000064 424 #define SCALER_DISPSTAT2 0x00000068 425 #define SCALER_DISPBASE2 0x0000006c 426 #define SCALER_DISPALPHA2 0x00000070 427 #define SCALER_GAMADDR 0x00000078 428 # define SCALER_GAMADDR_AUTOINC BIT(31) 429 /* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma 430 * enabled. 431 */ 432 # define SCALER_GAMADDR_SRAMENB BIT(30) 433 434 #define SCALER_GAMDATA 0x000000e0 435 #define SCALER_DLIST_START 0x00002000 436 #define SCALER_DLIST_SIZE 0x00004000 437 438 #define VC4_HDMI_CORE_REV 0x000 439 440 #define VC4_HDMI_SW_RESET_CONTROL 0x004 441 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1) 442 # define VC4_HDMI_SW_RESET_HDMI BIT(0) 443 444 #define VC4_HDMI_HOTPLUG_INT 0x008 445 446 #define VC4_HDMI_HOTPLUG 0x00c 447 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0) 448 449 /* 3 bits per field, where each field maps from that corresponding MAI 450 * bus channel to the given HDMI channel. 451 */ 452 #define VC4_HDMI_MAI_CHANNEL_MAP 0x090 453 454 #define VC4_HDMI_MAI_CONFIG 0x094 455 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27) 456 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26) 457 # define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0) 458 # define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0 459 460 /* Last received format word on the MAI bus. */ 461 #define VC4_HDMI_MAI_FORMAT 0x098 462 463 #define VC4_HDMI_AUDIO_PACKET_CONFIG 0x09c 464 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29) 465 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24) 466 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19) 467 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18) 468 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10) 469 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10 470 /* If set, then multichannel, otherwise 2 channel. */ 471 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9) 472 /* If set, then AUDIO_LAYOUT overrides audio_cea_mask */ 473 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8) 474 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0) 475 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0 476 477 #define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0 478 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16) 479 480 #define VC4_HDMI_RAM_PACKET_STATUS 0x0a4 481 482 #define VC4_HDMI_CRP_CFG 0x0a8 483 /* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead 484 * of pixel clock. 485 */ 486 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26) 487 /* When set, no CRP packets will be sent. */ 488 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25) 489 /* If set, generates CTS values based on N, audio clock, and video 490 * clock. N must be divisible by 128. 491 */ 492 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24) 493 # define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0) 494 # define VC4_HDMI_CRP_CFG_N_SHIFT 0 495 496 /* 20-bit fields containing CTS values to be transmitted if !EXTERNAL_CTS_EN */ 497 #define VC4_HDMI_CTS_0 0x0ac 498 #define VC4_HDMI_CTS_1 0x0b0 499 /* 20-bit fields containing number of clocks to send CTS0/1 before 500 * switching to the other one. 501 */ 502 #define VC4_HDMI_CTS_PERIOD_0 0x0b4 503 #define VC4_HDMI_CTS_PERIOD_1 0x0b8 504 505 #define VC4_HDMI_HORZA 0x0c4 506 # define VC4_HDMI_HORZA_VPOS BIT(14) 507 # define VC4_HDMI_HORZA_HPOS BIT(13) 508 /* Horizontal active pixels (hdisplay). */ 509 # define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0) 510 # define VC4_HDMI_HORZA_HAP_SHIFT 0 511 512 #define VC4_HDMI_HORZB 0x0c8 513 /* Horizontal pack porch (htotal - hsync_end). */ 514 # define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20) 515 # define VC4_HDMI_HORZB_HBP_SHIFT 20 516 /* Horizontal sync pulse (hsync_end - hsync_start). */ 517 # define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10) 518 # define VC4_HDMI_HORZB_HSP_SHIFT 10 519 /* Horizontal front porch (hsync_start - hdisplay). */ 520 # define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0) 521 # define VC4_HDMI_HORZB_HFP_SHIFT 0 522 523 #define VC4_HDMI_FIFO_CTL 0x05c 524 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14) 525 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13) 526 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7) 527 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6) 528 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5) 529 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4) 530 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3) 531 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2) 532 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1) 533 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0) 534 # define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff 535 536 #define VC4_HDMI_SCHEDULER_CONTROL 0x0c0 537 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15) 538 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5) 539 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3) 540 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1) 541 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0) 542 543 #define VC4_HDMI_VERTA0 0x0cc 544 #define VC4_HDMI_VERTA1 0x0d4 545 /* Vertical sync pulse (vsync_end - vsync_start). */ 546 # define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20) 547 # define VC4_HDMI_VERTA_VSP_SHIFT 20 548 /* Vertical front porch (vsync_start - vdisplay). */ 549 # define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13) 550 # define VC4_HDMI_VERTA_VFP_SHIFT 13 551 /* Vertical active lines (vdisplay). */ 552 # define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 553 # define VC4_HDMI_VERTA_VAL_SHIFT 0 554 555 #define VC4_HDMI_VERTB0 0x0d0 556 #define VC4_HDMI_VERTB1 0x0d8 557 /* Vertical sync pulse offset (for interlaced) */ 558 # define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9) 559 # define VC4_HDMI_VERTB_VSPO_SHIFT 9 560 /* Vertical pack porch (vtotal - vsync_end). */ 561 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0) 562 # define VC4_HDMI_VERTB_VBP_SHIFT 0 563 564 #define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0 565 566 #define VC4_HDMI_TX_PHY_CTL0 0x2c4 567 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25) 568 569 #define VC4_HDMI_GCP(x) (0x400 + ((x) * 0x4)) 570 #define VC4_HDMI_RAM_PACKET(x) (0x400 + ((x) * 0x24)) 571 #define VC4_HDMI_PACKET_STRIDE 0x24 572 573 #define VC4_HD_M_CTL 0x00c 574 # define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6) 575 # define VC4_HD_M_RAM_STANDBY (3 << 4) 576 # define VC4_HD_M_SW_RST BIT(2) 577 # define VC4_HD_M_ENABLE BIT(0) 578 579 #define VC4_HD_MAI_CTL 0x014 580 /* Set when audio stream is received at a slower rate than the 581 * sampling period, so MAI fifo goes empty. Write 1 to clear. 582 */ 583 # define VC4_HD_MAI_CTL_DLATE BIT(15) 584 # define VC4_HD_MAI_CTL_BUSY BIT(14) 585 # define VC4_HD_MAI_CTL_CHALIGN BIT(13) 586 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12) 587 # define VC4_HD_MAI_CTL_FULL BIT(11) 588 # define VC4_HD_MAI_CTL_EMPTY BIT(10) 589 # define VC4_HD_MAI_CTL_FLUSH BIT(9) 590 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing 591 * through. 592 */ 593 # define VC4_HD_MAI_CTL_PAREN BIT(8) 594 # define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4) 595 # define VC4_HD_MAI_CTL_CHNUM_SHIFT 4 596 # define VC4_HD_MAI_CTL_ENABLE BIT(3) 597 /* Underflow error status bit, write 1 to clear. */ 598 # define VC4_HD_MAI_CTL_ERRORE BIT(2) 599 /* Overflow error status bit, write 1 to clear. */ 600 # define VC4_HD_MAI_CTL_ERRORF BIT(1) 601 /* Single-shot reset bit. Read value is undefined. */ 602 # define VC4_HD_MAI_CTL_RESET BIT(0) 603 604 #define VC4_HD_MAI_THR 0x018 605 # define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24) 606 # define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24 607 # define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16) 608 # define VC4_HD_MAI_THR_PANICLOW_SHIFT 16 609 # define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8) 610 # define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8 611 # define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0) 612 # define VC4_HD_MAI_THR_DREQLOW_SHIFT 0 613 614 /* Format header to be placed on the MAI data. Unused. */ 615 #define VC4_HD_MAI_FMT 0x01c 616 617 /* Register for DMAing in audio data to be transported over the MAI 618 * bus to the Falcon core. 619 */ 620 #define VC4_HD_MAI_DATA 0x020 621 622 /* Divider from HDMI HSM clock to MAI serial clock. Sampling period 623 * converges to N / (M + 1) cycles. 624 */ 625 #define VC4_HD_MAI_SMP 0x02c 626 # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8) 627 # define VC4_HD_MAI_SMP_N_SHIFT 8 628 # define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0) 629 # define VC4_HD_MAI_SMP_M_SHIFT 0 630 631 #define VC4_HD_VID_CTL 0x038 632 # define VC4_HD_VID_CTL_ENABLE BIT(31) 633 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30) 634 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29) 635 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28) 636 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27) 637 638 #define VC4_HD_CSC_CTL 0x040 639 # define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5) 640 # define VC4_HD_CSC_CTL_ORDER_SHIFT 5 641 # define VC4_HD_CSC_CTL_ORDER_RGB 0 642 # define VC4_HD_CSC_CTL_ORDER_BGR 1 643 # define VC4_HD_CSC_CTL_ORDER_BRG 2 644 # define VC4_HD_CSC_CTL_ORDER_GRB 3 645 # define VC4_HD_CSC_CTL_ORDER_GBR 4 646 # define VC4_HD_CSC_CTL_ORDER_RBG 5 647 # define VC4_HD_CSC_CTL_PADMSB BIT(4) 648 # define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2) 649 # define VC4_HD_CSC_CTL_MODE_SHIFT 2 650 # define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0 651 # define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1 652 # define VC4_HD_CSC_CTL_MODE_CUSTOM 3 653 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1) 654 # define VC4_HD_CSC_CTL_ENABLE BIT(0) 655 656 #define VC4_HD_CSC_12_11 0x044 657 #define VC4_HD_CSC_14_13 0x048 658 #define VC4_HD_CSC_22_21 0x04c 659 #define VC4_HD_CSC_24_23 0x050 660 #define VC4_HD_CSC_32_31 0x054 661 #define VC4_HD_CSC_34_33 0x058 662 663 #define VC4_HD_FRAME_COUNT 0x068 664 665 /* HVS display list information. */ 666 #define HVS_BOOTLOADER_DLIST_END 32 667 668 enum hvs_pixel_format { 669 /* 8bpp */ 670 HVS_PIXEL_FORMAT_RGB332 = 0, 671 /* 16bpp */ 672 HVS_PIXEL_FORMAT_RGBA4444 = 1, 673 HVS_PIXEL_FORMAT_RGB555 = 2, 674 HVS_PIXEL_FORMAT_RGBA5551 = 3, 675 HVS_PIXEL_FORMAT_RGB565 = 4, 676 /* 24bpp */ 677 HVS_PIXEL_FORMAT_RGB888 = 5, 678 HVS_PIXEL_FORMAT_RGBA6666 = 6, 679 /* 32bpp */ 680 HVS_PIXEL_FORMAT_RGBA8888 = 7, 681 682 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8, 683 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9, 684 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10, 685 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11, 686 }; 687 688 /* Note: the LSB is the rightmost character shown. Only valid for 689 * HVS_PIXEL_FORMAT_RGB8888, not RGB888. 690 */ 691 #define HVS_PIXEL_ORDER_RGBA 0 692 #define HVS_PIXEL_ORDER_BGRA 1 693 #define HVS_PIXEL_ORDER_ARGB 2 694 #define HVS_PIXEL_ORDER_ABGR 3 695 696 #define HVS_PIXEL_ORDER_XBRG 0 697 #define HVS_PIXEL_ORDER_XRBG 1 698 #define HVS_PIXEL_ORDER_XRGB 2 699 #define HVS_PIXEL_ORDER_XBGR 3 700 701 #define HVS_PIXEL_ORDER_XYCBCR 0 702 #define HVS_PIXEL_ORDER_XYCRCB 1 703 #define HVS_PIXEL_ORDER_YXCBCR 2 704 #define HVS_PIXEL_ORDER_YXCRCB 3 705 706 #define SCALER_CTL0_END BIT(31) 707 #define SCALER_CTL0_VALID BIT(30) 708 709 #define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24) 710 #define SCALER_CTL0_SIZE_SHIFT 24 711 712 #define SCALER_CTL0_HFLIP BIT(16) 713 #define SCALER_CTL0_VFLIP BIT(15) 714 715 #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13) 716 #define SCALER_CTL0_ORDER_SHIFT 13 717 718 #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8) 719 #define SCALER_CTL0_SCL1_SHIFT 8 720 721 #define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5) 722 #define SCALER_CTL0_SCL0_SHIFT 5 723 724 #define SCALER_CTL0_SCL_H_PPF_V_PPF 0 725 #define SCALER_CTL0_SCL_H_TPZ_V_PPF 1 726 #define SCALER_CTL0_SCL_H_PPF_V_TPZ 2 727 #define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3 728 #define SCALER_CTL0_SCL_H_PPF_V_NONE 4 729 #define SCALER_CTL0_SCL_H_NONE_V_PPF 5 730 #define SCALER_CTL0_SCL_H_NONE_V_TPZ 6 731 #define SCALER_CTL0_SCL_H_TPZ_V_NONE 7 732 733 /* Set to indicate no scaling. */ 734 #define SCALER_CTL0_UNITY BIT(4) 735 736 #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0) 737 #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0 738 739 #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24) 740 #define SCALER_POS0_FIXED_ALPHA_SHIFT 24 741 742 #define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12) 743 #define SCALER_POS0_START_Y_SHIFT 12 744 745 #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0) 746 #define SCALER_POS0_START_X_SHIFT 0 747 748 #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16) 749 #define SCALER_POS1_SCL_HEIGHT_SHIFT 16 750 751 #define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0) 752 #define SCALER_POS1_SCL_WIDTH_SHIFT 0 753 754 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30) 755 #define SCALER_POS2_ALPHA_MODE_SHIFT 30 756 #define SCALER_POS2_ALPHA_MODE_PIPELINE 0 757 #define SCALER_POS2_ALPHA_MODE_FIXED 1 758 #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2 759 #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3 760 761 #define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16) 762 #define SCALER_POS2_HEIGHT_SHIFT 16 763 764 #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0) 765 #define SCALER_POS2_WIDTH_SHIFT 0 766 767 /* Color Space Conversion words. Some values are S2.8 signed 768 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1, 769 * 0x2: 2, 0x3: -1} 770 */ 771 /* bottom 8 bits of S2.8 contribution of Cr to Blue */ 772 #define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24) 773 #define SCALER_CSC0_COEF_CR_BLU_SHIFT 24 774 /* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */ 775 #define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16) 776 #define SCALER_CSC0_COEF_YY_OFS_SHIFT 16 777 /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */ 778 #define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8) 779 #define SCALER_CSC0_COEF_CB_OFS_SHIFT 8 780 /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */ 781 #define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0) 782 #define SCALER_CSC0_COEF_CR_OFS_SHIFT 0 783 #define SCALER_CSC0_ITR_R_601_5 0x00f00000 784 #define SCALER_CSC0_ITR_R_709_3 0x00f00000 785 #define SCALER_CSC0_JPEG_JFIF 0x00000000 786 787 /* S2.8 contribution of Cb to Green */ 788 #define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22) 789 #define SCALER_CSC1_COEF_CB_GRN_SHIFT 22 790 /* S2.8 contribution of Cr to Green */ 791 #define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12) 792 #define SCALER_CSC1_COEF_CR_GRN_SHIFT 12 793 /* S2.8 contribution of Y to all of RGB */ 794 #define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2) 795 #define SCALER_CSC1_COEF_YY_ALL_SHIFT 2 796 /* top 2 bits of S2.8 contribution of Cr to Blue */ 797 #define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0) 798 #define SCALER_CSC1_COEF_CR_BLU_SHIFT 0 799 #define SCALER_CSC1_ITR_R_601_5 0xe73304a8 800 #define SCALER_CSC1_ITR_R_709_3 0xf2b784a8 801 #define SCALER_CSC1_JPEG_JFIF 0xea34a400 802 803 /* S2.8 contribution of Cb to Red */ 804 #define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20) 805 #define SCALER_CSC2_COEF_CB_RED_SHIFT 20 806 /* S2.8 contribution of Cr to Red */ 807 #define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10) 808 #define SCALER_CSC2_COEF_CR_RED_SHIFT 10 809 /* S2.8 contribution of Cb to Blue */ 810 #define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10) 811 #define SCALER_CSC2_COEF_CB_BLU_SHIFT 10 812 #define SCALER_CSC2_ITR_R_601_5 0x00066204 813 #define SCALER_CSC2_ITR_R_709_3 0x00072a1c 814 #define SCALER_CSC2_JPEG_JFIF 0x000599c5 815 816 #define SCALER_TPZ0_VERT_RECALC BIT(31) 817 #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8) 818 #define SCALER_TPZ0_SCALE_SHIFT 8 819 #define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0) 820 #define SCALER_TPZ0_IPHASE_SHIFT 0 821 #define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0) 822 #define SCALER_TPZ1_RECIP_SHIFT 0 823 824 /* Skips interpolating coefficients to 64 phases, so just 8 are used. 825 * Required for nearest neighbor. 826 */ 827 #define SCALER_PPF_NOINTERP BIT(31) 828 /* Replaes the highest valued coefficient with one that makes all 4 829 * sum to unity. 830 */ 831 #define SCALER_PPF_AGC BIT(30) 832 #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8) 833 #define SCALER_PPF_SCALE_SHIFT 8 834 #define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0) 835 #define SCALER_PPF_IPHASE_SHIFT 0 836 837 #define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0) 838 #define SCALER_PPF_KERNEL_OFFSET_SHIFT 0 839 #define SCALER_PPF_KERNEL_UNCACHED BIT(31) 840 841 #define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0) 842 #define SCALER_SRC_PITCH_SHIFT 0 843 844 #endif /* VC4_REGS_H */ 845