1 /* 2 * Copyright © 2014-2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef VC4_REGS_H 10 #define VC4_REGS_H 11 12 #include <linux/bitops.h> 13 14 #define VC4_MASK(high, low) ((u32)GENMASK(high, low)) 15 /* Using the GNU statement expression extension */ 16 #define VC4_SET_FIELD(value, field) \ 17 ({ \ 18 uint32_t fieldval = (value) << field##_SHIFT; \ 19 WARN_ON((fieldval & ~field##_MASK) != 0); \ 20 fieldval & field##_MASK; \ 21 }) 22 23 #define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >> \ 24 field##_SHIFT) 25 26 #define V3D_IDENT0 0x00000 27 # define V3D_EXPECTED_IDENT0 \ 28 ((2 << 24) | \ 29 ('V' << 0) | \ 30 ('3' << 8) | \ 31 ('D' << 16)) 32 33 #define V3D_IDENT1 0x00004 34 /* Multiples of 1kb */ 35 # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28) 36 # define V3D_IDENT1_VPM_SIZE_SHIFT 28 37 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16) 38 # define V3D_IDENT1_NSEM_SHIFT 16 39 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12) 40 # define V3D_IDENT1_TUPS_SHIFT 12 41 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8) 42 # define V3D_IDENT1_QUPS_SHIFT 8 43 # define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4) 44 # define V3D_IDENT1_NSLC_SHIFT 4 45 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0) 46 # define V3D_IDENT1_REV_SHIFT 0 47 48 #define V3D_IDENT2 0x00008 49 #define V3D_SCRATCH 0x00010 50 #define V3D_L2CACTL 0x00020 51 # define V3D_L2CACTL_L2CCLR BIT(2) 52 # define V3D_L2CACTL_L2CDIS BIT(1) 53 # define V3D_L2CACTL_L2CENA BIT(0) 54 55 #define V3D_SLCACTL 0x00024 56 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24) 57 # define V3D_SLCACTL_T1CC_SHIFT 24 58 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16) 59 # define V3D_SLCACTL_T0CC_SHIFT 16 60 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8) 61 # define V3D_SLCACTL_UCC_SHIFT 8 62 # define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0) 63 # define V3D_SLCACTL_ICC_SHIFT 0 64 65 #define V3D_INTCTL 0x00030 66 #define V3D_INTENA 0x00034 67 #define V3D_INTDIS 0x00038 68 # define V3D_INT_SPILLUSE BIT(3) 69 # define V3D_INT_OUTOMEM BIT(2) 70 # define V3D_INT_FLDONE BIT(1) 71 # define V3D_INT_FRDONE BIT(0) 72 73 #define V3D_CT0CS 0x00100 74 #define V3D_CT1CS 0x00104 75 #define V3D_CTNCS(n) (V3D_CT0CS + 4 * n) 76 # define V3D_CTRSTA BIT(15) 77 # define V3D_CTSEMA BIT(12) 78 # define V3D_CTRTSD BIT(8) 79 # define V3D_CTRUN BIT(5) 80 # define V3D_CTSUBS BIT(4) 81 # define V3D_CTERR BIT(3) 82 # define V3D_CTMODE BIT(0) 83 84 #define V3D_CT0EA 0x00108 85 #define V3D_CT1EA 0x0010c 86 #define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n)) 87 #define V3D_CT0CA 0x00110 88 #define V3D_CT1CA 0x00114 89 #define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n)) 90 #define V3D_CT00RA0 0x00118 91 #define V3D_CT01RA0 0x0011c 92 #define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n)) 93 #define V3D_CT0LC 0x00120 94 #define V3D_CT1LC 0x00124 95 #define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n)) 96 #define V3D_CT0PC 0x00128 97 #define V3D_CT1PC 0x0012c 98 #define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n)) 99 100 #define V3D_PCS 0x00130 101 # define V3D_BMOOM BIT(8) 102 # define V3D_RMBUSY BIT(3) 103 # define V3D_RMACTIVE BIT(2) 104 # define V3D_BMBUSY BIT(1) 105 # define V3D_BMACTIVE BIT(0) 106 107 #define V3D_BFC 0x00134 108 #define V3D_RFC 0x00138 109 #define V3D_BPCA 0x00300 110 #define V3D_BPCS 0x00304 111 #define V3D_BPOA 0x00308 112 #define V3D_BPOS 0x0030c 113 #define V3D_BXCF 0x00310 114 #define V3D_SQRSV0 0x00410 115 #define V3D_SQRSV1 0x00414 116 #define V3D_SQCNTL 0x00418 117 #define V3D_SRQPC 0x00430 118 #define V3D_SRQUA 0x00434 119 #define V3D_SRQUL 0x00438 120 #define V3D_SRQCS 0x0043c 121 #define V3D_VPACNTL 0x00500 122 #define V3D_VPMBASE 0x00504 123 #define V3D_PCTRC 0x00670 124 #define V3D_PCTRE 0x00674 125 #define V3D_PCTR0 0x00680 126 #define V3D_PCTRS0 0x00684 127 #define V3D_PCTR1 0x00688 128 #define V3D_PCTRS1 0x0068c 129 #define V3D_PCTR2 0x00690 130 #define V3D_PCTRS2 0x00694 131 #define V3D_PCTR3 0x00698 132 #define V3D_PCTRS3 0x0069c 133 #define V3D_PCTR4 0x006a0 134 #define V3D_PCTRS4 0x006a4 135 #define V3D_PCTR5 0x006a8 136 #define V3D_PCTRS5 0x006ac 137 #define V3D_PCTR6 0x006b0 138 #define V3D_PCTRS6 0x006b4 139 #define V3D_PCTR7 0x006b8 140 #define V3D_PCTRS7 0x006bc 141 #define V3D_PCTR8 0x006c0 142 #define V3D_PCTRS8 0x006c4 143 #define V3D_PCTR9 0x006c8 144 #define V3D_PCTRS9 0x006cc 145 #define V3D_PCTR10 0x006d0 146 #define V3D_PCTRS10 0x006d4 147 #define V3D_PCTR11 0x006d8 148 #define V3D_PCTRS11 0x006dc 149 #define V3D_PCTR12 0x006e0 150 #define V3D_PCTRS12 0x006e4 151 #define V3D_PCTR13 0x006e8 152 #define V3D_PCTRS13 0x006ec 153 #define V3D_PCTR14 0x006f0 154 #define V3D_PCTRS14 0x006f4 155 #define V3D_PCTR15 0x006f8 156 #define V3D_PCTRS15 0x006fc 157 #define V3D_DBGE 0x00f00 158 #define V3D_FDBGO 0x00f04 159 #define V3D_FDBGB 0x00f08 160 #define V3D_FDBGR 0x00f0c 161 #define V3D_FDBGS 0x00f10 162 #define V3D_ERRSTAT 0x00f20 163 164 #define PV_CONTROL 0x00 165 # define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21) 166 # define PV_CONTROL_FORMAT_SHIFT 21 167 # define PV_CONTROL_FORMAT_24 0 168 # define PV_CONTROL_FORMAT_DSIV_16 1 169 # define PV_CONTROL_FORMAT_DSIC_16 2 170 # define PV_CONTROL_FORMAT_DSIV_18 3 171 # define PV_CONTROL_FORMAT_DSIV_24 4 172 173 # define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15) 174 # define PV_CONTROL_FIFO_LEVEL_SHIFT 15 175 # define PV_CONTROL_CLR_AT_START BIT(14) 176 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13) 177 # define PV_CONTROL_WAIT_HSTART BIT(12) 178 # define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4) 179 # define PV_CONTROL_PIXEL_REP_SHIFT 4 180 # define PV_CONTROL_CLK_SELECT_DSI_VEC 0 181 # define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1 182 # define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2) 183 # define PV_CONTROL_CLK_SELECT_SHIFT 2 184 # define PV_CONTROL_FIFO_CLR BIT(1) 185 # define PV_CONTROL_EN BIT(0) 186 187 #define PV_V_CONTROL 0x04 188 # define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6) 189 # define PV_VCONTROL_ODD_DELAY_SHIFT 6 190 # define PV_VCONTROL_ODD_FIRST BIT(5) 191 # define PV_VCONTROL_INTERLACE BIT(4) 192 # define PV_VCONTROL_CONTINUOUS BIT(1) 193 # define PV_VCONTROL_VIDEN BIT(0) 194 195 #define PV_VSYNCD_EVEN 0x08 196 197 #define PV_HORZA 0x0c 198 # define PV_HORZA_HBP_MASK VC4_MASK(31, 16) 199 # define PV_HORZA_HBP_SHIFT 16 200 # define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0) 201 # define PV_HORZA_HSYNC_SHIFT 0 202 203 #define PV_HORZB 0x10 204 # define PV_HORZB_HFP_MASK VC4_MASK(31, 16) 205 # define PV_HORZB_HFP_SHIFT 16 206 # define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0) 207 # define PV_HORZB_HACTIVE_SHIFT 0 208 209 #define PV_VERTA 0x14 210 # define PV_VERTA_VBP_MASK VC4_MASK(31, 16) 211 # define PV_VERTA_VBP_SHIFT 16 212 # define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0) 213 # define PV_VERTA_VSYNC_SHIFT 0 214 215 #define PV_VERTB 0x18 216 # define PV_VERTB_VFP_MASK VC4_MASK(31, 16) 217 # define PV_VERTB_VFP_SHIFT 16 218 # define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0) 219 # define PV_VERTB_VACTIVE_SHIFT 0 220 221 #define PV_VERTA_EVEN 0x1c 222 #define PV_VERTB_EVEN 0x20 223 224 #define PV_INTEN 0x24 225 #define PV_INTSTAT 0x28 226 # define PV_INT_VID_IDLE BIT(9) 227 # define PV_INT_VFP_END BIT(8) 228 # define PV_INT_VFP_START BIT(7) 229 # define PV_INT_VACT_START BIT(6) 230 # define PV_INT_VBP_START BIT(5) 231 # define PV_INT_VSYNC_START BIT(4) 232 # define PV_INT_HFP_START BIT(3) 233 # define PV_INT_HACT_START BIT(2) 234 # define PV_INT_HBP_START BIT(1) 235 # define PV_INT_HSYNC_START BIT(0) 236 237 #define PV_STAT 0x2c 238 239 #define PV_HACT_ACT 0x30 240 241 #define SCALER_DISPCTRL 0x00000000 242 /* Global register for clock gating the HVS */ 243 # define SCALER_DISPCTRL_ENABLE BIT(31) 244 # define SCALER_DISPCTRL_DSP2EISLUR BIT(15) 245 # define SCALER_DISPCTRL_DSP1EISLUR BIT(14) 246 /* Enables Display 0 short line and underrun contribution to 247 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are 248 * always enabled. 249 */ 250 # define SCALER_DISPCTRL_DSP0EISLUR BIT(13) 251 # define SCALER_DISPCTRL_DSP2EIEOLN BIT(12) 252 # define SCALER_DISPCTRL_DSP2EIEOF BIT(11) 253 # define SCALER_DISPCTRL_DSP1EIEOLN BIT(10) 254 # define SCALER_DISPCTRL_DSP1EIEOF BIT(9) 255 /* Enables Display 0 end-of-line-N contribution to 256 * SCALER_DISPSTAT_IRQDISP0 257 */ 258 # define SCALER_DISPCTRL_DSP0EIEOLN BIT(8) 259 /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */ 260 # define SCALER_DISPCTRL_DSP0EIEOF BIT(7) 261 262 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) 263 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5) 264 # define SCALER_DISPCTRL_DMAEIRQ BIT(4) 265 # define SCALER_DISPCTRL_DISP2EIRQ BIT(3) 266 # define SCALER_DISPCTRL_DISP1EIRQ BIT(2) 267 /* Enables interrupt generation on the enabled EOF/EOLN/EISLUR 268 * bits and short frames.. 269 */ 270 # define SCALER_DISPCTRL_DISP0EIRQ BIT(1) 271 /* Enables interrupt generation on scaler profiler interrupt. */ 272 # define SCALER_DISPCTRL_SCLEIRQ BIT(0) 273 274 #define SCALER_DISPSTAT 0x00000004 275 # define SCALER_DISPSTAT_COBLOW2 BIT(29) 276 # define SCALER_DISPSTAT_EOLN2 BIT(28) 277 # define SCALER_DISPSTAT_ESFRAME2 BIT(27) 278 # define SCALER_DISPSTAT_ESLINE2 BIT(26) 279 # define SCALER_DISPSTAT_EUFLOW2 BIT(25) 280 # define SCALER_DISPSTAT_EOF2 BIT(24) 281 282 # define SCALER_DISPSTAT_COBLOW1 BIT(21) 283 # define SCALER_DISPSTAT_EOLN1 BIT(20) 284 # define SCALER_DISPSTAT_ESFRAME1 BIT(19) 285 # define SCALER_DISPSTAT_ESLINE1 BIT(18) 286 # define SCALER_DISPSTAT_EUFLOW1 BIT(17) 287 # define SCALER_DISPSTAT_EOF1 BIT(16) 288 289 # define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14) 290 # define SCALER_DISPSTAT_RESP_SHIFT 14 291 # define SCALER_DISPSTAT_RESP_OKAY 0 292 # define SCALER_DISPSTAT_RESP_EXOKAY 1 293 # define SCALER_DISPSTAT_RESP_SLVERR 2 294 # define SCALER_DISPSTAT_RESP_DECERR 3 295 296 # define SCALER_DISPSTAT_COBLOW0 BIT(13) 297 /* Set when the DISPEOLN line is done compositing. */ 298 # define SCALER_DISPSTAT_EOLN0 BIT(12) 299 /* Set when VSTART is seen but there are still pixels in the current 300 * output line. 301 */ 302 # define SCALER_DISPSTAT_ESFRAME0 BIT(11) 303 /* Set when HSTART is seen but there are still pixels in the current 304 * output line. 305 */ 306 # define SCALER_DISPSTAT_ESLINE0 BIT(10) 307 /* Set when the the downstream tries to read from the display FIFO 308 * while it's empty. 309 */ 310 # define SCALER_DISPSTAT_EUFLOW0 BIT(9) 311 /* Set when the display mode changes from RUN to EOF */ 312 # define SCALER_DISPSTAT_EOF0 BIT(8) 313 314 /* Set on AXI invalid DMA ID error. */ 315 # define SCALER_DISPSTAT_DMA_ERROR BIT(7) 316 /* Set on AXI slave read decode error */ 317 # define SCALER_DISPSTAT_IRQSLVRD BIT(6) 318 /* Set on AXI slave write decode error */ 319 # define SCALER_DISPSTAT_IRQSLVWR BIT(5) 320 /* Set when SCALER_DISPSTAT_DMA_ERROR is set, or 321 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY. 322 */ 323 # define SCALER_DISPSTAT_IRQDMA BIT(4) 324 # define SCALER_DISPSTAT_IRQDISP2 BIT(3) 325 # define SCALER_DISPSTAT_IRQDISP1 BIT(2) 326 /* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their 327 * corresponding interrupt bit is enabled in DISPCTRL. 328 */ 329 # define SCALER_DISPSTAT_IRQDISP0 BIT(1) 330 /* On read, the profiler interrupt. On write, clear *all* interrupt bits. */ 331 # define SCALER_DISPSTAT_IRQSCL BIT(0) 332 333 #define SCALER_DISPID 0x00000008 334 #define SCALER_DISPECTRL 0x0000000c 335 #define SCALER_DISPPROF 0x00000010 336 #define SCALER_DISPDITHER 0x00000014 337 #define SCALER_DISPEOLN 0x00000018 338 #define SCALER_DISPLIST0 0x00000020 339 #define SCALER_DISPLIST1 0x00000024 340 #define SCALER_DISPLIST2 0x00000028 341 #define SCALER_DISPLSTAT 0x0000002c 342 #define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \ 343 (x) * (SCALER_DISPLIST1 - \ 344 SCALER_DISPLIST0)) 345 346 #define SCALER_DISPLACT0 0x00000030 347 #define SCALER_DISPLACT1 0x00000034 348 #define SCALER_DISPLACT2 0x00000038 349 #define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \ 350 (x) * (SCALER_DISPLACT1 - \ 351 SCALER_DISPLACT0)) 352 353 #define SCALER_DISPCTRL0 0x00000040 354 # define SCALER_DISPCTRLX_ENABLE BIT(31) 355 # define SCALER_DISPCTRLX_RESET BIT(30) 356 # define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12) 357 # define SCALER_DISPCTRLX_WIDTH_SHIFT 12 358 # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0) 359 # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0 360 361 #define SCALER_DISPBKGND0 0x00000044 362 # define SCALER_DISPBKGND_AUTOHS BIT(31) 363 # define SCALER_DISPBKGND_INTERLACE BIT(30) 364 # define SCALER_DISPBKGND_GAMMA BIT(29) 365 # define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25) 366 # define SCALER_DISPBKGND_TESTMODE_SHIFT 25 367 /* Enables filling the scaler line with the RGB value in the low 24 368 * bits before compositing. Costs cycles, so should be skipped if 369 * opaque display planes will cover everything. 370 */ 371 # define SCALER_DISPBKGND_FILL BIT(24) 372 373 #define SCALER_DISPSTAT0 0x00000048 374 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30) 375 # define SCALER_DISPSTATX_MODE_SHIFT 30 376 # define SCALER_DISPSTATX_MODE_DISABLED 0 377 # define SCALER_DISPSTATX_MODE_INIT 1 378 # define SCALER_DISPSTATX_MODE_RUN 2 379 # define SCALER_DISPSTATX_MODE_EOF 3 380 # define SCALER_DISPSTATX_FULL BIT(29) 381 # define SCALER_DISPSTATX_EMPTY BIT(28) 382 # define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12) 383 # define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12 384 # define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0) 385 # define SCALER_DISPSTATX_LINE_SHIFT 0 386 387 #define SCALER_DISPBASE0 0x0000004c 388 /* Last pixel in the COB (display FIFO memory) allocated to this HVS 389 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the 390 * next COB base). 391 */ 392 # define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16) 393 # define SCALER_DISPBASEX_TOP_SHIFT 16 394 /* First pixel in the COB (display FIFO memory) allocated to this HVS 395 * channel. Must be 4-pixel aligned. 396 */ 397 # define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0) 398 # define SCALER_DISPBASEX_BASE_SHIFT 0 399 400 #define SCALER_DISPCTRL1 0x00000050 401 #define SCALER_DISPBKGND1 0x00000054 402 #define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \ 403 (x) * (SCALER_DISPBKGND1 - \ 404 SCALER_DISPBKGND0)) 405 #define SCALER_DISPSTAT1 0x00000058 406 #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ 407 (x) * (SCALER_DISPSTAT1 - \ 408 SCALER_DISPSTAT0)) 409 #define SCALER_DISPBASE1 0x0000005c 410 #define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \ 411 (x) * (SCALER_DISPBASE1 - \ 412 SCALER_DISPBASE0)) 413 #define SCALER_DISPCTRL2 0x00000060 414 #define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \ 415 (x) * (SCALER_DISPCTRL1 - \ 416 SCALER_DISPCTRL0)) 417 #define SCALER_DISPBKGND2 0x00000064 418 #define SCALER_DISPSTAT2 0x00000068 419 #define SCALER_DISPBASE2 0x0000006c 420 #define SCALER_DISPALPHA2 0x00000070 421 #define SCALER_GAMADDR 0x00000078 422 # define SCALER_GAMADDR_AUTOINC BIT(31) 423 /* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma 424 * enabled. 425 */ 426 # define SCALER_GAMADDR_SRAMENB BIT(30) 427 428 #define SCALER_GAMDATA 0x000000e0 429 #define SCALER_DLIST_START 0x00002000 430 #define SCALER_DLIST_SIZE 0x00004000 431 432 #define VC4_HDMI_CORE_REV 0x000 433 434 #define VC4_HDMI_SW_RESET_CONTROL 0x004 435 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1) 436 # define VC4_HDMI_SW_RESET_HDMI BIT(0) 437 438 #define VC4_HDMI_HOTPLUG_INT 0x008 439 440 #define VC4_HDMI_HOTPLUG 0x00c 441 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0) 442 443 #define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0 444 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16) 445 446 #define VC4_HDMI_RAM_PACKET_STATUS 0x0a4 447 448 #define VC4_HDMI_HORZA 0x0c4 449 # define VC4_HDMI_HORZA_VPOS BIT(14) 450 # define VC4_HDMI_HORZA_HPOS BIT(13) 451 /* Horizontal active pixels (hdisplay). */ 452 # define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0) 453 # define VC4_HDMI_HORZA_HAP_SHIFT 0 454 455 #define VC4_HDMI_HORZB 0x0c8 456 /* Horizontal pack porch (htotal - hsync_end). */ 457 # define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20) 458 # define VC4_HDMI_HORZB_HBP_SHIFT 20 459 /* Horizontal sync pulse (hsync_end - hsync_start). */ 460 # define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10) 461 # define VC4_HDMI_HORZB_HSP_SHIFT 10 462 /* Horizontal front porch (hsync_start - hdisplay). */ 463 # define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0) 464 # define VC4_HDMI_HORZB_HFP_SHIFT 0 465 466 #define VC4_HDMI_FIFO_CTL 0x05c 467 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14) 468 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13) 469 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7) 470 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6) 471 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5) 472 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4) 473 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3) 474 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2) 475 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1) 476 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0) 477 # define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff 478 479 #define VC4_HDMI_SCHEDULER_CONTROL 0x0c0 480 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15) 481 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5) 482 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3) 483 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1) 484 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0) 485 486 #define VC4_HDMI_VERTA0 0x0cc 487 #define VC4_HDMI_VERTA1 0x0d4 488 /* Vertical sync pulse (vsync_end - vsync_start). */ 489 # define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20) 490 # define VC4_HDMI_VERTA_VSP_SHIFT 20 491 /* Vertical front porch (vsync_start - vdisplay). */ 492 # define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13) 493 # define VC4_HDMI_VERTA_VFP_SHIFT 13 494 /* Vertical active lines (vdisplay). */ 495 # define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 496 # define VC4_HDMI_VERTA_VAL_SHIFT 0 497 498 #define VC4_HDMI_VERTB0 0x0d0 499 #define VC4_HDMI_VERTB1 0x0d8 500 /* Vertical sync pulse offset (for interlaced) */ 501 # define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9) 502 # define VC4_HDMI_VERTB_VSPO_SHIFT 9 503 /* Vertical pack porch (vtotal - vsync_end). */ 504 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0) 505 # define VC4_HDMI_VERTB_VBP_SHIFT 0 506 507 #define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0 508 509 #define VC4_HDMI_GCP_0 0x400 510 #define VC4_HDMI_PACKET_STRIDE 0x24 511 512 #define VC4_HD_M_CTL 0x00c 513 # define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6) 514 # define VC4_HD_M_RAM_STANDBY (3 << 4) 515 # define VC4_HD_M_SW_RST BIT(2) 516 # define VC4_HD_M_ENABLE BIT(0) 517 518 #define VC4_HD_MAI_CTL 0x014 519 520 #define VC4_HD_VID_CTL 0x038 521 # define VC4_HD_VID_CTL_ENABLE BIT(31) 522 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30) 523 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29) 524 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28) 525 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27) 526 527 #define VC4_HD_CSC_CTL 0x040 528 # define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5) 529 # define VC4_HD_CSC_CTL_ORDER_SHIFT 5 530 # define VC4_HD_CSC_CTL_ORDER_RGB 0 531 # define VC4_HD_CSC_CTL_ORDER_BGR 1 532 # define VC4_HD_CSC_CTL_ORDER_BRG 2 533 # define VC4_HD_CSC_CTL_ORDER_GRB 3 534 # define VC4_HD_CSC_CTL_ORDER_GBR 4 535 # define VC4_HD_CSC_CTL_ORDER_RBG 5 536 # define VC4_HD_CSC_CTL_PADMSB BIT(4) 537 # define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2) 538 # define VC4_HD_CSC_CTL_MODE_SHIFT 2 539 # define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0 540 # define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1 541 # define VC4_HD_CSC_CTL_MODE_CUSTOM 3 542 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1) 543 # define VC4_HD_CSC_CTL_ENABLE BIT(0) 544 545 #define VC4_HD_CSC_12_11 0x044 546 #define VC4_HD_CSC_14_13 0x048 547 #define VC4_HD_CSC_22_21 0x04c 548 #define VC4_HD_CSC_24_23 0x050 549 #define VC4_HD_CSC_32_31 0x054 550 #define VC4_HD_CSC_34_33 0x058 551 552 #define VC4_HD_FRAME_COUNT 0x068 553 554 /* HVS display list information. */ 555 #define HVS_BOOTLOADER_DLIST_END 32 556 557 enum hvs_pixel_format { 558 /* 8bpp */ 559 HVS_PIXEL_FORMAT_RGB332 = 0, 560 /* 16bpp */ 561 HVS_PIXEL_FORMAT_RGBA4444 = 1, 562 HVS_PIXEL_FORMAT_RGB555 = 2, 563 HVS_PIXEL_FORMAT_RGBA5551 = 3, 564 HVS_PIXEL_FORMAT_RGB565 = 4, 565 /* 24bpp */ 566 HVS_PIXEL_FORMAT_RGB888 = 5, 567 HVS_PIXEL_FORMAT_RGBA6666 = 6, 568 /* 32bpp */ 569 HVS_PIXEL_FORMAT_RGBA8888 = 7, 570 571 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8, 572 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9, 573 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10, 574 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11, 575 }; 576 577 /* Note: the LSB is the rightmost character shown. Only valid for 578 * HVS_PIXEL_FORMAT_RGB8888, not RGB888. 579 */ 580 #define HVS_PIXEL_ORDER_RGBA 0 581 #define HVS_PIXEL_ORDER_BGRA 1 582 #define HVS_PIXEL_ORDER_ARGB 2 583 #define HVS_PIXEL_ORDER_ABGR 3 584 585 #define HVS_PIXEL_ORDER_XBRG 0 586 #define HVS_PIXEL_ORDER_XRBG 1 587 #define HVS_PIXEL_ORDER_XRGB 2 588 #define HVS_PIXEL_ORDER_XBGR 3 589 590 #define HVS_PIXEL_ORDER_XYCBCR 0 591 #define HVS_PIXEL_ORDER_XYCRCB 1 592 #define HVS_PIXEL_ORDER_YXCBCR 2 593 #define HVS_PIXEL_ORDER_YXCRCB 3 594 595 #define SCALER_CTL0_END BIT(31) 596 #define SCALER_CTL0_VALID BIT(30) 597 598 #define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24) 599 #define SCALER_CTL0_SIZE_SHIFT 24 600 601 #define SCALER_CTL0_HFLIP BIT(16) 602 #define SCALER_CTL0_VFLIP BIT(15) 603 604 #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13) 605 #define SCALER_CTL0_ORDER_SHIFT 13 606 607 #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8) 608 #define SCALER_CTL0_SCL1_SHIFT 8 609 610 #define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5) 611 #define SCALER_CTL0_SCL0_SHIFT 5 612 613 #define SCALER_CTL0_SCL_H_PPF_V_PPF 0 614 #define SCALER_CTL0_SCL_H_TPZ_V_PPF 1 615 #define SCALER_CTL0_SCL_H_PPF_V_TPZ 2 616 #define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3 617 #define SCALER_CTL0_SCL_H_PPF_V_NONE 4 618 #define SCALER_CTL0_SCL_H_NONE_V_PPF 5 619 #define SCALER_CTL0_SCL_H_NONE_V_TPZ 6 620 #define SCALER_CTL0_SCL_H_TPZ_V_NONE 7 621 622 /* Set to indicate no scaling. */ 623 #define SCALER_CTL0_UNITY BIT(4) 624 625 #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0) 626 #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0 627 628 #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24) 629 #define SCALER_POS0_FIXED_ALPHA_SHIFT 24 630 631 #define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12) 632 #define SCALER_POS0_START_Y_SHIFT 12 633 634 #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0) 635 #define SCALER_POS0_START_X_SHIFT 0 636 637 #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16) 638 #define SCALER_POS1_SCL_HEIGHT_SHIFT 16 639 640 #define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0) 641 #define SCALER_POS1_SCL_WIDTH_SHIFT 0 642 643 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30) 644 #define SCALER_POS2_ALPHA_MODE_SHIFT 30 645 #define SCALER_POS2_ALPHA_MODE_PIPELINE 0 646 #define SCALER_POS2_ALPHA_MODE_FIXED 1 647 #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2 648 #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3 649 650 #define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16) 651 #define SCALER_POS2_HEIGHT_SHIFT 16 652 653 #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0) 654 #define SCALER_POS2_WIDTH_SHIFT 0 655 656 /* Color Space Conversion words. Some values are S2.8 signed 657 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1, 658 * 0x2: 2, 0x3: -1} 659 */ 660 /* bottom 8 bits of S2.8 contribution of Cr to Blue */ 661 #define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24) 662 #define SCALER_CSC0_COEF_CR_BLU_SHIFT 24 663 /* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */ 664 #define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16) 665 #define SCALER_CSC0_COEF_YY_OFS_SHIFT 16 666 /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */ 667 #define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8) 668 #define SCALER_CSC0_COEF_CB_OFS_SHIFT 8 669 /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */ 670 #define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0) 671 #define SCALER_CSC0_COEF_CR_OFS_SHIFT 0 672 #define SCALER_CSC0_ITR_R_601_5 0x00f00000 673 #define SCALER_CSC0_ITR_R_709_3 0x00f00000 674 #define SCALER_CSC0_JPEG_JFIF 0x00000000 675 676 /* S2.8 contribution of Cb to Green */ 677 #define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22) 678 #define SCALER_CSC1_COEF_CB_GRN_SHIFT 22 679 /* S2.8 contribution of Cr to Green */ 680 #define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12) 681 #define SCALER_CSC1_COEF_CR_GRN_SHIFT 12 682 /* S2.8 contribution of Y to all of RGB */ 683 #define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2) 684 #define SCALER_CSC1_COEF_YY_ALL_SHIFT 2 685 /* top 2 bits of S2.8 contribution of Cr to Blue */ 686 #define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0) 687 #define SCALER_CSC1_COEF_CR_BLU_SHIFT 0 688 #define SCALER_CSC1_ITR_R_601_5 0xe73304a8 689 #define SCALER_CSC1_ITR_R_709_3 0xf2b784a8 690 #define SCALER_CSC1_JPEG_JFIF 0xea34a400 691 692 /* S2.8 contribution of Cb to Red */ 693 #define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20) 694 #define SCALER_CSC2_COEF_CB_RED_SHIFT 20 695 /* S2.8 contribution of Cr to Red */ 696 #define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10) 697 #define SCALER_CSC2_COEF_CR_RED_SHIFT 10 698 /* S2.8 contribution of Cb to Blue */ 699 #define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10) 700 #define SCALER_CSC2_COEF_CB_BLU_SHIFT 10 701 #define SCALER_CSC2_ITR_R_601_5 0x00066204 702 #define SCALER_CSC2_ITR_R_709_3 0x00072a1c 703 #define SCALER_CSC2_JPEG_JFIF 0x000599c5 704 705 #define SCALER_TPZ0_VERT_RECALC BIT(31) 706 #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8) 707 #define SCALER_TPZ0_SCALE_SHIFT 8 708 #define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0) 709 #define SCALER_TPZ0_IPHASE_SHIFT 0 710 #define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0) 711 #define SCALER_TPZ1_RECIP_SHIFT 0 712 713 /* Skips interpolating coefficients to 64 phases, so just 8 are used. 714 * Required for nearest neighbor. 715 */ 716 #define SCALER_PPF_NOINTERP BIT(31) 717 /* Replaes the highest valued coefficient with one that makes all 4 718 * sum to unity. 719 */ 720 #define SCALER_PPF_AGC BIT(30) 721 #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8) 722 #define SCALER_PPF_SCALE_SHIFT 8 723 #define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0) 724 #define SCALER_PPF_IPHASE_SHIFT 0 725 726 #define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0) 727 #define SCALER_PPF_KERNEL_OFFSET_SHIFT 0 728 #define SCALER_PPF_KERNEL_UNCACHED BIT(31) 729 730 #define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0) 731 #define SCALER_SRC_PITCH_SHIFT 0 732 733 #endif /* VC4_REGS_H */ 734