1 /* 2 * Copyright © 2014-2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef VC4_REGS_H 10 #define VC4_REGS_H 11 12 #include <linux/bitops.h> 13 14 #define VC4_MASK(high, low) ((u32)GENMASK(high, low)) 15 /* Using the GNU statement expression extension */ 16 #define VC4_SET_FIELD(value, field) \ 17 ({ \ 18 uint32_t fieldval = (value) << field##_SHIFT; \ 19 WARN_ON((fieldval & ~field##_MASK) != 0); \ 20 fieldval & field##_MASK; \ 21 }) 22 23 #define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >> \ 24 field##_SHIFT) 25 26 #define V3D_IDENT0 0x00000 27 # define V3D_EXPECTED_IDENT0 \ 28 ((2 << 24) | \ 29 ('V' << 0) | \ 30 ('3' << 8) | \ 31 ('D' << 16)) 32 33 #define V3D_IDENT1 0x00004 34 /* Multiples of 1kb */ 35 # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28) 36 # define V3D_IDENT1_VPM_SIZE_SHIFT 28 37 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16) 38 # define V3D_IDENT1_NSEM_SHIFT 16 39 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12) 40 # define V3D_IDENT1_TUPS_SHIFT 12 41 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8) 42 # define V3D_IDENT1_QUPS_SHIFT 8 43 # define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4) 44 # define V3D_IDENT1_NSLC_SHIFT 4 45 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0) 46 # define V3D_IDENT1_REV_SHIFT 0 47 48 #define V3D_IDENT2 0x00008 49 #define V3D_SCRATCH 0x00010 50 #define V3D_L2CACTL 0x00020 51 # define V3D_L2CACTL_L2CCLR BIT(2) 52 # define V3D_L2CACTL_L2CDIS BIT(1) 53 # define V3D_L2CACTL_L2CENA BIT(0) 54 55 #define V3D_SLCACTL 0x00024 56 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24) 57 # define V3D_SLCACTL_T1CC_SHIFT 24 58 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16) 59 # define V3D_SLCACTL_T0CC_SHIFT 16 60 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8) 61 # define V3D_SLCACTL_UCC_SHIFT 8 62 # define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0) 63 # define V3D_SLCACTL_ICC_SHIFT 0 64 65 #define V3D_INTCTL 0x00030 66 #define V3D_INTENA 0x00034 67 #define V3D_INTDIS 0x00038 68 # define V3D_INT_SPILLUSE BIT(3) 69 # define V3D_INT_OUTOMEM BIT(2) 70 # define V3D_INT_FLDONE BIT(1) 71 # define V3D_INT_FRDONE BIT(0) 72 73 #define V3D_CT0CS 0x00100 74 #define V3D_CT1CS 0x00104 75 #define V3D_CTNCS(n) (V3D_CT0CS + 4 * n) 76 # define V3D_CTRSTA BIT(15) 77 # define V3D_CTSEMA BIT(12) 78 # define V3D_CTRTSD BIT(8) 79 # define V3D_CTRUN BIT(5) 80 # define V3D_CTSUBS BIT(4) 81 # define V3D_CTERR BIT(3) 82 # define V3D_CTMODE BIT(0) 83 84 #define V3D_CT0EA 0x00108 85 #define V3D_CT1EA 0x0010c 86 #define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n)) 87 #define V3D_CT0CA 0x00110 88 #define V3D_CT1CA 0x00114 89 #define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n)) 90 #define V3D_CT00RA0 0x00118 91 #define V3D_CT01RA0 0x0011c 92 #define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n)) 93 #define V3D_CT0LC 0x00120 94 #define V3D_CT1LC 0x00124 95 #define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n)) 96 #define V3D_CT0PC 0x00128 97 #define V3D_CT1PC 0x0012c 98 #define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n)) 99 100 #define V3D_PCS 0x00130 101 # define V3D_BMOOM BIT(8) 102 # define V3D_RMBUSY BIT(3) 103 # define V3D_RMACTIVE BIT(2) 104 # define V3D_BMBUSY BIT(1) 105 # define V3D_BMACTIVE BIT(0) 106 107 #define V3D_BFC 0x00134 108 #define V3D_RFC 0x00138 109 #define V3D_BPCA 0x00300 110 #define V3D_BPCS 0x00304 111 #define V3D_BPOA 0x00308 112 #define V3D_BPOS 0x0030c 113 #define V3D_BXCF 0x00310 114 #define V3D_SQRSV0 0x00410 115 #define V3D_SQRSV1 0x00414 116 #define V3D_SQCNTL 0x00418 117 #define V3D_SRQPC 0x00430 118 #define V3D_SRQUA 0x00434 119 #define V3D_SRQUL 0x00438 120 #define V3D_SRQCS 0x0043c 121 #define V3D_VPACNTL 0x00500 122 #define V3D_VPMBASE 0x00504 123 #define V3D_PCTRC 0x00670 124 #define V3D_PCTRE 0x00674 125 # define V3D_PCTRE_EN BIT(31) 126 #define V3D_PCTR(x) (0x00680 + ((x) * 8)) 127 #define V3D_PCTRS(x) (0x00684 + ((x) * 8)) 128 #define V3D_DBGE 0x00f00 129 #define V3D_FDBGO 0x00f04 130 #define V3D_FDBGB 0x00f08 131 #define V3D_FDBGR 0x00f0c 132 #define V3D_FDBGS 0x00f10 133 #define V3D_ERRSTAT 0x00f20 134 135 #define PV_CONTROL 0x00 136 # define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21) 137 # define PV_CONTROL_FORMAT_SHIFT 21 138 # define PV_CONTROL_FORMAT_24 0 139 # define PV_CONTROL_FORMAT_DSIV_16 1 140 # define PV_CONTROL_FORMAT_DSIC_16 2 141 # define PV_CONTROL_FORMAT_DSIV_18 3 142 # define PV_CONTROL_FORMAT_DSIV_24 4 143 144 # define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15) 145 # define PV_CONTROL_FIFO_LEVEL_SHIFT 15 146 # define PV_CONTROL_CLR_AT_START BIT(14) 147 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13) 148 # define PV_CONTROL_WAIT_HSTART BIT(12) 149 # define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4) 150 # define PV_CONTROL_PIXEL_REP_SHIFT 4 151 # define PV_CONTROL_CLK_SELECT_DSI 0 152 # define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1 153 # define PV_CONTROL_CLK_SELECT_VEC 2 154 # define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2) 155 # define PV_CONTROL_CLK_SELECT_SHIFT 2 156 # define PV_CONTROL_FIFO_CLR BIT(1) 157 # define PV_CONTROL_EN BIT(0) 158 159 #define PV_V_CONTROL 0x04 160 # define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6) 161 # define PV_VCONTROL_ODD_DELAY_SHIFT 6 162 # define PV_VCONTROL_ODD_FIRST BIT(5) 163 # define PV_VCONTROL_INTERLACE BIT(4) 164 # define PV_VCONTROL_DSI BIT(3) 165 # define PV_VCONTROL_COMMAND BIT(2) 166 # define PV_VCONTROL_CONTINUOUS BIT(1) 167 # define PV_VCONTROL_VIDEN BIT(0) 168 169 #define PV_VSYNCD_EVEN 0x08 170 171 #define PV_HORZA 0x0c 172 # define PV_HORZA_HBP_MASK VC4_MASK(31, 16) 173 # define PV_HORZA_HBP_SHIFT 16 174 # define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0) 175 # define PV_HORZA_HSYNC_SHIFT 0 176 177 #define PV_HORZB 0x10 178 # define PV_HORZB_HFP_MASK VC4_MASK(31, 16) 179 # define PV_HORZB_HFP_SHIFT 16 180 # define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0) 181 # define PV_HORZB_HACTIVE_SHIFT 0 182 183 #define PV_VERTA 0x14 184 # define PV_VERTA_VBP_MASK VC4_MASK(31, 16) 185 # define PV_VERTA_VBP_SHIFT 16 186 # define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0) 187 # define PV_VERTA_VSYNC_SHIFT 0 188 189 #define PV_VERTB 0x18 190 # define PV_VERTB_VFP_MASK VC4_MASK(31, 16) 191 # define PV_VERTB_VFP_SHIFT 16 192 # define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0) 193 # define PV_VERTB_VACTIVE_SHIFT 0 194 195 #define PV_VERTA_EVEN 0x1c 196 #define PV_VERTB_EVEN 0x20 197 198 #define PV_INTEN 0x24 199 #define PV_INTSTAT 0x28 200 # define PV_INT_VID_IDLE BIT(9) 201 # define PV_INT_VFP_END BIT(8) 202 # define PV_INT_VFP_START BIT(7) 203 # define PV_INT_VACT_START BIT(6) 204 # define PV_INT_VBP_START BIT(5) 205 # define PV_INT_VSYNC_START BIT(4) 206 # define PV_INT_HFP_START BIT(3) 207 # define PV_INT_HACT_START BIT(2) 208 # define PV_INT_HBP_START BIT(1) 209 # define PV_INT_HSYNC_START BIT(0) 210 211 #define PV_STAT 0x2c 212 213 #define PV_HACT_ACT 0x30 214 215 #define SCALER_CHANNELS_COUNT 3 216 217 #define SCALER_DISPCTRL 0x00000000 218 /* Global register for clock gating the HVS */ 219 # define SCALER_DISPCTRL_ENABLE BIT(31) 220 # define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18) 221 # define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18 222 223 /* Enables Display 0 short line and underrun contribution to 224 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are 225 * always enabled. 226 */ 227 # define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x)) 228 /* Enables Display 0 end-of-line-N contribution to 229 * SCALER_DISPSTAT_IRQDISP0 230 */ 231 # define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2)) 232 /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */ 233 # define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2)) 234 235 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) 236 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5) 237 # define SCALER_DISPCTRL_DMAEIRQ BIT(4) 238 /* Enables interrupt generation on the enabled EOF/EOLN/EISLUR 239 * bits and short frames.. 240 */ 241 # define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x)) 242 /* Enables interrupt generation on scaler profiler interrupt. */ 243 # define SCALER_DISPCTRL_SCLEIRQ BIT(0) 244 245 #define SCALER_DISPSTAT 0x00000004 246 # define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14) 247 # define SCALER_DISPSTAT_RESP_SHIFT 14 248 # define SCALER_DISPSTAT_RESP_OKAY 0 249 # define SCALER_DISPSTAT_RESP_EXOKAY 1 250 # define SCALER_DISPSTAT_RESP_SLVERR 2 251 # define SCALER_DISPSTAT_RESP_DECERR 3 252 253 # define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8)) 254 /* Set when the DISPEOLN line is done compositing. */ 255 # define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8)) 256 /* Set when VSTART is seen but there are still pixels in the current 257 * output line. 258 */ 259 # define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8)) 260 /* Set when HSTART is seen but there are still pixels in the current 261 * output line. 262 */ 263 # define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8)) 264 /* Set when the the downstream tries to read from the display FIFO 265 * while it's empty. 266 */ 267 # define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8)) 268 /* Set when the display mode changes from RUN to EOF */ 269 # define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8)) 270 271 # define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \ 272 8 + ((x) * 8)) 273 274 /* Set on AXI invalid DMA ID error. */ 275 # define SCALER_DISPSTAT_DMA_ERROR BIT(7) 276 /* Set on AXI slave read decode error */ 277 # define SCALER_DISPSTAT_IRQSLVRD BIT(6) 278 /* Set on AXI slave write decode error */ 279 # define SCALER_DISPSTAT_IRQSLVWR BIT(5) 280 /* Set when SCALER_DISPSTAT_DMA_ERROR is set, or 281 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY. 282 */ 283 # define SCALER_DISPSTAT_IRQDMA BIT(4) 284 /* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their 285 * corresponding interrupt bit is enabled in DISPCTRL. 286 */ 287 # define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x)) 288 /* On read, the profiler interrupt. On write, clear *all* interrupt bits. */ 289 # define SCALER_DISPSTAT_IRQSCL BIT(0) 290 291 #define SCALER_DISPID 0x00000008 292 #define SCALER_DISPECTRL 0x0000000c 293 #define SCALER_DISPPROF 0x00000010 294 #define SCALER_DISPDITHER 0x00000014 295 #define SCALER_DISPEOLN 0x00000018 296 #define SCALER_DISPLIST0 0x00000020 297 #define SCALER_DISPLIST1 0x00000024 298 #define SCALER_DISPLIST2 0x00000028 299 #define SCALER_DISPLSTAT 0x0000002c 300 #define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \ 301 (x) * (SCALER_DISPLIST1 - \ 302 SCALER_DISPLIST0)) 303 304 #define SCALER_DISPLACT0 0x00000030 305 #define SCALER_DISPLACT1 0x00000034 306 #define SCALER_DISPLACT2 0x00000038 307 #define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \ 308 (x) * (SCALER_DISPLACT1 - \ 309 SCALER_DISPLACT0)) 310 311 #define SCALER_DISPCTRL0 0x00000040 312 # define SCALER_DISPCTRLX_ENABLE BIT(31) 313 # define SCALER_DISPCTRLX_RESET BIT(30) 314 /* Generates a single frame when VSTART is seen and stops at the last 315 * pixel read from the FIFO. 316 */ 317 # define SCALER_DISPCTRLX_ONESHOT BIT(29) 318 /* Processes a single context in the dlist and then task switch, 319 * instead of an entire line. 320 */ 321 # define SCALER_DISPCTRLX_ONECTX BIT(28) 322 /* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */ 323 # define SCALER_DISPCTRLX_FIFO32 BIT(27) 324 /* Turns on output to the DISPSLAVE register instead of the normal 325 * FIFO. 326 */ 327 # define SCALER_DISPCTRLX_FIFOREG BIT(26) 328 329 # define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12) 330 # define SCALER_DISPCTRLX_WIDTH_SHIFT 12 331 # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0) 332 # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0 333 334 #define SCALER_DISPBKGND0 0x00000044 335 # define SCALER_DISPBKGND_AUTOHS BIT(31) 336 # define SCALER_DISPBKGND_INTERLACE BIT(30) 337 # define SCALER_DISPBKGND_GAMMA BIT(29) 338 # define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25) 339 # define SCALER_DISPBKGND_TESTMODE_SHIFT 25 340 /* Enables filling the scaler line with the RGB value in the low 24 341 * bits before compositing. Costs cycles, so should be skipped if 342 * opaque display planes will cover everything. 343 */ 344 # define SCALER_DISPBKGND_FILL BIT(24) 345 346 #define SCALER_DISPSTAT0 0x00000048 347 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30) 348 # define SCALER_DISPSTATX_MODE_SHIFT 30 349 # define SCALER_DISPSTATX_MODE_DISABLED 0 350 # define SCALER_DISPSTATX_MODE_INIT 1 351 # define SCALER_DISPSTATX_MODE_RUN 2 352 # define SCALER_DISPSTATX_MODE_EOF 3 353 # define SCALER_DISPSTATX_FULL BIT(29) 354 # define SCALER_DISPSTATX_EMPTY BIT(28) 355 # define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12) 356 # define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12 357 # define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0) 358 # define SCALER_DISPSTATX_LINE_SHIFT 0 359 360 #define SCALER_DISPBASE0 0x0000004c 361 /* Last pixel in the COB (display FIFO memory) allocated to this HVS 362 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the 363 * next COB base). 364 */ 365 # define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16) 366 # define SCALER_DISPBASEX_TOP_SHIFT 16 367 /* First pixel in the COB (display FIFO memory) allocated to this HVS 368 * channel. Must be 4-pixel aligned. 369 */ 370 # define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0) 371 # define SCALER_DISPBASEX_BASE_SHIFT 0 372 373 #define SCALER_DISPCTRL1 0x00000050 374 #define SCALER_DISPBKGND1 0x00000054 375 #define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \ 376 (x) * (SCALER_DISPBKGND1 - \ 377 SCALER_DISPBKGND0)) 378 #define SCALER_DISPSTAT1 0x00000058 379 #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ 380 (x) * (SCALER_DISPSTAT1 - \ 381 SCALER_DISPSTAT0)) 382 #define SCALER_DISPBASE1 0x0000005c 383 #define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \ 384 (x) * (SCALER_DISPBASE1 - \ 385 SCALER_DISPBASE0)) 386 #define SCALER_DISPCTRL2 0x00000060 387 #define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \ 388 (x) * (SCALER_DISPCTRL1 - \ 389 SCALER_DISPCTRL0)) 390 #define SCALER_DISPBKGND2 0x00000064 391 #define SCALER_DISPSTAT2 0x00000068 392 #define SCALER_DISPBASE2 0x0000006c 393 #define SCALER_DISPALPHA2 0x00000070 394 #define SCALER_GAMADDR 0x00000078 395 # define SCALER_GAMADDR_AUTOINC BIT(31) 396 /* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma 397 * enabled. 398 */ 399 # define SCALER_GAMADDR_SRAMENB BIT(30) 400 401 #define SCALER_OLEDOFFS 0x00000080 402 /* Clamps R to [16,235] and G/B to [16,240]. */ 403 # define SCALER_OLEDOFFS_YUVCLAMP BIT(31) 404 405 /* Chooses which display FIFO the matrix applies to. */ 406 # define SCALER_OLEDOFFS_DISPFIFO_MASK VC4_MASK(25, 24) 407 # define SCALER_OLEDOFFS_DISPFIFO_SHIFT 24 408 # define SCALER_OLEDOFFS_DISPFIFO_DISABLED 0 409 # define SCALER_OLEDOFFS_DISPFIFO_0 1 410 # define SCALER_OLEDOFFS_DISPFIFO_1 2 411 # define SCALER_OLEDOFFS_DISPFIFO_2 3 412 413 /* Offsets are 8-bit 2s-complement. */ 414 # define SCALER_OLEDOFFS_RED_MASK VC4_MASK(23, 16) 415 # define SCALER_OLEDOFFS_RED_SHIFT 16 416 # define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8) 417 # define SCALER_OLEDOFFS_GREEN_SHIFT 8 418 # define SCALER_OLEDOFFS_BLUE_MASK VC4_MASK(7, 0) 419 # define SCALER_OLEDOFFS_BLUE_SHIFT 0 420 421 /* The coefficients are S0.9 fractions. */ 422 #define SCALER_OLEDCOEF0 0x00000084 423 # define SCALER_OLEDCOEF0_B_TO_R_MASK VC4_MASK(29, 20) 424 # define SCALER_OLEDCOEF0_B_TO_R_SHIFT 20 425 # define SCALER_OLEDCOEF0_B_TO_G_MASK VC4_MASK(19, 10) 426 # define SCALER_OLEDCOEF0_B_TO_G_SHIFT 10 427 # define SCALER_OLEDCOEF0_B_TO_B_MASK VC4_MASK(9, 0) 428 # define SCALER_OLEDCOEF0_B_TO_B_SHIFT 0 429 430 #define SCALER_OLEDCOEF1 0x00000088 431 # define SCALER_OLEDCOEF1_G_TO_R_MASK VC4_MASK(29, 20) 432 # define SCALER_OLEDCOEF1_G_TO_R_SHIFT 20 433 # define SCALER_OLEDCOEF1_G_TO_G_MASK VC4_MASK(19, 10) 434 # define SCALER_OLEDCOEF1_G_TO_G_SHIFT 10 435 # define SCALER_OLEDCOEF1_G_TO_B_MASK VC4_MASK(9, 0) 436 # define SCALER_OLEDCOEF1_G_TO_B_SHIFT 0 437 438 #define SCALER_OLEDCOEF2 0x0000008c 439 # define SCALER_OLEDCOEF2_R_TO_R_MASK VC4_MASK(29, 20) 440 # define SCALER_OLEDCOEF2_R_TO_R_SHIFT 20 441 # define SCALER_OLEDCOEF2_R_TO_G_MASK VC4_MASK(19, 10) 442 # define SCALER_OLEDCOEF2_R_TO_G_SHIFT 10 443 # define SCALER_OLEDCOEF2_R_TO_B_MASK VC4_MASK(9, 0) 444 # define SCALER_OLEDCOEF2_R_TO_B_SHIFT 0 445 446 /* Slave addresses for DMAing from HVS composition output to other 447 * devices. The top bits are valid only in !FIFO32 mode. 448 */ 449 #define SCALER_DISPSLAVE0 0x000000c0 450 #define SCALER_DISPSLAVE1 0x000000c9 451 #define SCALER_DISPSLAVE2 0x000000d0 452 # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31) 453 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30) 454 /* Set when the current line has been read and an HSTART is required. */ 455 # define SCALER_DISPSLAVE_EOL BIT(26) 456 /* Set when the display FIFO is empty. */ 457 # define SCALER_DISPSLAVE_EMPTY BIT(25) 458 /* Set when there is RGB data ready to read. */ 459 # define SCALER_DISPSLAVE_VALID BIT(24) 460 # define SCALER_DISPSLAVE_RGB_MASK VC4_MASK(23, 0) 461 # define SCALER_DISPSLAVE_RGB_SHIFT 0 462 463 #define SCALER_GAMDATA 0x000000e0 464 #define SCALER_DLIST_START 0x00002000 465 #define SCALER_DLIST_SIZE 0x00004000 466 467 #define VC4_HDMI_CORE_REV 0x000 468 469 #define VC4_HDMI_SW_RESET_CONTROL 0x004 470 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1) 471 # define VC4_HDMI_SW_RESET_HDMI BIT(0) 472 473 #define VC4_HDMI_HOTPLUG_INT 0x008 474 475 #define VC4_HDMI_HOTPLUG 0x00c 476 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0) 477 478 /* 3 bits per field, where each field maps from that corresponding MAI 479 * bus channel to the given HDMI channel. 480 */ 481 #define VC4_HDMI_MAI_CHANNEL_MAP 0x090 482 483 #define VC4_HDMI_MAI_CONFIG 0x094 484 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27) 485 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26) 486 # define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0) 487 # define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0 488 489 /* Last received format word on the MAI bus. */ 490 #define VC4_HDMI_MAI_FORMAT 0x098 491 492 #define VC4_HDMI_AUDIO_PACKET_CONFIG 0x09c 493 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29) 494 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24) 495 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19) 496 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18) 497 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10) 498 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10 499 /* If set, then multichannel, otherwise 2 channel. */ 500 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9) 501 /* If set, then AUDIO_LAYOUT overrides audio_cea_mask */ 502 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8) 503 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0) 504 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0 505 506 #define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0 507 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16) 508 509 #define VC4_HDMI_RAM_PACKET_STATUS 0x0a4 510 511 #define VC4_HDMI_CRP_CFG 0x0a8 512 /* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead 513 * of pixel clock. 514 */ 515 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26) 516 /* When set, no CRP packets will be sent. */ 517 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25) 518 /* If set, generates CTS values based on N, audio clock, and video 519 * clock. N must be divisible by 128. 520 */ 521 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24) 522 # define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0) 523 # define VC4_HDMI_CRP_CFG_N_SHIFT 0 524 525 /* 20-bit fields containing CTS values to be transmitted if !EXTERNAL_CTS_EN */ 526 #define VC4_HDMI_CTS_0 0x0ac 527 #define VC4_HDMI_CTS_1 0x0b0 528 /* 20-bit fields containing number of clocks to send CTS0/1 before 529 * switching to the other one. 530 */ 531 #define VC4_HDMI_CTS_PERIOD_0 0x0b4 532 #define VC4_HDMI_CTS_PERIOD_1 0x0b8 533 534 #define VC4_HDMI_HORZA 0x0c4 535 # define VC4_HDMI_HORZA_VPOS BIT(14) 536 # define VC4_HDMI_HORZA_HPOS BIT(13) 537 /* Horizontal active pixels (hdisplay). */ 538 # define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0) 539 # define VC4_HDMI_HORZA_HAP_SHIFT 0 540 541 #define VC4_HDMI_HORZB 0x0c8 542 /* Horizontal pack porch (htotal - hsync_end). */ 543 # define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20) 544 # define VC4_HDMI_HORZB_HBP_SHIFT 20 545 /* Horizontal sync pulse (hsync_end - hsync_start). */ 546 # define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10) 547 # define VC4_HDMI_HORZB_HSP_SHIFT 10 548 /* Horizontal front porch (hsync_start - hdisplay). */ 549 # define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0) 550 # define VC4_HDMI_HORZB_HFP_SHIFT 0 551 552 #define VC4_HDMI_FIFO_CTL 0x05c 553 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14) 554 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13) 555 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7) 556 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6) 557 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5) 558 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4) 559 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3) 560 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2) 561 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1) 562 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0) 563 # define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff 564 565 #define VC4_HDMI_SCHEDULER_CONTROL 0x0c0 566 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15) 567 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5) 568 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3) 569 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1) 570 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0) 571 572 #define VC4_HDMI_VERTA0 0x0cc 573 #define VC4_HDMI_VERTA1 0x0d4 574 /* Vertical sync pulse (vsync_end - vsync_start). */ 575 # define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20) 576 # define VC4_HDMI_VERTA_VSP_SHIFT 20 577 /* Vertical front porch (vsync_start - vdisplay). */ 578 # define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13) 579 # define VC4_HDMI_VERTA_VFP_SHIFT 13 580 /* Vertical active lines (vdisplay). */ 581 # define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 582 # define VC4_HDMI_VERTA_VAL_SHIFT 0 583 584 #define VC4_HDMI_VERTB0 0x0d0 585 #define VC4_HDMI_VERTB1 0x0d8 586 /* Vertical sync pulse offset (for interlaced) */ 587 # define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9) 588 # define VC4_HDMI_VERTB_VSPO_SHIFT 9 589 /* Vertical pack porch (vtotal - vsync_end). */ 590 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0) 591 # define VC4_HDMI_VERTB_VBP_SHIFT 0 592 593 #define VC4_HDMI_CEC_CNTRL_1 0x0e8 594 /* Set when the transmission has ended. */ 595 # define VC4_HDMI_CEC_TX_EOM BIT(31) 596 /* If set, transmission was acked on the 1st or 2nd attempt (only one 597 * retry is attempted). If in continuous mode, this means TX needs to 598 * be filled if !TX_EOM. 599 */ 600 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30) 601 # define VC4_HDMI_CEC_RX_EOM BIT(29) 602 # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28) 603 /* Number of bytes received for the message. */ 604 # define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24) 605 # define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24 606 /* Sets continuous receive mode. Generates interrupt after each 8 607 * bytes to signal that RX_DATA should be consumed, and at RX_EOM. 608 * 609 * If disabled, maximum 16 bytes will be received (including header), 610 * and interrupt at RX_EOM. Later bytes will be acked but not put 611 * into the RX_DATA. 612 */ 613 # define VC4_HDMI_CEC_RX_CONTINUE BIT(23) 614 # define VC4_HDMI_CEC_TX_CONTINUE BIT(22) 615 /* Set this after a CEC interrupt. */ 616 # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21) 617 /* Starts a TX. Will wait for appropriate idel time before CEC 618 * activity. Must be cleared in between transmits. 619 */ 620 # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20) 621 # define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16) 622 # define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16 623 /* Device's CEC address */ 624 # define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12) 625 # define VC4_HDMI_CEC_ADDR_SHIFT 12 626 /* Divides off of HSM clock to generate CEC bit clock. */ 627 /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */ 628 # define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0) 629 # define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0 630 631 /* Set these fields to how many bit clock cycles get to that many 632 * microseconds. 633 */ 634 #define VC4_HDMI_CEC_CNTRL_2 0x0ec 635 # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24) 636 # define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24 637 # define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17) 638 # define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17 639 # define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11) 640 # define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11 641 # define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5) 642 # define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5 643 # define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0) 644 # define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0 645 646 #define VC4_HDMI_CEC_CNTRL_3 0x0f0 647 # define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24) 648 # define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24 649 # define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16) 650 # define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16 651 # define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8) 652 # define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8 653 # define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0) 654 # define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0 655 656 #define VC4_HDMI_CEC_CNTRL_4 0x0f4 657 # define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24) 658 # define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24 659 # define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16) 660 # define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16 661 # define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8) 662 # define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8 663 # define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0) 664 # define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0 665 666 #define VC4_HDMI_CEC_CNTRL_5 0x0f8 667 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27) 668 # define VC4_HDMI_CEC_RX_SW_RESET BIT(26) 669 # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25) 670 # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24) 671 # define VC4_HDMI_CEC_RX_CEC_INT BIT(23) 672 # define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16) 673 # define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16 674 # define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8) 675 # define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8 676 # define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0) 677 # define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0 678 679 /* Transmit data, first byte is low byte of the 32-bit reg. MSB of 680 * each byte transmitted first. 681 */ 682 #define VC4_HDMI_CEC_TX_DATA_1 0x0fc 683 #define VC4_HDMI_CEC_TX_DATA_2 0x100 684 #define VC4_HDMI_CEC_TX_DATA_3 0x104 685 #define VC4_HDMI_CEC_TX_DATA_4 0x108 686 #define VC4_HDMI_CEC_RX_DATA_1 0x10c 687 #define VC4_HDMI_CEC_RX_DATA_2 0x110 688 #define VC4_HDMI_CEC_RX_DATA_3 0x114 689 #define VC4_HDMI_CEC_RX_DATA_4 0x118 690 691 #define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0 692 693 #define VC4_HDMI_TX_PHY_CTL0 0x2c4 694 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25) 695 696 /* Interrupt status bits */ 697 #define VC4_HDMI_CPU_STATUS 0x340 698 #define VC4_HDMI_CPU_SET 0x344 699 #define VC4_HDMI_CPU_CLEAR 0x348 700 # define VC4_HDMI_CPU_CEC BIT(6) 701 # define VC4_HDMI_CPU_HOTPLUG BIT(0) 702 703 #define VC4_HDMI_CPU_MASK_STATUS 0x34c 704 #define VC4_HDMI_CPU_MASK_SET 0x350 705 #define VC4_HDMI_CPU_MASK_CLEAR 0x354 706 707 #define VC4_HDMI_GCP(x) (0x400 + ((x) * 0x4)) 708 #define VC4_HDMI_RAM_PACKET(x) (0x400 + ((x) * 0x24)) 709 #define VC4_HDMI_PACKET_STRIDE 0x24 710 711 #define VC4_HD_M_CTL 0x00c 712 /* Debug: Current receive value on the CEC pad. */ 713 # define VC4_HD_CECRXD BIT(9) 714 /* Debug: Override CEC output to 0. */ 715 # define VC4_HD_CECOVR BIT(8) 716 # define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6) 717 # define VC4_HD_M_RAM_STANDBY (3 << 4) 718 # define VC4_HD_M_SW_RST BIT(2) 719 # define VC4_HD_M_ENABLE BIT(0) 720 721 #define VC4_HD_MAI_CTL 0x014 722 /* Set when audio stream is received at a slower rate than the 723 * sampling period, so MAI fifo goes empty. Write 1 to clear. 724 */ 725 # define VC4_HD_MAI_CTL_DLATE BIT(15) 726 # define VC4_HD_MAI_CTL_BUSY BIT(14) 727 # define VC4_HD_MAI_CTL_CHALIGN BIT(13) 728 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12) 729 # define VC4_HD_MAI_CTL_FULL BIT(11) 730 # define VC4_HD_MAI_CTL_EMPTY BIT(10) 731 # define VC4_HD_MAI_CTL_FLUSH BIT(9) 732 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing 733 * through. 734 */ 735 # define VC4_HD_MAI_CTL_PAREN BIT(8) 736 # define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4) 737 # define VC4_HD_MAI_CTL_CHNUM_SHIFT 4 738 # define VC4_HD_MAI_CTL_ENABLE BIT(3) 739 /* Underflow error status bit, write 1 to clear. */ 740 # define VC4_HD_MAI_CTL_ERRORE BIT(2) 741 /* Overflow error status bit, write 1 to clear. */ 742 # define VC4_HD_MAI_CTL_ERRORF BIT(1) 743 /* Single-shot reset bit. Read value is undefined. */ 744 # define VC4_HD_MAI_CTL_RESET BIT(0) 745 746 #define VC4_HD_MAI_THR 0x018 747 # define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24) 748 # define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24 749 # define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16) 750 # define VC4_HD_MAI_THR_PANICLOW_SHIFT 16 751 # define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8) 752 # define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8 753 # define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0) 754 # define VC4_HD_MAI_THR_DREQLOW_SHIFT 0 755 756 /* Format header to be placed on the MAI data. Unused. */ 757 #define VC4_HD_MAI_FMT 0x01c 758 759 /* Register for DMAing in audio data to be transported over the MAI 760 * bus to the Falcon core. 761 */ 762 #define VC4_HD_MAI_DATA 0x020 763 764 /* Divider from HDMI HSM clock to MAI serial clock. Sampling period 765 * converges to N / (M + 1) cycles. 766 */ 767 #define VC4_HD_MAI_SMP 0x02c 768 # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8) 769 # define VC4_HD_MAI_SMP_N_SHIFT 8 770 # define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0) 771 # define VC4_HD_MAI_SMP_M_SHIFT 0 772 773 #define VC4_HD_VID_CTL 0x038 774 # define VC4_HD_VID_CTL_ENABLE BIT(31) 775 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30) 776 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29) 777 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28) 778 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27) 779 780 #define VC4_HD_CSC_CTL 0x040 781 # define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5) 782 # define VC4_HD_CSC_CTL_ORDER_SHIFT 5 783 # define VC4_HD_CSC_CTL_ORDER_RGB 0 784 # define VC4_HD_CSC_CTL_ORDER_BGR 1 785 # define VC4_HD_CSC_CTL_ORDER_BRG 2 786 # define VC4_HD_CSC_CTL_ORDER_GRB 3 787 # define VC4_HD_CSC_CTL_ORDER_GBR 4 788 # define VC4_HD_CSC_CTL_ORDER_RBG 5 789 # define VC4_HD_CSC_CTL_PADMSB BIT(4) 790 # define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2) 791 # define VC4_HD_CSC_CTL_MODE_SHIFT 2 792 # define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0 793 # define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1 794 # define VC4_HD_CSC_CTL_MODE_CUSTOM 3 795 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1) 796 # define VC4_HD_CSC_CTL_ENABLE BIT(0) 797 798 #define VC4_HD_CSC_12_11 0x044 799 #define VC4_HD_CSC_14_13 0x048 800 #define VC4_HD_CSC_22_21 0x04c 801 #define VC4_HD_CSC_24_23 0x050 802 #define VC4_HD_CSC_32_31 0x054 803 #define VC4_HD_CSC_34_33 0x058 804 805 #define VC4_HD_FRAME_COUNT 0x068 806 807 /* HVS display list information. */ 808 #define HVS_BOOTLOADER_DLIST_END 32 809 810 enum hvs_pixel_format { 811 /* 8bpp */ 812 HVS_PIXEL_FORMAT_RGB332 = 0, 813 /* 16bpp */ 814 HVS_PIXEL_FORMAT_RGBA4444 = 1, 815 HVS_PIXEL_FORMAT_RGB555 = 2, 816 HVS_PIXEL_FORMAT_RGBA5551 = 3, 817 HVS_PIXEL_FORMAT_RGB565 = 4, 818 /* 24bpp */ 819 HVS_PIXEL_FORMAT_RGB888 = 5, 820 HVS_PIXEL_FORMAT_RGBA6666 = 6, 821 /* 32bpp */ 822 HVS_PIXEL_FORMAT_RGBA8888 = 7, 823 824 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8, 825 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9, 826 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10, 827 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11, 828 HVS_PIXEL_FORMAT_H264 = 12, 829 HVS_PIXEL_FORMAT_PALETTE = 13, 830 HVS_PIXEL_FORMAT_YUV444_RGB = 14, 831 HVS_PIXEL_FORMAT_AYUV444_RGB = 15, 832 }; 833 834 /* Note: the LSB is the rightmost character shown. Only valid for 835 * HVS_PIXEL_FORMAT_RGB8888, not RGB888. 836 */ 837 #define HVS_PIXEL_ORDER_RGBA 0 838 #define HVS_PIXEL_ORDER_BGRA 1 839 #define HVS_PIXEL_ORDER_ARGB 2 840 #define HVS_PIXEL_ORDER_ABGR 3 841 842 #define HVS_PIXEL_ORDER_XBRG 0 843 #define HVS_PIXEL_ORDER_XRBG 1 844 #define HVS_PIXEL_ORDER_XRGB 2 845 #define HVS_PIXEL_ORDER_XBGR 3 846 847 #define HVS_PIXEL_ORDER_XYCBCR 0 848 #define HVS_PIXEL_ORDER_XYCRCB 1 849 #define HVS_PIXEL_ORDER_YXCBCR 2 850 #define HVS_PIXEL_ORDER_YXCRCB 3 851 852 #define SCALER_CTL0_END BIT(31) 853 #define SCALER_CTL0_VALID BIT(30) 854 855 #define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24) 856 #define SCALER_CTL0_SIZE_SHIFT 24 857 858 #define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20) 859 #define SCALER_CTL0_TILING_SHIFT 20 860 #define SCALER_CTL0_TILING_LINEAR 0 861 #define SCALER_CTL0_TILING_64B 1 862 #define SCALER_CTL0_TILING_128B 2 863 #define SCALER_CTL0_TILING_256B_OR_T 3 864 865 #define SCALER_CTL0_ALPHA_MASK BIT(19) 866 #define SCALER_CTL0_HFLIP BIT(16) 867 #define SCALER_CTL0_VFLIP BIT(15) 868 869 #define SCALER_CTL0_KEY_MODE_MASK VC4_MASK(18, 17) 870 #define SCALER_CTL0_KEY_MODE_SHIFT 17 871 #define SCALER_CTL0_KEY_DISABLED 0 872 #define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB 1 873 #define SCALER_CTL0_KEY_MATCH 2 /* turn transparent */ 874 #define SCALER_CTL0_KEY_REPLACE 3 /* replace with value from key mask word 2 */ 875 876 #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13) 877 #define SCALER_CTL0_ORDER_SHIFT 13 878 879 #define SCALER_CTL0_RGBA_EXPAND_MASK VC4_MASK(12, 11) 880 #define SCALER_CTL0_RGBA_EXPAND_SHIFT 11 881 #define SCALER_CTL0_RGBA_EXPAND_ZERO 0 882 #define SCALER_CTL0_RGBA_EXPAND_LSB 1 883 #define SCALER_CTL0_RGBA_EXPAND_MSB 2 884 #define SCALER_CTL0_RGBA_EXPAND_ROUND 3 885 886 #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8) 887 #define SCALER_CTL0_SCL1_SHIFT 8 888 889 #define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5) 890 #define SCALER_CTL0_SCL0_SHIFT 5 891 892 #define SCALER_CTL0_SCL_H_PPF_V_PPF 0 893 #define SCALER_CTL0_SCL_H_TPZ_V_PPF 1 894 #define SCALER_CTL0_SCL_H_PPF_V_TPZ 2 895 #define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3 896 #define SCALER_CTL0_SCL_H_PPF_V_NONE 4 897 #define SCALER_CTL0_SCL_H_NONE_V_PPF 5 898 #define SCALER_CTL0_SCL_H_NONE_V_TPZ 6 899 #define SCALER_CTL0_SCL_H_TPZ_V_NONE 7 900 901 /* Set to indicate no scaling. */ 902 #define SCALER_CTL0_UNITY BIT(4) 903 904 #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0) 905 #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0 906 907 #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24) 908 #define SCALER_POS0_FIXED_ALPHA_SHIFT 24 909 910 #define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12) 911 #define SCALER_POS0_START_Y_SHIFT 12 912 913 #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0) 914 #define SCALER_POS0_START_X_SHIFT 0 915 916 #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16) 917 #define SCALER_POS1_SCL_HEIGHT_SHIFT 16 918 919 #define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0) 920 #define SCALER_POS1_SCL_WIDTH_SHIFT 0 921 922 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30) 923 #define SCALER_POS2_ALPHA_MODE_SHIFT 30 924 #define SCALER_POS2_ALPHA_MODE_PIPELINE 0 925 #define SCALER_POS2_ALPHA_MODE_FIXED 1 926 #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2 927 #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3 928 #define SCALER_POS2_ALPHA_PREMULT BIT(29) 929 #define SCALER_POS2_ALPHA_MIX BIT(28) 930 931 #define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16) 932 #define SCALER_POS2_HEIGHT_SHIFT 16 933 934 #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0) 935 #define SCALER_POS2_WIDTH_SHIFT 0 936 937 /* Color Space Conversion words. Some values are S2.8 signed 938 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1, 939 * 0x2: 2, 0x3: -1} 940 */ 941 /* bottom 8 bits of S2.8 contribution of Cr to Blue */ 942 #define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24) 943 #define SCALER_CSC0_COEF_CR_BLU_SHIFT 24 944 /* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */ 945 #define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16) 946 #define SCALER_CSC0_COEF_YY_OFS_SHIFT 16 947 /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */ 948 #define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8) 949 #define SCALER_CSC0_COEF_CB_OFS_SHIFT 8 950 /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */ 951 #define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0) 952 #define SCALER_CSC0_COEF_CR_OFS_SHIFT 0 953 #define SCALER_CSC0_ITR_R_601_5 0x00f00000 954 #define SCALER_CSC0_ITR_R_709_3 0x00f00000 955 #define SCALER_CSC0_JPEG_JFIF 0x00000000 956 957 /* S2.8 contribution of Cb to Green */ 958 #define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22) 959 #define SCALER_CSC1_COEF_CB_GRN_SHIFT 22 960 /* S2.8 contribution of Cr to Green */ 961 #define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12) 962 #define SCALER_CSC1_COEF_CR_GRN_SHIFT 12 963 /* S2.8 contribution of Y to all of RGB */ 964 #define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2) 965 #define SCALER_CSC1_COEF_YY_ALL_SHIFT 2 966 /* top 2 bits of S2.8 contribution of Cr to Blue */ 967 #define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0) 968 #define SCALER_CSC1_COEF_CR_BLU_SHIFT 0 969 #define SCALER_CSC1_ITR_R_601_5 0xe73304a8 970 #define SCALER_CSC1_ITR_R_709_3 0xf2b784a8 971 #define SCALER_CSC1_JPEG_JFIF 0xea34a400 972 973 /* S2.8 contribution of Cb to Red */ 974 #define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20) 975 #define SCALER_CSC2_COEF_CB_RED_SHIFT 20 976 /* S2.8 contribution of Cr to Red */ 977 #define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10) 978 #define SCALER_CSC2_COEF_CR_RED_SHIFT 10 979 /* S2.8 contribution of Cb to Blue */ 980 #define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10) 981 #define SCALER_CSC2_COEF_CB_BLU_SHIFT 10 982 #define SCALER_CSC2_ITR_R_601_5 0x00066204 983 #define SCALER_CSC2_ITR_R_709_3 0x00072a1c 984 #define SCALER_CSC2_JPEG_JFIF 0x000599c5 985 986 #define SCALER_TPZ0_VERT_RECALC BIT(31) 987 #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8) 988 #define SCALER_TPZ0_SCALE_SHIFT 8 989 #define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0) 990 #define SCALER_TPZ0_IPHASE_SHIFT 0 991 #define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0) 992 #define SCALER_TPZ1_RECIP_SHIFT 0 993 994 /* Skips interpolating coefficients to 64 phases, so just 8 are used. 995 * Required for nearest neighbor. 996 */ 997 #define SCALER_PPF_NOINTERP BIT(31) 998 /* Replaes the highest valued coefficient with one that makes all 4 999 * sum to unity. 1000 */ 1001 #define SCALER_PPF_AGC BIT(30) 1002 #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8) 1003 #define SCALER_PPF_SCALE_SHIFT 8 1004 #define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0) 1005 #define SCALER_PPF_IPHASE_SHIFT 0 1006 1007 #define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0) 1008 #define SCALER_PPF_KERNEL_OFFSET_SHIFT 0 1009 #define SCALER_PPF_KERNEL_UNCACHED BIT(31) 1010 1011 /* PITCH0/1/2 fields for raster. */ 1012 #define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0) 1013 #define SCALER_SRC_PITCH_SHIFT 0 1014 1015 /* PITCH0/1/2 fields for tiled (SAND). */ 1016 #define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16) 1017 #define SCALER_TILE_SKIP_0_SHIFT 16 1018 #define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0) 1019 #define SCALER_TILE_HEIGHT_SHIFT 0 1020 1021 /* Common PITCH0 fields */ 1022 #define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26) 1023 #define SCALER_PITCH0_SINK_PIX_SHIFT 26 1024 1025 /* PITCH0 fields for T-tiled. */ 1026 #define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16) 1027 #define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16 1028 #define SCALER_PITCH0_TILE_LINE_DIR BIT(15) 1029 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14) 1030 /* Y offset within a tile. */ 1031 #define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8) 1032 #define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8 1033 #define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0) 1034 #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0 1035 1036 #endif /* VC4_REGS_H */ 1037