1 /* 2 * Copyright © 2014-2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef VC4_REGS_H 10 #define VC4_REGS_H 11 12 #include <linux/bitops.h> 13 14 #define VC4_MASK(high, low) ((u32)GENMASK(high, low)) 15 /* Using the GNU statement expression extension */ 16 #define VC4_SET_FIELD(value, field) \ 17 ({ \ 18 uint32_t fieldval = (value) << field##_SHIFT; \ 19 WARN_ON((fieldval & ~field##_MASK) != 0); \ 20 fieldval & field##_MASK; \ 21 }) 22 23 #define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >> \ 24 field##_SHIFT) 25 26 #define V3D_IDENT0 0x00000 27 # define V3D_EXPECTED_IDENT0 \ 28 ((2 << 24) | \ 29 ('V' << 0) | \ 30 ('3' << 8) | \ 31 ('D' << 16)) 32 33 #define V3D_IDENT1 0x00004 34 /* Multiples of 1kb */ 35 # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28) 36 # define V3D_IDENT1_VPM_SIZE_SHIFT 28 37 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16) 38 # define V3D_IDENT1_NSEM_SHIFT 16 39 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12) 40 # define V3D_IDENT1_TUPS_SHIFT 12 41 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8) 42 # define V3D_IDENT1_QUPS_SHIFT 8 43 # define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4) 44 # define V3D_IDENT1_NSLC_SHIFT 4 45 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0) 46 # define V3D_IDENT1_REV_SHIFT 0 47 48 #define V3D_IDENT2 0x00008 49 #define V3D_SCRATCH 0x00010 50 #define V3D_L2CACTL 0x00020 51 # define V3D_L2CACTL_L2CCLR BIT(2) 52 # define V3D_L2CACTL_L2CDIS BIT(1) 53 # define V3D_L2CACTL_L2CENA BIT(0) 54 55 #define V3D_SLCACTL 0x00024 56 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24) 57 # define V3D_SLCACTL_T1CC_SHIFT 24 58 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16) 59 # define V3D_SLCACTL_T0CC_SHIFT 16 60 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8) 61 # define V3D_SLCACTL_UCC_SHIFT 8 62 # define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0) 63 # define V3D_SLCACTL_ICC_SHIFT 0 64 65 #define V3D_INTCTL 0x00030 66 #define V3D_INTENA 0x00034 67 #define V3D_INTDIS 0x00038 68 # define V3D_INT_SPILLUSE BIT(3) 69 # define V3D_INT_OUTOMEM BIT(2) 70 # define V3D_INT_FLDONE BIT(1) 71 # define V3D_INT_FRDONE BIT(0) 72 73 #define V3D_CT0CS 0x00100 74 #define V3D_CT1CS 0x00104 75 #define V3D_CTNCS(n) (V3D_CT0CS + 4 * n) 76 # define V3D_CTRSTA BIT(15) 77 # define V3D_CTSEMA BIT(12) 78 # define V3D_CTRTSD BIT(8) 79 # define V3D_CTRUN BIT(5) 80 # define V3D_CTSUBS BIT(4) 81 # define V3D_CTERR BIT(3) 82 # define V3D_CTMODE BIT(0) 83 84 #define V3D_CT0EA 0x00108 85 #define V3D_CT1EA 0x0010c 86 #define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n)) 87 #define V3D_CT0CA 0x00110 88 #define V3D_CT1CA 0x00114 89 #define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n)) 90 #define V3D_CT00RA0 0x00118 91 #define V3D_CT01RA0 0x0011c 92 #define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n)) 93 #define V3D_CT0LC 0x00120 94 #define V3D_CT1LC 0x00124 95 #define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n)) 96 #define V3D_CT0PC 0x00128 97 #define V3D_CT1PC 0x0012c 98 #define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n)) 99 100 #define V3D_PCS 0x00130 101 # define V3D_BMOOM BIT(8) 102 # define V3D_RMBUSY BIT(3) 103 # define V3D_RMACTIVE BIT(2) 104 # define V3D_BMBUSY BIT(1) 105 # define V3D_BMACTIVE BIT(0) 106 107 #define V3D_BFC 0x00134 108 #define V3D_RFC 0x00138 109 #define V3D_BPCA 0x00300 110 #define V3D_BPCS 0x00304 111 #define V3D_BPOA 0x00308 112 #define V3D_BPOS 0x0030c 113 #define V3D_BXCF 0x00310 114 #define V3D_SQRSV0 0x00410 115 #define V3D_SQRSV1 0x00414 116 #define V3D_SQCNTL 0x00418 117 #define V3D_SRQPC 0x00430 118 #define V3D_SRQUA 0x00434 119 #define V3D_SRQUL 0x00438 120 #define V3D_SRQCS 0x0043c 121 #define V3D_VPACNTL 0x00500 122 #define V3D_VPMBASE 0x00504 123 #define V3D_PCTRC 0x00670 124 #define V3D_PCTRE 0x00674 125 #define V3D_PCTR0 0x00680 126 #define V3D_PCTRS0 0x00684 127 #define V3D_PCTR1 0x00688 128 #define V3D_PCTRS1 0x0068c 129 #define V3D_PCTR2 0x00690 130 #define V3D_PCTRS2 0x00694 131 #define V3D_PCTR3 0x00698 132 #define V3D_PCTRS3 0x0069c 133 #define V3D_PCTR4 0x006a0 134 #define V3D_PCTRS4 0x006a4 135 #define V3D_PCTR5 0x006a8 136 #define V3D_PCTRS5 0x006ac 137 #define V3D_PCTR6 0x006b0 138 #define V3D_PCTRS6 0x006b4 139 #define V3D_PCTR7 0x006b8 140 #define V3D_PCTRS7 0x006bc 141 #define V3D_PCTR8 0x006c0 142 #define V3D_PCTRS8 0x006c4 143 #define V3D_PCTR9 0x006c8 144 #define V3D_PCTRS9 0x006cc 145 #define V3D_PCTR10 0x006d0 146 #define V3D_PCTRS10 0x006d4 147 #define V3D_PCTR11 0x006d8 148 #define V3D_PCTRS11 0x006dc 149 #define V3D_PCTR12 0x006e0 150 #define V3D_PCTRS12 0x006e4 151 #define V3D_PCTR13 0x006e8 152 #define V3D_PCTRS13 0x006ec 153 #define V3D_PCTR14 0x006f0 154 #define V3D_PCTRS14 0x006f4 155 #define V3D_PCTR15 0x006f8 156 #define V3D_PCTRS15 0x006fc 157 #define V3D_DBGE 0x00f00 158 #define V3D_FDBGO 0x00f04 159 #define V3D_FDBGB 0x00f08 160 #define V3D_FDBGR 0x00f0c 161 #define V3D_FDBGS 0x00f10 162 #define V3D_ERRSTAT 0x00f20 163 164 #define PV_CONTROL 0x00 165 # define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21) 166 # define PV_CONTROL_FORMAT_SHIFT 21 167 # define PV_CONTROL_FORMAT_24 0 168 # define PV_CONTROL_FORMAT_DSIV_16 1 169 # define PV_CONTROL_FORMAT_DSIC_16 2 170 # define PV_CONTROL_FORMAT_DSIV_18 3 171 # define PV_CONTROL_FORMAT_DSIV_24 4 172 173 # define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15) 174 # define PV_CONTROL_FIFO_LEVEL_SHIFT 15 175 # define PV_CONTROL_CLR_AT_START BIT(14) 176 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13) 177 # define PV_CONTROL_WAIT_HSTART BIT(12) 178 # define PV_CONTROL_CLK_SELECT_DSI_VEC 0 179 # define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1 180 # define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2) 181 # define PV_CONTROL_CLK_SELECT_SHIFT 2 182 # define PV_CONTROL_FIFO_CLR BIT(1) 183 # define PV_CONTROL_EN BIT(0) 184 185 #define PV_V_CONTROL 0x04 186 # define PV_VCONTROL_INTERLACE BIT(4) 187 # define PV_VCONTROL_CONTINUOUS BIT(1) 188 # define PV_VCONTROL_VIDEN BIT(0) 189 190 #define PV_VSYNCD 0x08 191 192 #define PV_HORZA 0x0c 193 # define PV_HORZA_HBP_MASK VC4_MASK(31, 16) 194 # define PV_HORZA_HBP_SHIFT 16 195 # define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0) 196 # define PV_HORZA_HSYNC_SHIFT 0 197 198 #define PV_HORZB 0x10 199 # define PV_HORZB_HFP_MASK VC4_MASK(31, 16) 200 # define PV_HORZB_HFP_SHIFT 16 201 # define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0) 202 # define PV_HORZB_HACTIVE_SHIFT 0 203 204 #define PV_VERTA 0x14 205 # define PV_VERTA_VBP_MASK VC4_MASK(31, 16) 206 # define PV_VERTA_VBP_SHIFT 16 207 # define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0) 208 # define PV_VERTA_VSYNC_SHIFT 0 209 210 #define PV_VERTB 0x18 211 # define PV_VERTB_VFP_MASK VC4_MASK(31, 16) 212 # define PV_VERTB_VFP_SHIFT 16 213 # define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0) 214 # define PV_VERTB_VACTIVE_SHIFT 0 215 216 #define PV_VERTA_EVEN 0x1c 217 #define PV_VERTB_EVEN 0x20 218 219 #define PV_INTEN 0x24 220 #define PV_INTSTAT 0x28 221 # define PV_INT_VID_IDLE BIT(9) 222 # define PV_INT_VFP_END BIT(8) 223 # define PV_INT_VFP_START BIT(7) 224 # define PV_INT_VACT_START BIT(6) 225 # define PV_INT_VBP_START BIT(5) 226 # define PV_INT_VSYNC_START BIT(4) 227 # define PV_INT_HFP_START BIT(3) 228 # define PV_INT_HACT_START BIT(2) 229 # define PV_INT_HBP_START BIT(1) 230 # define PV_INT_HSYNC_START BIT(0) 231 232 #define PV_STAT 0x2c 233 234 #define PV_HACT_ACT 0x30 235 236 #define SCALER_DISPCTRL 0x00000000 237 /* Global register for clock gating the HVS */ 238 # define SCALER_DISPCTRL_ENABLE BIT(31) 239 # define SCALER_DISPCTRL_DSP2EISLUR BIT(15) 240 # define SCALER_DISPCTRL_DSP1EISLUR BIT(14) 241 /* Enables Display 0 short line and underrun contribution to 242 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are 243 * always enabled. 244 */ 245 # define SCALER_DISPCTRL_DSP0EISLUR BIT(13) 246 # define SCALER_DISPCTRL_DSP2EIEOLN BIT(12) 247 # define SCALER_DISPCTRL_DSP2EIEOF BIT(11) 248 # define SCALER_DISPCTRL_DSP1EIEOLN BIT(10) 249 # define SCALER_DISPCTRL_DSP1EIEOF BIT(9) 250 /* Enables Display 0 end-of-line-N contribution to 251 * SCALER_DISPSTAT_IRQDISP0 252 */ 253 # define SCALER_DISPCTRL_DSP0EIEOLN BIT(8) 254 /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */ 255 # define SCALER_DISPCTRL_DSP0EIEOF BIT(7) 256 257 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) 258 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5) 259 # define SCALER_DISPCTRL_DMAEIRQ BIT(4) 260 # define SCALER_DISPCTRL_DISP2EIRQ BIT(3) 261 # define SCALER_DISPCTRL_DISP1EIRQ BIT(2) 262 /* Enables interrupt generation on the enabled EOF/EOLN/EISLUR 263 * bits and short frames.. 264 */ 265 # define SCALER_DISPCTRL_DISP0EIRQ BIT(1) 266 /* Enables interrupt generation on scaler profiler interrupt. */ 267 # define SCALER_DISPCTRL_SCLEIRQ BIT(0) 268 269 #define SCALER_DISPSTAT 0x00000004 270 # define SCALER_DISPSTAT_COBLOW2 BIT(29) 271 # define SCALER_DISPSTAT_EOLN2 BIT(28) 272 # define SCALER_DISPSTAT_ESFRAME2 BIT(27) 273 # define SCALER_DISPSTAT_ESLINE2 BIT(26) 274 # define SCALER_DISPSTAT_EUFLOW2 BIT(25) 275 # define SCALER_DISPSTAT_EOF2 BIT(24) 276 277 # define SCALER_DISPSTAT_COBLOW1 BIT(21) 278 # define SCALER_DISPSTAT_EOLN1 BIT(20) 279 # define SCALER_DISPSTAT_ESFRAME1 BIT(19) 280 # define SCALER_DISPSTAT_ESLINE1 BIT(18) 281 # define SCALER_DISPSTAT_EUFLOW1 BIT(17) 282 # define SCALER_DISPSTAT_EOF1 BIT(16) 283 284 # define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14) 285 # define SCALER_DISPSTAT_RESP_SHIFT 14 286 # define SCALER_DISPSTAT_RESP_OKAY 0 287 # define SCALER_DISPSTAT_RESP_EXOKAY 1 288 # define SCALER_DISPSTAT_RESP_SLVERR 2 289 # define SCALER_DISPSTAT_RESP_DECERR 3 290 291 # define SCALER_DISPSTAT_COBLOW0 BIT(13) 292 /* Set when the DISPEOLN line is done compositing. */ 293 # define SCALER_DISPSTAT_EOLN0 BIT(12) 294 /* Set when VSTART is seen but there are still pixels in the current 295 * output line. 296 */ 297 # define SCALER_DISPSTAT_ESFRAME0 BIT(11) 298 /* Set when HSTART is seen but there are still pixels in the current 299 * output line. 300 */ 301 # define SCALER_DISPSTAT_ESLINE0 BIT(10) 302 /* Set when the the downstream tries to read from the display FIFO 303 * while it's empty. 304 */ 305 # define SCALER_DISPSTAT_EUFLOW0 BIT(9) 306 /* Set when the display mode changes from RUN to EOF */ 307 # define SCALER_DISPSTAT_EOF0 BIT(8) 308 309 /* Set on AXI invalid DMA ID error. */ 310 # define SCALER_DISPSTAT_DMA_ERROR BIT(7) 311 /* Set on AXI slave read decode error */ 312 # define SCALER_DISPSTAT_IRQSLVRD BIT(6) 313 /* Set on AXI slave write decode error */ 314 # define SCALER_DISPSTAT_IRQSLVWR BIT(5) 315 /* Set when SCALER_DISPSTAT_DMA_ERROR is set, or 316 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY. 317 */ 318 # define SCALER_DISPSTAT_IRQDMA BIT(4) 319 # define SCALER_DISPSTAT_IRQDISP2 BIT(3) 320 # define SCALER_DISPSTAT_IRQDISP1 BIT(2) 321 /* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their 322 * corresponding interrupt bit is enabled in DISPCTRL. 323 */ 324 # define SCALER_DISPSTAT_IRQDISP0 BIT(1) 325 /* On read, the profiler interrupt. On write, clear *all* interrupt bits. */ 326 # define SCALER_DISPSTAT_IRQSCL BIT(0) 327 328 #define SCALER_DISPID 0x00000008 329 #define SCALER_DISPECTRL 0x0000000c 330 #define SCALER_DISPPROF 0x00000010 331 #define SCALER_DISPDITHER 0x00000014 332 #define SCALER_DISPEOLN 0x00000018 333 #define SCALER_DISPLIST0 0x00000020 334 #define SCALER_DISPLIST1 0x00000024 335 #define SCALER_DISPLIST2 0x00000028 336 #define SCALER_DISPLSTAT 0x0000002c 337 #define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \ 338 (x) * (SCALER_DISPLIST1 - \ 339 SCALER_DISPLIST0)) 340 341 #define SCALER_DISPLACT0 0x00000030 342 #define SCALER_DISPLACT1 0x00000034 343 #define SCALER_DISPLACT2 0x00000038 344 #define SCALER_DISPCTRL0 0x00000040 345 # define SCALER_DISPCTRLX_ENABLE BIT(31) 346 # define SCALER_DISPCTRLX_RESET BIT(30) 347 # define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12) 348 # define SCALER_DISPCTRLX_WIDTH_SHIFT 12 349 # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0) 350 # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0 351 352 #define SCALER_DISPBKGND0 0x00000044 353 #define SCALER_DISPSTAT0 0x00000048 354 #define SCALER_DISPBASE0 0x0000004c 355 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30) 356 # define SCALER_DISPSTATX_MODE_SHIFT 30 357 # define SCALER_DISPSTATX_MODE_DISABLED 0 358 # define SCALER_DISPSTATX_MODE_INIT 1 359 # define SCALER_DISPSTATX_MODE_RUN 2 360 # define SCALER_DISPSTATX_MODE_EOF 3 361 # define SCALER_DISPSTATX_FULL BIT(29) 362 # define SCALER_DISPSTATX_EMPTY BIT(28) 363 #define SCALER_DISPCTRL1 0x00000050 364 #define SCALER_DISPBKGND1 0x00000054 365 #define SCALER_DISPSTAT1 0x00000058 366 #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ 367 (x) * (SCALER_DISPSTAT1 - \ 368 SCALER_DISPSTAT0)) 369 #define SCALER_DISPBASE1 0x0000005c 370 #define SCALER_DISPCTRL2 0x00000060 371 #define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \ 372 (x) * (SCALER_DISPCTRL1 - \ 373 SCALER_DISPCTRL0)) 374 #define SCALER_DISPBKGND2 0x00000064 375 #define SCALER_DISPSTAT2 0x00000068 376 #define SCALER_DISPBASE2 0x0000006c 377 #define SCALER_DISPALPHA2 0x00000070 378 #define SCALER_GAMADDR 0x00000078 379 #define SCALER_GAMDATA 0x000000e0 380 #define SCALER_DLIST_START 0x00002000 381 #define SCALER_DLIST_SIZE 0x00004000 382 383 #define VC4_HDMI_CORE_REV 0x000 384 385 #define VC4_HDMI_SW_RESET_CONTROL 0x004 386 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1) 387 # define VC4_HDMI_SW_RESET_HDMI BIT(0) 388 389 #define VC4_HDMI_HOTPLUG_INT 0x008 390 391 #define VC4_HDMI_HOTPLUG 0x00c 392 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0) 393 394 #define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0 395 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16) 396 397 #define VC4_HDMI_HORZA 0x0c4 398 # define VC4_HDMI_HORZA_VPOS BIT(14) 399 # define VC4_HDMI_HORZA_HPOS BIT(13) 400 /* Horizontal active pixels (hdisplay). */ 401 # define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0) 402 # define VC4_HDMI_HORZA_HAP_SHIFT 0 403 404 #define VC4_HDMI_HORZB 0x0c8 405 /* Horizontal pack porch (htotal - hsync_end). */ 406 # define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20) 407 # define VC4_HDMI_HORZB_HBP_SHIFT 20 408 /* Horizontal sync pulse (hsync_end - hsync_start). */ 409 # define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10) 410 # define VC4_HDMI_HORZB_HSP_SHIFT 10 411 /* Horizontal front porch (hsync_start - hdisplay). */ 412 # define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0) 413 # define VC4_HDMI_HORZB_HFP_SHIFT 0 414 415 #define VC4_HDMI_FIFO_CTL 0x05c 416 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14) 417 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13) 418 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7) 419 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6) 420 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5) 421 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4) 422 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3) 423 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2) 424 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1) 425 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0) 426 # define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff 427 428 #define VC4_HDMI_SCHEDULER_CONTROL 0x0c0 429 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15) 430 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5) 431 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3) 432 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1) 433 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0) 434 435 #define VC4_HDMI_VERTA0 0x0cc 436 #define VC4_HDMI_VERTA1 0x0d4 437 /* Vertical sync pulse (vsync_end - vsync_start). */ 438 # define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20) 439 # define VC4_HDMI_VERTA_VSP_SHIFT 20 440 /* Vertical front porch (vsync_start - vdisplay). */ 441 # define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13) 442 # define VC4_HDMI_VERTA_VFP_SHIFT 13 443 /* Vertical active lines (vdisplay). */ 444 # define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 445 # define VC4_HDMI_VERTA_VAL_SHIFT 0 446 447 #define VC4_HDMI_VERTB0 0x0d0 448 #define VC4_HDMI_VERTB1 0x0d8 449 /* Vertical sync pulse offset (for interlaced) */ 450 # define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9) 451 # define VC4_HDMI_VERTB_VSPO_SHIFT 9 452 /* Vertical pack porch (vtotal - vsync_end). */ 453 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0) 454 # define VC4_HDMI_VERTB_VBP_SHIFT 0 455 456 #define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0 457 458 #define VC4_HD_M_CTL 0x00c 459 # define VC4_HD_M_SW_RST BIT(2) 460 # define VC4_HD_M_ENABLE BIT(0) 461 462 #define VC4_HD_MAI_CTL 0x014 463 464 #define VC4_HD_VID_CTL 0x038 465 # define VC4_HD_VID_CTL_ENABLE BIT(31) 466 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30) 467 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29) 468 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28) 469 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27) 470 471 #define VC4_HD_CSC_CTL 0x040 472 # define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5) 473 # define VC4_HD_CSC_CTL_ORDER_SHIFT 5 474 # define VC4_HD_CSC_CTL_ORDER_RGB 0 475 # define VC4_HD_CSC_CTL_ORDER_BGR 1 476 # define VC4_HD_CSC_CTL_ORDER_BRG 2 477 # define VC4_HD_CSC_CTL_ORDER_GRB 3 478 # define VC4_HD_CSC_CTL_ORDER_GBR 4 479 # define VC4_HD_CSC_CTL_ORDER_RBG 5 480 # define VC4_HD_CSC_CTL_PADMSB BIT(4) 481 # define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2) 482 # define VC4_HD_CSC_CTL_MODE_SHIFT 2 483 # define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0 484 # define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1 485 # define VC4_HD_CSC_CTL_MODE_CUSTOM 2 486 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1) 487 # define VC4_HD_CSC_CTL_ENABLE BIT(0) 488 489 #define VC4_HD_FRAME_COUNT 0x068 490 491 /* HVS display list information. */ 492 #define HVS_BOOTLOADER_DLIST_END 32 493 494 enum hvs_pixel_format { 495 /* 8bpp */ 496 HVS_PIXEL_FORMAT_RGB332 = 0, 497 /* 16bpp */ 498 HVS_PIXEL_FORMAT_RGBA4444 = 1, 499 HVS_PIXEL_FORMAT_RGB555 = 2, 500 HVS_PIXEL_FORMAT_RGBA5551 = 3, 501 HVS_PIXEL_FORMAT_RGB565 = 4, 502 /* 24bpp */ 503 HVS_PIXEL_FORMAT_RGB888 = 5, 504 HVS_PIXEL_FORMAT_RGBA6666 = 6, 505 /* 32bpp */ 506 HVS_PIXEL_FORMAT_RGBA8888 = 7 507 }; 508 509 /* Note: the LSB is the rightmost character shown. Only valid for 510 * HVS_PIXEL_FORMAT_RGB8888, not RGB888. 511 */ 512 #define HVS_PIXEL_ORDER_RGBA 0 513 #define HVS_PIXEL_ORDER_BGRA 1 514 #define HVS_PIXEL_ORDER_ARGB 2 515 #define HVS_PIXEL_ORDER_ABGR 3 516 517 #define HVS_PIXEL_ORDER_XBRG 0 518 #define HVS_PIXEL_ORDER_XRBG 1 519 #define HVS_PIXEL_ORDER_XRGB 2 520 #define HVS_PIXEL_ORDER_XBGR 3 521 522 #define HVS_PIXEL_ORDER_XYCBCR 0 523 #define HVS_PIXEL_ORDER_XYCRCB 1 524 #define HVS_PIXEL_ORDER_YXCBCR 2 525 #define HVS_PIXEL_ORDER_YXCRCB 3 526 527 #define SCALER_CTL0_END BIT(31) 528 #define SCALER_CTL0_VALID BIT(30) 529 530 #define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24) 531 #define SCALER_CTL0_SIZE_SHIFT 24 532 533 #define SCALER_CTL0_HFLIP BIT(16) 534 #define SCALER_CTL0_VFLIP BIT(15) 535 536 #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13) 537 #define SCALER_CTL0_ORDER_SHIFT 13 538 539 /* Set to indicate no scaling. */ 540 #define SCALER_CTL0_UNITY BIT(4) 541 542 #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0) 543 #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0 544 545 #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24) 546 #define SCALER_POS0_FIXED_ALPHA_SHIFT 24 547 548 #define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12) 549 #define SCALER_POS0_START_Y_SHIFT 12 550 551 #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0) 552 #define SCALER_POS0_START_X_SHIFT 0 553 554 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30) 555 #define SCALER_POS2_ALPHA_MODE_SHIFT 30 556 #define SCALER_POS2_ALPHA_MODE_PIPELINE 0 557 #define SCALER_POS2_ALPHA_MODE_FIXED 1 558 #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2 559 #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3 560 561 #define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16) 562 #define SCALER_POS2_HEIGHT_SHIFT 16 563 564 #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0) 565 #define SCALER_POS2_WIDTH_SHIFT 0 566 567 #define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0) 568 #define SCALER_SRC_PITCH_SHIFT 0 569 570 #endif /* VC4_REGS_H */ 571