1 /* 2 * Copyright © 2014-2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef VC4_REGS_H 10 #define VC4_REGS_H 11 12 #include <linux/bitops.h> 13 14 #define VC4_MASK(high, low) ((u32)GENMASK(high, low)) 15 /* Using the GNU statement expression extension */ 16 #define VC4_SET_FIELD(value, field) \ 17 ({ \ 18 uint32_t fieldval = (value) << field##_SHIFT; \ 19 WARN_ON((fieldval & ~field##_MASK) != 0); \ 20 fieldval & field##_MASK; \ 21 }) 22 23 #define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >> \ 24 field##_SHIFT) 25 26 #define V3D_IDENT0 0x00000 27 # define V3D_EXPECTED_IDENT0 \ 28 ((2 << 24) | \ 29 ('V' << 0) | \ 30 ('3' << 8) | \ 31 ('D' << 16)) 32 33 #define V3D_IDENT1 0x00004 34 /* Multiples of 1kb */ 35 # define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28) 36 # define V3D_IDENT1_VPM_SIZE_SHIFT 28 37 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16) 38 # define V3D_IDENT1_NSEM_SHIFT 16 39 # define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12) 40 # define V3D_IDENT1_TUPS_SHIFT 12 41 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8) 42 # define V3D_IDENT1_QUPS_SHIFT 8 43 # define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4) 44 # define V3D_IDENT1_NSLC_SHIFT 4 45 # define V3D_IDENT1_REV_MASK VC4_MASK(3, 0) 46 # define V3D_IDENT1_REV_SHIFT 0 47 48 #define V3D_IDENT2 0x00008 49 #define V3D_SCRATCH 0x00010 50 #define V3D_L2CACTL 0x00020 51 # define V3D_L2CACTL_L2CCLR BIT(2) 52 # define V3D_L2CACTL_L2CDIS BIT(1) 53 # define V3D_L2CACTL_L2CENA BIT(0) 54 55 #define V3D_SLCACTL 0x00024 56 # define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24) 57 # define V3D_SLCACTL_T1CC_SHIFT 24 58 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16) 59 # define V3D_SLCACTL_T0CC_SHIFT 16 60 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8) 61 # define V3D_SLCACTL_UCC_SHIFT 8 62 # define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0) 63 # define V3D_SLCACTL_ICC_SHIFT 0 64 65 #define V3D_INTCTL 0x00030 66 #define V3D_INTENA 0x00034 67 #define V3D_INTDIS 0x00038 68 # define V3D_INT_SPILLUSE BIT(3) 69 # define V3D_INT_OUTOMEM BIT(2) 70 # define V3D_INT_FLDONE BIT(1) 71 # define V3D_INT_FRDONE BIT(0) 72 73 #define V3D_CT0CS 0x00100 74 #define V3D_CT1CS 0x00104 75 #define V3D_CTNCS(n) (V3D_CT0CS + 4 * n) 76 # define V3D_CTRSTA BIT(15) 77 # define V3D_CTSEMA BIT(12) 78 # define V3D_CTRTSD BIT(8) 79 # define V3D_CTRUN BIT(5) 80 # define V3D_CTSUBS BIT(4) 81 # define V3D_CTERR BIT(3) 82 # define V3D_CTMODE BIT(0) 83 84 #define V3D_CT0EA 0x00108 85 #define V3D_CT1EA 0x0010c 86 #define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n)) 87 #define V3D_CT0CA 0x00110 88 #define V3D_CT1CA 0x00114 89 #define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n)) 90 #define V3D_CT00RA0 0x00118 91 #define V3D_CT01RA0 0x0011c 92 #define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n)) 93 #define V3D_CT0LC 0x00120 94 #define V3D_CT1LC 0x00124 95 #define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n)) 96 #define V3D_CT0PC 0x00128 97 #define V3D_CT1PC 0x0012c 98 #define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n)) 99 100 #define V3D_PCS 0x00130 101 # define V3D_BMOOM BIT(8) 102 # define V3D_RMBUSY BIT(3) 103 # define V3D_RMACTIVE BIT(2) 104 # define V3D_BMBUSY BIT(1) 105 # define V3D_BMACTIVE BIT(0) 106 107 #define V3D_BFC 0x00134 108 #define V3D_RFC 0x00138 109 #define V3D_BPCA 0x00300 110 #define V3D_BPCS 0x00304 111 #define V3D_BPOA 0x00308 112 #define V3D_BPOS 0x0030c 113 #define V3D_BXCF 0x00310 114 #define V3D_SQRSV0 0x00410 115 #define V3D_SQRSV1 0x00414 116 #define V3D_SQCNTL 0x00418 117 #define V3D_SRQPC 0x00430 118 #define V3D_SRQUA 0x00434 119 #define V3D_SRQUL 0x00438 120 #define V3D_SRQCS 0x0043c 121 #define V3D_VPACNTL 0x00500 122 #define V3D_VPMBASE 0x00504 123 #define V3D_PCTRC 0x00670 124 #define V3D_PCTRE 0x00674 125 # define V3D_PCTRE_EN BIT(31) 126 #define V3D_PCTR(x) (0x00680 + ((x) * 8)) 127 #define V3D_PCTRS(x) (0x00684 + ((x) * 8)) 128 #define V3D_DBGE 0x00f00 129 #define V3D_FDBGO 0x00f04 130 #define V3D_FDBGB 0x00f08 131 #define V3D_FDBGR 0x00f0c 132 #define V3D_FDBGS 0x00f10 133 #define V3D_ERRSTAT 0x00f20 134 135 #define PV_CONTROL 0x00 136 # define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21) 137 # define PV_CONTROL_FORMAT_SHIFT 21 138 # define PV_CONTROL_FORMAT_24 0 139 # define PV_CONTROL_FORMAT_DSIV_16 1 140 # define PV_CONTROL_FORMAT_DSIC_16 2 141 # define PV_CONTROL_FORMAT_DSIV_18 3 142 # define PV_CONTROL_FORMAT_DSIV_24 4 143 144 # define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15) 145 # define PV_CONTROL_FIFO_LEVEL_SHIFT 15 146 # define PV_CONTROL_CLR_AT_START BIT(14) 147 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13) 148 # define PV_CONTROL_WAIT_HSTART BIT(12) 149 # define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4) 150 # define PV_CONTROL_PIXEL_REP_SHIFT 4 151 # define PV_CONTROL_CLK_SELECT_DSI 0 152 # define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1 153 # define PV_CONTROL_CLK_SELECT_VEC 2 154 # define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2) 155 # define PV_CONTROL_CLK_SELECT_SHIFT 2 156 # define PV_CONTROL_FIFO_CLR BIT(1) 157 # define PV_CONTROL_EN BIT(0) 158 159 #define PV_V_CONTROL 0x04 160 # define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6) 161 # define PV_VCONTROL_ODD_DELAY_SHIFT 6 162 # define PV_VCONTROL_ODD_FIRST BIT(5) 163 # define PV_VCONTROL_INTERLACE BIT(4) 164 # define PV_VCONTROL_DSI BIT(3) 165 # define PV_VCONTROL_COMMAND BIT(2) 166 # define PV_VCONTROL_CONTINUOUS BIT(1) 167 # define PV_VCONTROL_VIDEN BIT(0) 168 169 #define PV_VSYNCD_EVEN 0x08 170 171 #define PV_HORZA 0x0c 172 # define PV_HORZA_HBP_MASK VC4_MASK(31, 16) 173 # define PV_HORZA_HBP_SHIFT 16 174 # define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0) 175 # define PV_HORZA_HSYNC_SHIFT 0 176 177 #define PV_HORZB 0x10 178 # define PV_HORZB_HFP_MASK VC4_MASK(31, 16) 179 # define PV_HORZB_HFP_SHIFT 16 180 # define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0) 181 # define PV_HORZB_HACTIVE_SHIFT 0 182 183 #define PV_VERTA 0x14 184 # define PV_VERTA_VBP_MASK VC4_MASK(31, 16) 185 # define PV_VERTA_VBP_SHIFT 16 186 # define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0) 187 # define PV_VERTA_VSYNC_SHIFT 0 188 189 #define PV_VERTB 0x18 190 # define PV_VERTB_VFP_MASK VC4_MASK(31, 16) 191 # define PV_VERTB_VFP_SHIFT 16 192 # define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0) 193 # define PV_VERTB_VACTIVE_SHIFT 0 194 195 #define PV_VERTA_EVEN 0x1c 196 #define PV_VERTB_EVEN 0x20 197 198 #define PV_INTEN 0x24 199 #define PV_INTSTAT 0x28 200 # define PV_INT_VID_IDLE BIT(9) 201 # define PV_INT_VFP_END BIT(8) 202 # define PV_INT_VFP_START BIT(7) 203 # define PV_INT_VACT_START BIT(6) 204 # define PV_INT_VBP_START BIT(5) 205 # define PV_INT_VSYNC_START BIT(4) 206 # define PV_INT_HFP_START BIT(3) 207 # define PV_INT_HACT_START BIT(2) 208 # define PV_INT_HBP_START BIT(1) 209 # define PV_INT_HSYNC_START BIT(0) 210 211 #define PV_STAT 0x2c 212 213 #define PV_HACT_ACT 0x30 214 215 #define SCALER_DISPCTRL 0x00000000 216 /* Global register for clock gating the HVS */ 217 # define SCALER_DISPCTRL_ENABLE BIT(31) 218 # define SCALER_DISPCTRL_DSP2EISLUR BIT(15) 219 # define SCALER_DISPCTRL_DSP1EISLUR BIT(14) 220 # define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18) 221 # define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18 222 223 /* Enables Display 0 short line and underrun contribution to 224 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are 225 * always enabled. 226 */ 227 # define SCALER_DISPCTRL_DSP0EISLUR BIT(13) 228 # define SCALER_DISPCTRL_DSP2EIEOLN BIT(12) 229 # define SCALER_DISPCTRL_DSP2EIEOF BIT(11) 230 # define SCALER_DISPCTRL_DSP1EIEOLN BIT(10) 231 # define SCALER_DISPCTRL_DSP1EIEOF BIT(9) 232 /* Enables Display 0 end-of-line-N contribution to 233 * SCALER_DISPSTAT_IRQDISP0 234 */ 235 # define SCALER_DISPCTRL_DSP0EIEOLN BIT(8) 236 /* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */ 237 # define SCALER_DISPCTRL_DSP0EIEOF BIT(7) 238 239 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) 240 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5) 241 # define SCALER_DISPCTRL_DMAEIRQ BIT(4) 242 # define SCALER_DISPCTRL_DISP2EIRQ BIT(3) 243 # define SCALER_DISPCTRL_DISP1EIRQ BIT(2) 244 /* Enables interrupt generation on the enabled EOF/EOLN/EISLUR 245 * bits and short frames.. 246 */ 247 # define SCALER_DISPCTRL_DISP0EIRQ BIT(1) 248 /* Enables interrupt generation on scaler profiler interrupt. */ 249 # define SCALER_DISPCTRL_SCLEIRQ BIT(0) 250 251 #define SCALER_DISPSTAT 0x00000004 252 # define SCALER_DISPSTAT_COBLOW2 BIT(29) 253 # define SCALER_DISPSTAT_EOLN2 BIT(28) 254 # define SCALER_DISPSTAT_ESFRAME2 BIT(27) 255 # define SCALER_DISPSTAT_ESLINE2 BIT(26) 256 # define SCALER_DISPSTAT_EUFLOW2 BIT(25) 257 # define SCALER_DISPSTAT_EOF2 BIT(24) 258 259 # define SCALER_DISPSTAT_COBLOW1 BIT(21) 260 # define SCALER_DISPSTAT_EOLN1 BIT(20) 261 # define SCALER_DISPSTAT_ESFRAME1 BIT(19) 262 # define SCALER_DISPSTAT_ESLINE1 BIT(18) 263 # define SCALER_DISPSTAT_EUFLOW1 BIT(17) 264 # define SCALER_DISPSTAT_EOF1 BIT(16) 265 266 # define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14) 267 # define SCALER_DISPSTAT_RESP_SHIFT 14 268 # define SCALER_DISPSTAT_RESP_OKAY 0 269 # define SCALER_DISPSTAT_RESP_EXOKAY 1 270 # define SCALER_DISPSTAT_RESP_SLVERR 2 271 # define SCALER_DISPSTAT_RESP_DECERR 3 272 273 # define SCALER_DISPSTAT_COBLOW0 BIT(13) 274 /* Set when the DISPEOLN line is done compositing. */ 275 # define SCALER_DISPSTAT_EOLN0 BIT(12) 276 /* Set when VSTART is seen but there are still pixels in the current 277 * output line. 278 */ 279 # define SCALER_DISPSTAT_ESFRAME0 BIT(11) 280 /* Set when HSTART is seen but there are still pixels in the current 281 * output line. 282 */ 283 # define SCALER_DISPSTAT_ESLINE0 BIT(10) 284 /* Set when the the downstream tries to read from the display FIFO 285 * while it's empty. 286 */ 287 # define SCALER_DISPSTAT_EUFLOW0 BIT(9) 288 /* Set when the display mode changes from RUN to EOF */ 289 # define SCALER_DISPSTAT_EOF0 BIT(8) 290 291 /* Set on AXI invalid DMA ID error. */ 292 # define SCALER_DISPSTAT_DMA_ERROR BIT(7) 293 /* Set on AXI slave read decode error */ 294 # define SCALER_DISPSTAT_IRQSLVRD BIT(6) 295 /* Set on AXI slave write decode error */ 296 # define SCALER_DISPSTAT_IRQSLVWR BIT(5) 297 /* Set when SCALER_DISPSTAT_DMA_ERROR is set, or 298 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY. 299 */ 300 # define SCALER_DISPSTAT_IRQDMA BIT(4) 301 # define SCALER_DISPSTAT_IRQDISP2 BIT(3) 302 # define SCALER_DISPSTAT_IRQDISP1 BIT(2) 303 /* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their 304 * corresponding interrupt bit is enabled in DISPCTRL. 305 */ 306 # define SCALER_DISPSTAT_IRQDISP0 BIT(1) 307 /* On read, the profiler interrupt. On write, clear *all* interrupt bits. */ 308 # define SCALER_DISPSTAT_IRQSCL BIT(0) 309 310 #define SCALER_DISPID 0x00000008 311 #define SCALER_DISPECTRL 0x0000000c 312 #define SCALER_DISPPROF 0x00000010 313 #define SCALER_DISPDITHER 0x00000014 314 #define SCALER_DISPEOLN 0x00000018 315 #define SCALER_DISPLIST0 0x00000020 316 #define SCALER_DISPLIST1 0x00000024 317 #define SCALER_DISPLIST2 0x00000028 318 #define SCALER_DISPLSTAT 0x0000002c 319 #define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \ 320 (x) * (SCALER_DISPLIST1 - \ 321 SCALER_DISPLIST0)) 322 323 #define SCALER_DISPLACT0 0x00000030 324 #define SCALER_DISPLACT1 0x00000034 325 #define SCALER_DISPLACT2 0x00000038 326 #define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \ 327 (x) * (SCALER_DISPLACT1 - \ 328 SCALER_DISPLACT0)) 329 330 #define SCALER_DISPCTRL0 0x00000040 331 # define SCALER_DISPCTRLX_ENABLE BIT(31) 332 # define SCALER_DISPCTRLX_RESET BIT(30) 333 # define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12) 334 # define SCALER_DISPCTRLX_WIDTH_SHIFT 12 335 # define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0) 336 # define SCALER_DISPCTRLX_HEIGHT_SHIFT 0 337 338 #define SCALER_DISPBKGND0 0x00000044 339 # define SCALER_DISPBKGND_AUTOHS BIT(31) 340 # define SCALER_DISPBKGND_INTERLACE BIT(30) 341 # define SCALER_DISPBKGND_GAMMA BIT(29) 342 # define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25) 343 # define SCALER_DISPBKGND_TESTMODE_SHIFT 25 344 /* Enables filling the scaler line with the RGB value in the low 24 345 * bits before compositing. Costs cycles, so should be skipped if 346 * opaque display planes will cover everything. 347 */ 348 # define SCALER_DISPBKGND_FILL BIT(24) 349 350 #define SCALER_DISPSTAT0 0x00000048 351 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30) 352 # define SCALER_DISPSTATX_MODE_SHIFT 30 353 # define SCALER_DISPSTATX_MODE_DISABLED 0 354 # define SCALER_DISPSTATX_MODE_INIT 1 355 # define SCALER_DISPSTATX_MODE_RUN 2 356 # define SCALER_DISPSTATX_MODE_EOF 3 357 # define SCALER_DISPSTATX_FULL BIT(29) 358 # define SCALER_DISPSTATX_EMPTY BIT(28) 359 # define SCALER_DISPSTATX_FRAME_COUNT_MASK VC4_MASK(17, 12) 360 # define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12 361 # define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0) 362 # define SCALER_DISPSTATX_LINE_SHIFT 0 363 364 #define SCALER_DISPBASE0 0x0000004c 365 /* Last pixel in the COB (display FIFO memory) allocated to this HVS 366 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the 367 * next COB base). 368 */ 369 # define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16) 370 # define SCALER_DISPBASEX_TOP_SHIFT 16 371 /* First pixel in the COB (display FIFO memory) allocated to this HVS 372 * channel. Must be 4-pixel aligned. 373 */ 374 # define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0) 375 # define SCALER_DISPBASEX_BASE_SHIFT 0 376 377 #define SCALER_DISPCTRL1 0x00000050 378 #define SCALER_DISPBKGND1 0x00000054 379 #define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \ 380 (x) * (SCALER_DISPBKGND1 - \ 381 SCALER_DISPBKGND0)) 382 #define SCALER_DISPSTAT1 0x00000058 383 #define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \ 384 (x) * (SCALER_DISPSTAT1 - \ 385 SCALER_DISPSTAT0)) 386 #define SCALER_DISPBASE1 0x0000005c 387 #define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \ 388 (x) * (SCALER_DISPBASE1 - \ 389 SCALER_DISPBASE0)) 390 #define SCALER_DISPCTRL2 0x00000060 391 #define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \ 392 (x) * (SCALER_DISPCTRL1 - \ 393 SCALER_DISPCTRL0)) 394 #define SCALER_DISPBKGND2 0x00000064 395 #define SCALER_DISPSTAT2 0x00000068 396 #define SCALER_DISPBASE2 0x0000006c 397 #define SCALER_DISPALPHA2 0x00000070 398 #define SCALER_GAMADDR 0x00000078 399 # define SCALER_GAMADDR_AUTOINC BIT(31) 400 /* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma 401 * enabled. 402 */ 403 # define SCALER_GAMADDR_SRAMENB BIT(30) 404 405 #define SCALER_GAMDATA 0x000000e0 406 #define SCALER_DLIST_START 0x00002000 407 #define SCALER_DLIST_SIZE 0x00004000 408 409 #define VC4_HDMI_CORE_REV 0x000 410 411 #define VC4_HDMI_SW_RESET_CONTROL 0x004 412 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1) 413 # define VC4_HDMI_SW_RESET_HDMI BIT(0) 414 415 #define VC4_HDMI_HOTPLUG_INT 0x008 416 417 #define VC4_HDMI_HOTPLUG 0x00c 418 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0) 419 420 /* 3 bits per field, where each field maps from that corresponding MAI 421 * bus channel to the given HDMI channel. 422 */ 423 #define VC4_HDMI_MAI_CHANNEL_MAP 0x090 424 425 #define VC4_HDMI_MAI_CONFIG 0x094 426 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27) 427 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26) 428 # define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0) 429 # define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0 430 431 /* Last received format word on the MAI bus. */ 432 #define VC4_HDMI_MAI_FORMAT 0x098 433 434 #define VC4_HDMI_AUDIO_PACKET_CONFIG 0x09c 435 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29) 436 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24) 437 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19) 438 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18) 439 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10) 440 # define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10 441 /* If set, then multichannel, otherwise 2 channel. */ 442 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9) 443 /* If set, then AUDIO_LAYOUT overrides audio_cea_mask */ 444 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8) 445 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0) 446 # define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0 447 448 #define VC4_HDMI_RAM_PACKET_CONFIG 0x0a0 449 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16) 450 451 #define VC4_HDMI_RAM_PACKET_STATUS 0x0a4 452 453 #define VC4_HDMI_CRP_CFG 0x0a8 454 /* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead 455 * of pixel clock. 456 */ 457 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26) 458 /* When set, no CRP packets will be sent. */ 459 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25) 460 /* If set, generates CTS values based on N, audio clock, and video 461 * clock. N must be divisible by 128. 462 */ 463 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24) 464 # define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0) 465 # define VC4_HDMI_CRP_CFG_N_SHIFT 0 466 467 /* 20-bit fields containing CTS values to be transmitted if !EXTERNAL_CTS_EN */ 468 #define VC4_HDMI_CTS_0 0x0ac 469 #define VC4_HDMI_CTS_1 0x0b0 470 /* 20-bit fields containing number of clocks to send CTS0/1 before 471 * switching to the other one. 472 */ 473 #define VC4_HDMI_CTS_PERIOD_0 0x0b4 474 #define VC4_HDMI_CTS_PERIOD_1 0x0b8 475 476 #define VC4_HDMI_HORZA 0x0c4 477 # define VC4_HDMI_HORZA_VPOS BIT(14) 478 # define VC4_HDMI_HORZA_HPOS BIT(13) 479 /* Horizontal active pixels (hdisplay). */ 480 # define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0) 481 # define VC4_HDMI_HORZA_HAP_SHIFT 0 482 483 #define VC4_HDMI_HORZB 0x0c8 484 /* Horizontal pack porch (htotal - hsync_end). */ 485 # define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20) 486 # define VC4_HDMI_HORZB_HBP_SHIFT 20 487 /* Horizontal sync pulse (hsync_end - hsync_start). */ 488 # define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10) 489 # define VC4_HDMI_HORZB_HSP_SHIFT 10 490 /* Horizontal front porch (hsync_start - hdisplay). */ 491 # define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0) 492 # define VC4_HDMI_HORZB_HFP_SHIFT 0 493 494 #define VC4_HDMI_FIFO_CTL 0x05c 495 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14) 496 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13) 497 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7) 498 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6) 499 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5) 500 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4) 501 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3) 502 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2) 503 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1) 504 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0) 505 # define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff 506 507 #define VC4_HDMI_SCHEDULER_CONTROL 0x0c0 508 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15) 509 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5) 510 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3) 511 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1) 512 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0) 513 514 #define VC4_HDMI_VERTA0 0x0cc 515 #define VC4_HDMI_VERTA1 0x0d4 516 /* Vertical sync pulse (vsync_end - vsync_start). */ 517 # define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20) 518 # define VC4_HDMI_VERTA_VSP_SHIFT 20 519 /* Vertical front porch (vsync_start - vdisplay). */ 520 # define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13) 521 # define VC4_HDMI_VERTA_VFP_SHIFT 13 522 /* Vertical active lines (vdisplay). */ 523 # define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 524 # define VC4_HDMI_VERTA_VAL_SHIFT 0 525 526 #define VC4_HDMI_VERTB0 0x0d0 527 #define VC4_HDMI_VERTB1 0x0d8 528 /* Vertical sync pulse offset (for interlaced) */ 529 # define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9) 530 # define VC4_HDMI_VERTB_VSPO_SHIFT 9 531 /* Vertical pack porch (vtotal - vsync_end). */ 532 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0) 533 # define VC4_HDMI_VERTB_VBP_SHIFT 0 534 535 #define VC4_HDMI_CEC_CNTRL_1 0x0e8 536 /* Set when the transmission has ended. */ 537 # define VC4_HDMI_CEC_TX_EOM BIT(31) 538 /* If set, transmission was acked on the 1st or 2nd attempt (only one 539 * retry is attempted). If in continuous mode, this means TX needs to 540 * be filled if !TX_EOM. 541 */ 542 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30) 543 # define VC4_HDMI_CEC_RX_EOM BIT(29) 544 # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28) 545 /* Number of bytes received for the message. */ 546 # define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24) 547 # define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24 548 /* Sets continuous receive mode. Generates interrupt after each 8 549 * bytes to signal that RX_DATA should be consumed, and at RX_EOM. 550 * 551 * If disabled, maximum 16 bytes will be received (including header), 552 * and interrupt at RX_EOM. Later bytes will be acked but not put 553 * into the RX_DATA. 554 */ 555 # define VC4_HDMI_CEC_RX_CONTINUE BIT(23) 556 # define VC4_HDMI_CEC_TX_CONTINUE BIT(22) 557 /* Set this after a CEC interrupt. */ 558 # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21) 559 /* Starts a TX. Will wait for appropriate idel time before CEC 560 * activity. Must be cleared in between transmits. 561 */ 562 # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20) 563 # define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16) 564 # define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16 565 /* Device's CEC address */ 566 # define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12) 567 # define VC4_HDMI_CEC_ADDR_SHIFT 12 568 /* Divides off of HSM clock to generate CEC bit clock. */ 569 /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */ 570 # define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0) 571 # define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0 572 573 /* Set these fields to how many bit clock cycles get to that many 574 * microseconds. 575 */ 576 #define VC4_HDMI_CEC_CNTRL_2 0x0ec 577 # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24) 578 # define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24 579 # define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17) 580 # define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17 581 # define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11) 582 # define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11 583 # define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5) 584 # define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5 585 # define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0) 586 # define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0 587 588 #define VC4_HDMI_CEC_CNTRL_3 0x0f0 589 # define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24) 590 # define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24 591 # define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16) 592 # define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16 593 # define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8) 594 # define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8 595 # define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0) 596 # define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0 597 598 #define VC4_HDMI_CEC_CNTRL_4 0x0f4 599 # define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24) 600 # define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24 601 # define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16) 602 # define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16 603 # define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8) 604 # define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8 605 # define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0) 606 # define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0 607 608 #define VC4_HDMI_CEC_CNTRL_5 0x0f8 609 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27) 610 # define VC4_HDMI_CEC_RX_SW_RESET BIT(26) 611 # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25) 612 # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24) 613 # define VC4_HDMI_CEC_RX_CEC_INT BIT(23) 614 # define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16) 615 # define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16 616 # define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8) 617 # define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8 618 # define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0) 619 # define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0 620 621 /* Transmit data, first byte is low byte of the 32-bit reg. MSB of 622 * each byte transmitted first. 623 */ 624 #define VC4_HDMI_CEC_TX_DATA_1 0x0fc 625 #define VC4_HDMI_CEC_TX_DATA_2 0x100 626 #define VC4_HDMI_CEC_TX_DATA_3 0x104 627 #define VC4_HDMI_CEC_TX_DATA_4 0x108 628 #define VC4_HDMI_CEC_RX_DATA_1 0x10c 629 #define VC4_HDMI_CEC_RX_DATA_2 0x110 630 #define VC4_HDMI_CEC_RX_DATA_3 0x114 631 #define VC4_HDMI_CEC_RX_DATA_4 0x118 632 633 #define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0 634 635 #define VC4_HDMI_TX_PHY_CTL0 0x2c4 636 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25) 637 638 /* Interrupt status bits */ 639 #define VC4_HDMI_CPU_STATUS 0x340 640 #define VC4_HDMI_CPU_SET 0x344 641 #define VC4_HDMI_CPU_CLEAR 0x348 642 # define VC4_HDMI_CPU_CEC BIT(6) 643 # define VC4_HDMI_CPU_HOTPLUG BIT(0) 644 645 #define VC4_HDMI_CPU_MASK_STATUS 0x34c 646 #define VC4_HDMI_CPU_MASK_SET 0x350 647 #define VC4_HDMI_CPU_MASK_CLEAR 0x354 648 649 #define VC4_HDMI_GCP(x) (0x400 + ((x) * 0x4)) 650 #define VC4_HDMI_RAM_PACKET(x) (0x400 + ((x) * 0x24)) 651 #define VC4_HDMI_PACKET_STRIDE 0x24 652 653 #define VC4_HD_M_CTL 0x00c 654 /* Debug: Current receive value on the CEC pad. */ 655 # define VC4_HD_CECRXD BIT(9) 656 /* Debug: Override CEC output to 0. */ 657 # define VC4_HD_CECOVR BIT(8) 658 # define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6) 659 # define VC4_HD_M_RAM_STANDBY (3 << 4) 660 # define VC4_HD_M_SW_RST BIT(2) 661 # define VC4_HD_M_ENABLE BIT(0) 662 663 #define VC4_HD_MAI_CTL 0x014 664 /* Set when audio stream is received at a slower rate than the 665 * sampling period, so MAI fifo goes empty. Write 1 to clear. 666 */ 667 # define VC4_HD_MAI_CTL_DLATE BIT(15) 668 # define VC4_HD_MAI_CTL_BUSY BIT(14) 669 # define VC4_HD_MAI_CTL_CHALIGN BIT(13) 670 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12) 671 # define VC4_HD_MAI_CTL_FULL BIT(11) 672 # define VC4_HD_MAI_CTL_EMPTY BIT(10) 673 # define VC4_HD_MAI_CTL_FLUSH BIT(9) 674 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing 675 * through. 676 */ 677 # define VC4_HD_MAI_CTL_PAREN BIT(8) 678 # define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4) 679 # define VC4_HD_MAI_CTL_CHNUM_SHIFT 4 680 # define VC4_HD_MAI_CTL_ENABLE BIT(3) 681 /* Underflow error status bit, write 1 to clear. */ 682 # define VC4_HD_MAI_CTL_ERRORE BIT(2) 683 /* Overflow error status bit, write 1 to clear. */ 684 # define VC4_HD_MAI_CTL_ERRORF BIT(1) 685 /* Single-shot reset bit. Read value is undefined. */ 686 # define VC4_HD_MAI_CTL_RESET BIT(0) 687 688 #define VC4_HD_MAI_THR 0x018 689 # define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24) 690 # define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24 691 # define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16) 692 # define VC4_HD_MAI_THR_PANICLOW_SHIFT 16 693 # define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8) 694 # define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8 695 # define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0) 696 # define VC4_HD_MAI_THR_DREQLOW_SHIFT 0 697 698 /* Format header to be placed on the MAI data. Unused. */ 699 #define VC4_HD_MAI_FMT 0x01c 700 701 /* Register for DMAing in audio data to be transported over the MAI 702 * bus to the Falcon core. 703 */ 704 #define VC4_HD_MAI_DATA 0x020 705 706 /* Divider from HDMI HSM clock to MAI serial clock. Sampling period 707 * converges to N / (M + 1) cycles. 708 */ 709 #define VC4_HD_MAI_SMP 0x02c 710 # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8) 711 # define VC4_HD_MAI_SMP_N_SHIFT 8 712 # define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0) 713 # define VC4_HD_MAI_SMP_M_SHIFT 0 714 715 #define VC4_HD_VID_CTL 0x038 716 # define VC4_HD_VID_CTL_ENABLE BIT(31) 717 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30) 718 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29) 719 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28) 720 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27) 721 722 #define VC4_HD_CSC_CTL 0x040 723 # define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5) 724 # define VC4_HD_CSC_CTL_ORDER_SHIFT 5 725 # define VC4_HD_CSC_CTL_ORDER_RGB 0 726 # define VC4_HD_CSC_CTL_ORDER_BGR 1 727 # define VC4_HD_CSC_CTL_ORDER_BRG 2 728 # define VC4_HD_CSC_CTL_ORDER_GRB 3 729 # define VC4_HD_CSC_CTL_ORDER_GBR 4 730 # define VC4_HD_CSC_CTL_ORDER_RBG 5 731 # define VC4_HD_CSC_CTL_PADMSB BIT(4) 732 # define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2) 733 # define VC4_HD_CSC_CTL_MODE_SHIFT 2 734 # define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0 735 # define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1 736 # define VC4_HD_CSC_CTL_MODE_CUSTOM 3 737 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1) 738 # define VC4_HD_CSC_CTL_ENABLE BIT(0) 739 740 #define VC4_HD_CSC_12_11 0x044 741 #define VC4_HD_CSC_14_13 0x048 742 #define VC4_HD_CSC_22_21 0x04c 743 #define VC4_HD_CSC_24_23 0x050 744 #define VC4_HD_CSC_32_31 0x054 745 #define VC4_HD_CSC_34_33 0x058 746 747 #define VC4_HD_FRAME_COUNT 0x068 748 749 /* HVS display list information. */ 750 #define HVS_BOOTLOADER_DLIST_END 32 751 752 enum hvs_pixel_format { 753 /* 8bpp */ 754 HVS_PIXEL_FORMAT_RGB332 = 0, 755 /* 16bpp */ 756 HVS_PIXEL_FORMAT_RGBA4444 = 1, 757 HVS_PIXEL_FORMAT_RGB555 = 2, 758 HVS_PIXEL_FORMAT_RGBA5551 = 3, 759 HVS_PIXEL_FORMAT_RGB565 = 4, 760 /* 24bpp */ 761 HVS_PIXEL_FORMAT_RGB888 = 5, 762 HVS_PIXEL_FORMAT_RGBA6666 = 6, 763 /* 32bpp */ 764 HVS_PIXEL_FORMAT_RGBA8888 = 7, 765 766 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8, 767 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9, 768 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10, 769 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11, 770 }; 771 772 /* Note: the LSB is the rightmost character shown. Only valid for 773 * HVS_PIXEL_FORMAT_RGB8888, not RGB888. 774 */ 775 #define HVS_PIXEL_ORDER_RGBA 0 776 #define HVS_PIXEL_ORDER_BGRA 1 777 #define HVS_PIXEL_ORDER_ARGB 2 778 #define HVS_PIXEL_ORDER_ABGR 3 779 780 #define HVS_PIXEL_ORDER_XBRG 0 781 #define HVS_PIXEL_ORDER_XRBG 1 782 #define HVS_PIXEL_ORDER_XRGB 2 783 #define HVS_PIXEL_ORDER_XBGR 3 784 785 #define HVS_PIXEL_ORDER_XYCBCR 0 786 #define HVS_PIXEL_ORDER_XYCRCB 1 787 #define HVS_PIXEL_ORDER_YXCBCR 2 788 #define HVS_PIXEL_ORDER_YXCRCB 3 789 790 #define SCALER_CTL0_END BIT(31) 791 #define SCALER_CTL0_VALID BIT(30) 792 793 #define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24) 794 #define SCALER_CTL0_SIZE_SHIFT 24 795 796 #define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20) 797 #define SCALER_CTL0_TILING_SHIFT 20 798 #define SCALER_CTL0_TILING_LINEAR 0 799 #define SCALER_CTL0_TILING_64B 1 800 #define SCALER_CTL0_TILING_128B 2 801 #define SCALER_CTL0_TILING_256B_OR_T 3 802 803 #define SCALER_CTL0_HFLIP BIT(16) 804 #define SCALER_CTL0_VFLIP BIT(15) 805 806 #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13) 807 #define SCALER_CTL0_ORDER_SHIFT 13 808 809 #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8) 810 #define SCALER_CTL0_SCL1_SHIFT 8 811 812 #define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5) 813 #define SCALER_CTL0_SCL0_SHIFT 5 814 815 #define SCALER_CTL0_SCL_H_PPF_V_PPF 0 816 #define SCALER_CTL0_SCL_H_TPZ_V_PPF 1 817 #define SCALER_CTL0_SCL_H_PPF_V_TPZ 2 818 #define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3 819 #define SCALER_CTL0_SCL_H_PPF_V_NONE 4 820 #define SCALER_CTL0_SCL_H_NONE_V_PPF 5 821 #define SCALER_CTL0_SCL_H_NONE_V_TPZ 6 822 #define SCALER_CTL0_SCL_H_TPZ_V_NONE 7 823 824 /* Set to indicate no scaling. */ 825 #define SCALER_CTL0_UNITY BIT(4) 826 827 #define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0) 828 #define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0 829 830 #define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24) 831 #define SCALER_POS0_FIXED_ALPHA_SHIFT 24 832 833 #define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12) 834 #define SCALER_POS0_START_Y_SHIFT 12 835 836 #define SCALER_POS0_START_X_MASK VC4_MASK(11, 0) 837 #define SCALER_POS0_START_X_SHIFT 0 838 839 #define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16) 840 #define SCALER_POS1_SCL_HEIGHT_SHIFT 16 841 842 #define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0) 843 #define SCALER_POS1_SCL_WIDTH_SHIFT 0 844 845 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30) 846 #define SCALER_POS2_ALPHA_MODE_SHIFT 30 847 #define SCALER_POS2_ALPHA_MODE_PIPELINE 0 848 #define SCALER_POS2_ALPHA_MODE_FIXED 1 849 #define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2 850 #define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3 851 #define SCALER_POS2_ALPHA_PREMULT BIT(29) 852 853 #define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16) 854 #define SCALER_POS2_HEIGHT_SHIFT 16 855 856 #define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0) 857 #define SCALER_POS2_WIDTH_SHIFT 0 858 859 /* Color Space Conversion words. Some values are S2.8 signed 860 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1, 861 * 0x2: 2, 0x3: -1} 862 */ 863 /* bottom 8 bits of S2.8 contribution of Cr to Blue */ 864 #define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24) 865 #define SCALER_CSC0_COEF_CR_BLU_SHIFT 24 866 /* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */ 867 #define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16) 868 #define SCALER_CSC0_COEF_YY_OFS_SHIFT 16 869 /* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */ 870 #define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8) 871 #define SCALER_CSC0_COEF_CB_OFS_SHIFT 8 872 /* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */ 873 #define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0) 874 #define SCALER_CSC0_COEF_CR_OFS_SHIFT 0 875 #define SCALER_CSC0_ITR_R_601_5 0x00f00000 876 #define SCALER_CSC0_ITR_R_709_3 0x00f00000 877 #define SCALER_CSC0_JPEG_JFIF 0x00000000 878 879 /* S2.8 contribution of Cb to Green */ 880 #define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22) 881 #define SCALER_CSC1_COEF_CB_GRN_SHIFT 22 882 /* S2.8 contribution of Cr to Green */ 883 #define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12) 884 #define SCALER_CSC1_COEF_CR_GRN_SHIFT 12 885 /* S2.8 contribution of Y to all of RGB */ 886 #define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2) 887 #define SCALER_CSC1_COEF_YY_ALL_SHIFT 2 888 /* top 2 bits of S2.8 contribution of Cr to Blue */ 889 #define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0) 890 #define SCALER_CSC1_COEF_CR_BLU_SHIFT 0 891 #define SCALER_CSC1_ITR_R_601_5 0xe73304a8 892 #define SCALER_CSC1_ITR_R_709_3 0xf2b784a8 893 #define SCALER_CSC1_JPEG_JFIF 0xea34a400 894 895 /* S2.8 contribution of Cb to Red */ 896 #define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20) 897 #define SCALER_CSC2_COEF_CB_RED_SHIFT 20 898 /* S2.8 contribution of Cr to Red */ 899 #define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10) 900 #define SCALER_CSC2_COEF_CR_RED_SHIFT 10 901 /* S2.8 contribution of Cb to Blue */ 902 #define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10) 903 #define SCALER_CSC2_COEF_CB_BLU_SHIFT 10 904 #define SCALER_CSC2_ITR_R_601_5 0x00066204 905 #define SCALER_CSC2_ITR_R_709_3 0x00072a1c 906 #define SCALER_CSC2_JPEG_JFIF 0x000599c5 907 908 #define SCALER_TPZ0_VERT_RECALC BIT(31) 909 #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8) 910 #define SCALER_TPZ0_SCALE_SHIFT 8 911 #define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0) 912 #define SCALER_TPZ0_IPHASE_SHIFT 0 913 #define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0) 914 #define SCALER_TPZ1_RECIP_SHIFT 0 915 916 /* Skips interpolating coefficients to 64 phases, so just 8 are used. 917 * Required for nearest neighbor. 918 */ 919 #define SCALER_PPF_NOINTERP BIT(31) 920 /* Replaes the highest valued coefficient with one that makes all 4 921 * sum to unity. 922 */ 923 #define SCALER_PPF_AGC BIT(30) 924 #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8) 925 #define SCALER_PPF_SCALE_SHIFT 8 926 #define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0) 927 #define SCALER_PPF_IPHASE_SHIFT 0 928 929 #define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0) 930 #define SCALER_PPF_KERNEL_OFFSET_SHIFT 0 931 #define SCALER_PPF_KERNEL_UNCACHED BIT(31) 932 933 /* PITCH0/1/2 fields for raster. */ 934 #define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0) 935 #define SCALER_SRC_PITCH_SHIFT 0 936 937 /* PITCH0 fields for T-tiled. */ 938 #define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16) 939 #define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16 940 #define SCALER_PITCH0_TILE_LINE_DIR BIT(15) 941 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14) 942 /* Y offset within a tile. */ 943 #define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 7) 944 #define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 7 945 #define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0) 946 #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0 947 948 #endif /* VC4_REGS_H */ 949